JPH0421044A - One-chip cache memory - Google Patents

Abstract

PURPOSE:To obtain a high hit rate by providing a pre-fetch means for deciding a bus access type, and executing a pre-fetch of the number of times which is set at every bus access type. CONSTITUTION:A directory 3 and a block load buffer 4 are referred to by a CPU address 2, and in the case of a cache miss, use of a memory bus is requested through a system bus interface 7, and data is fetched from a main memory. In this case, while the memory bus is being accessed, a pre-fetcher 11 refers to the next block of the directory 3, and in the case of a cache miss, a bus use request is outputted to the system bus interface 7 and a fetch of the next block is executed. Subsequently, by a bus access type signal 12 received together with the CPU address 2, the number of pre-fetch blocks is varied. In such a way, by setting the corresponding optimal pre-fetch blocks at every bus access type, a high hit rate can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to an improvement in a one-chip cache memory.

[Conventional technology]

Figure 2 shows, for example, the article "1-chip cache memory μPD436" published in the August 19B7 issue of the magazine "Interface J" published by CQ Publishing Co., Ltd., pp.241-257.
FIG. 2 is a block diagram showing the configuration of a conventional one-chip cache memory shown in "Overview and Utilization of 08R".

Figure 3 shows the one-chip cache memory μ shown in Figure 2.
It is a diagram showing a memory block configuration of PD43608R.

In FIG. 2, 2 is a CPU address, 3 is a directory, 4 is a block load buffer, 5 is a data block, 6 is CPU data, 7 is a system bus interface, 8 is a block address generator, 9 is an input latch, 10 is a bypass buffer, 11 is a brief fetcher,
13 is CPU bus interface, 14 is LRU
(Least Recently Used).

Next, the operation will be explained. A one-chip cache memory stores data in main memory in response to a request from a CPU, and reads/writes the data at high speed in place of the main memory when accessed by the CPU. Memory access from the CPU has locality, and data stored in the cache memory upon request from the CPU is highly likely to be accessed again in the near future.

In addition, there is a high possibility that data near the accessed data will be accessed again. Therefore, once the accessed data and the data near it are stored in the cache memory, data is exchanged between the CPU and the cache memory. Therefore, high-speed memory access by the CPU is realized.

When the CPU accesses the 1-chip cache memory, if data exists, it is called a cache hit, and if data does not exist, it is called a cache miss. In the case of Catschcht,
Data is read from cache memory at high speed. In the case of a cache miss, a data block containing the word requested by the CPU is fetched from the main memory into the cache memory (fetch operation) in preparation for the next CPU access. This block of data, which is the unit of information transfer between cache memory and main memory, is called a block.
This size is called the block size.

If there is no free space in the cache memory to store that block, one of the existing old blocks is evicted (replace operation).

Next, the memory configuration and operation of a conventional one-chip cache memory will be explained. FIG. 3 shows data block 5. of FIG. 2. Directory 3. A data block 5, which shows a four-way set associative memory configuration consisting of three blocks of the LRU 14, is a memory section that holds data in the main memory.

The directory 3 consists of an address tag that is a storage location for an address corresponding to each data block and a valid pit that indicates whether the stored data is valid or invalid. LRU1
4 stores information on how old each 4-way data was accessed from the CPU.

The CPU accesses data in memory blocks using addresses. As shown in FIG. 3, the access address includes the above-mentioned address tag, a set select indicating the address within the data block loaded from main memory to the cache,
It is divided into three parts: word select, which is word selection information for a data block. Address tags and valid pits are selected and read from the directory by access address set selection. Similarly, a block is selected from the data blocks and read out. The address tag, which is the upper part of the access address, is compared with the contents of the address tag part in the directory selected by set select.

In the 4-way set associative method, up to four address tags are stored simultaneously for one set select. Therefore, when making a hit/miss determination, four address tags are simultaneously referenced and compared for a certain set selection.

The valid pit indicates the validity of each address tag stored in memory, and checks whether it is valid during hit/miss judgment.The four ways perform the same operation in parallel, and the address read from the directory is checked. The tag and the address tag part of the access address are compared simultaneously in four ways to determine hit/miss.On the other hand, the word of the read data block is selected by word select, and finally, from the hit determination, it is determined which way it is. One word is determined by receiving a way selection signal indicating whether or not the word has been hit.

Next, the fetch method will be explained. The 1-chip cache memory supports on-demand and brief-fetch-on-miss fetch algorithms. The on-demand method is a method in which the contents of the main memory are fetched block by block into the 1-chip cache memory when a certain block is needed (at the time of a cache miss). On the other hand, in the brifetch-on-miss method, after fetching the block that was accessed when a cache miss occurred, the cache hit/miss of the block next to the accessed block is checked, and if the next block is a cache miss, then the cache hit/miss is checked. This method also fetches blocks.

Hit rate is generally used to indicate the performance of cache memory. The hit rate is the probability that accessed data exists in the cache memory with respect to a memory access from the CPU.

[Problem to be solved by the invention]

Since the conventional 1-chimp cache memory is configured as described above, the number of blocks to be pre-fetched is fixed at one. By the way, in general programs, address continuity differs between data and instructions. Instructions have highly continuous addresses, so if you increase the number of briefetches, you can expect a high hit rate, but data has discrete addresses, so even if you increase the number of briefetches, you can't expect much improvement in the hit rate. To maximize system performance, the number of briefetch locks must be selected separately for data and instructions.

The present invention was made to solve the above-mentioned problems, and aims to provide a one-chip cache memory that can maximize system performance.

[Means to solve the problem]

The one-chip cache memory according to the present invention includes a brief fetch means for determining a bus access type and executing prefetching a preset number of times for each bus access type.

[Effect]

In the one-chip cache memory of this invention, the number of briefetch blocks is changed corresponding to each bus access type such as instruction and data, so the number of briefetch blocks is adjusted to the optimal number of briefetch blocks corresponding to each bus access type. You can get the hint rate.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows a one-chip cache memory according to an embodiment of the present invention, in which l is l-chip cache memory, 2 is a CPU address, 3 is a directory, 4 is a block load buffer, 5 is a data block, and 6 is a CPU data, 7 is a system bus interface, 8 is a block address generator, 9 is an input latch, 10 is a bypass buffer, 11 is a briefetch in progress, and 12 is a bus access type signal.

Further, FIG. 4 shows the bus access type of this embodiment.

Next, a read access operation of the one-chip cache memory 1 will be explained. 1-chip cache memory 1 is C
The directory 3 and the block load buffer 4 are referred to using the PU address 2, and if a cash hit is made here, the data is output from the data block 5 to the CPU data bus 6. To refer to block load buffer 4,
This is because the data is written to the data block 5 when one block of data is available in the block load buffer 4, so even if there is no data in the data block 5, there is a possibility that the data exists in the block load buffer 4. If there is a cache miss, a request is made to use the memory bus through the system bus interface 7, and when use of the memory bus is permitted, bus access is started and data is fetched from the main memory using the address generated by the block address generator 8. Fetch data from main memory is passed from input latch 9 to block load buffer 4 and bypass buffer 10. The bypass buffer 10 outputs the data to the CPtJ data bus 6 and notifies the CPU of completion of data output. Subsequently, the block load buffer 4 receives data, and when the data fetch for one block is completed, the data of the data block is updated using the address generated by the block address generator 8. Also, at this time, the briefetching 11 refers to the next block in the directory 3 while accessing the memory bus. If it is a cache hit, nothing is done, but if it is a cache miss, a bus usage request is sent to the system bus interface 7 to fetch the next block. At this time,
The number of briefetch blocks is changed by the bus access type signal 12 received along with the CPU address.

As shown in FIG. 4, if the bus access type is data, one block is briefetched, and if it is an instruction, two blocks are briefetched.

Bus access types other than instructions and data are not cached. Bus access types other than instructions and data include interrupt response cycles and coprocessor cycles. Finally, blocks corresponding to the set number of prefetch blocks are fetched and written to the data block 5 following the block that caused the cache miss.

After the prefetch is completed, the memory during one chip is again in a state where it accepts accesses, and accepts read accesses and write accesses.

〔Effect of the invention〕

As described above, according to the present invention, since the number of briefetch blocks in one chip cache memory is configured to vary depending on the bus access type,
It has the effect of gaining memory during chipping.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram of a 1-chip memory that is an embodiment of the present invention, FIG. 2 is a block configuration diagram of a conventional 1-chip cache memory, and FIG. 3 is a memory block diagram of a 1-chip cache memory shown in FIG. 2. The configuration diagram, FIG. 4, is a diagram showing bus access types of a one-chip cache memory that is an embodiment of the present invention. In FIG. 1, 1 is one chip cache memory, 2 is a CPU address, 3 is a directory, 4 is a block load buffer, 5 is a data block, 6 is CPU data,
7 is a system bus interface, 8 is a block address generator, 9 is an input latch, 10 is a bypass buffer, 11 is a briefetcher, 12 is a bus access type signal, 13 is a CPU bus interface, and 14 is an LRU. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) In a one-chip cache memory, means for holding a CPU access address and an address within a data block loaded from the main memory to the cache;
means for increasing a first set select in the access address to obtain a second set select; accessing the cache memory using the second set select, determining a hit or a miss; The present invention is characterized by comprising means for fetching data, means for determining a CPU bus access type, and means for changing the number of times the second set select is increased in accordance with the bus access of the CPU access address. 1-chip cache memory.