JPH0728701A - Computer system - Google Patents

Abstract

PURPOSE:To transfer the data at a high speed by providing a means which transfers the data on an area designated in a main storage to a cache memory and a means which stores the address of the area received by the cache memory. CONSTITUTION:When a reading instruction 111 is issued, a data block of a main storage 14 including the address (requested by a CPU 11) designated by the instruction 111 is transferred to a data storage 134. Then the address of the data block of the storage 134 holding the data is set at a data block register 12. Meanwhile an address of the storage 14 is designated with a writing instruction 112. Then the data on the data block pointed by the register 12 are written into the address of the storage 14 that is requested by the CPU 11. If the old data on the address requested by the CPU 11 is remained in the storage 134, the data are invalidated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system having a cache memory.

[0002]

2. Description of the Related Art A central processing unit (hereinafter, CPU) used in a recent electronic computer has an improved architecture.
Due to integration and mounting technologies such as VLSI, there is a trend toward higher performance and higher speed. The same applies to the main storage device used in such an electronic computer,
Further, there is a tendency for the capacity to be increased due to the integration technology of the storage elements used.

However, the operating speed of the CPU is several times faster than that of the main storage device, and there is a large gap between them in terms of performance. Therefore, it is known that if the CPU and the main storage device are directly connected, the performance of the entire system is deteriorated.

Therefore, generally, a cache memory which can be accessed faster than the main memory device is arranged between the CPU and the main memory device so as to make up for a gap between the operating speeds of the CPU and the main memory device. There is.

FIG. 2 is a block diagram showing the configuration of a conventional computer system. In FIG. 2, the cache memory 1
Reference numeral 2 indicates a portion of the data in the main memory device 14 that is temporarily retained.
4 has an address tag device 133 for recording the address on the upper side. When there is a data access request from the CPU 11 to the cache memory 12, the data block determination device 1
31 determines an area (data block) on the data storage device 134 that holds data in an area (hereinafter, referred to as a data block) including the requested data from the address of the requested data. The address determination device 132 compares the address tag of the data currently held in the data block obtained by the data block determination device and recorded in the address tag device 133 with the requested data address,
Determine if the requested data is on the data store 134.

The requested data is data storage device 134.
If it is above (cache hit), the CPU 11 can access the data in the data storage device 134 at high speed.
If the requested data is not in the data storage device 134 (cache miss), the data transfer device 135 transfers the data block including the requested data from the main storage device 14 to the data block determined by the data block determination device 131 ( Move-in), the address of the data transferred to the data block in the main storage device 14 is stored in the address tag device 133, and then the CPU 21 accesses the requested data stored in the data storage device 134.

FIG. 4 shows a basic data access processing flow when there is a data access request from the CPU. When the access request from the CPU is data reading, the data block determining device 131 first determines the data block to be used on the data storage device 134 from the access address (step 301). Next, the data held in the target data block is the CPU 21
Whether or not the data includes the data requested by the address tag and the CP stored in the address tag storage device 133.
Judgment is made from the request address of U (step 302). When the requested data does not exist in the target data block, it is judged whether or not there is any data in the target data block (step 303). If there is data that is not the requested data in the target data block, the data is stored in the main memory. It is checked whether it needs to be written back on the device (step 304), and if it needs to be written back, it is written back on the main memory (move out). Next, the data block including the data requested from the main memory device is moved into the target data block on the data memory device 134. Next, the address of the moved-in data in the main storage device is stored in the address tag storage device. The CPU reads the data held in the data storage device (step 401). Also,
The same applies when the access request from the CPU is a data write request, and the CPU writes to the data held in the data storage device (step 60).
2).

As described above, the CPU can access the cache memory that can be accessed at high speed and can access the data at high speed when the accessed data exists in the cache memory.

Further, when all the data included in the data block on the cache memory is rewritten when writing the data, the target data block is directly transferred without transferring the write destination data to the data block on the cache memory. There is also proposed a method for writing the address to the address and updating the address tag.

As a data writing method, the swap method in which data is written back to the main memory when the data blocks in the cache memory are exchanged has been described, but another method is to write the data blocks in the cache memory at the same time. There is a store-through method in which data is also written in the main storage device. With the store-through method, when erasing the data in the cache memory,
Since it is not necessary to write data to the main storage device, the processes 303, 304, and 305 in FIG. 4 are unnecessary.

[0011]

By using the cache memory as described above, when a cache hit occurs, C
The PU can access the data at high speed, and the program can be executed at high speed. However, in the case of a cache miss, it is necessary to transfer data from the main storage device to the cache memory, and it takes time to execute the program.

Therefore, in the computer system having the above-mentioned cache memory, when performing the data transfer processing for transferring the data in the first area on the main storage device to the second area on the main storage device, There is such a problem.

(1) In the data transfer process, if the transfer source data is not in the cache memory, it is moved in to the cache memory, and if the data of the transfer destination area is not in the cache memory, it is the transfer destination area. Data is moved into the cache memory, and then the transfer source data in the cache memory is transferred to the transfer destination area in the cache memory. As described above, it is necessary to temporarily hold the data of the transfer source address and the data of the transfer destination address in the cache memory, and the larger the amount of data to be transferred, the easier the cache miss occurs. Therefore, the data transfer process takes time.

(2) Depending on the address accessed by the program, the transfer source area and the transfer destination area in the main memory may use the same data block in the cache memory. In this case, after the transfer source data is moved in. ,
When moving in the data of the transfer destination address, be sure to
A cache miss occurs. Furthermore, if the data transfer unit is smaller than the data block in the cache memory, a cache miss occurs when reading the transfer source data and writing to the transfer destination area depending on the program access pattern, and one data block is being processed. Multiple cache misses occur. Therefore, when using such an identical data block, data transfer is
It may take longer than using different data blocks.

In order to solve these problems, the program determines which data block in the cache memory
It is difficult to fully understand the order of access and consider it when developing a program.

An object of the present invention is to provide a computer system which solves the problems in the prior art as described above and enables high speed data transfer.

[0017]

In order to achieve the above object, the present invention, in a computer system having a cache memory, transfers data in a designated area on a main storage device to the cache memory and transfers the data. Means for returning the address of the area on the cache memory and means for transferring the data of the specified area on the cache memory to the specified area on the main memory are provided.

[0018]

In the computer system of the present invention, when data is transferred from the first area to the second area on the main memory,
First, it is checked whether the data in the first area in the main memory exists in the cache memory (cache hit).

Next, when there is no cache hit (cache miss), it is necessary to write back the existing data in the main memory device to the area on the cache memory to which the data in the first area is transferred. Find out.

Next, if it is necessary to write back the data existing in the cache memory to the main storage device, the data is written back to the main storage device.

Next, the data in the first area on the main memory is transferred to the cache memory, and the data in the designated area on the main memory is transferred to the cache memory. The returning means transfers the data to the cache memory and stores the transferred area on the cache memory.

Next, the means for transferring the data in the designated area in the cache memory to the designated area in the main storage device stores the data in the area in the cache memory stored in the above process in the main storage device. Transfer to the second area of.

As described above, according to the computer system of the present invention, the data transfer processing for transferring the data in the first area on the main storage device to the second area on the main storage device is performed on the main storage device. This can be realized by using only the area on the cache memory that temporarily holds the transfer source area. As a result, the conventional problems can be solved and high-speed data transfer can be realized.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the system configuration of the same embodiment. In FIG. 1, 11 is a CPU, 12 is a data block register having an address of a data block of the data storage device 132, 14 is a main storage device, 13
Reference numeral 1 is a data block determination device that determines a data block in which requested data is held from a data address requested by the CPU 11, 134 is a data storage device that temporarily holds data in the main storage device 14, and 133 is a data storage device 134. Address tag storage device for storing the address of the data held by the main storage device 14, 135 is a data transfer device for transferring data between the data storage device 134 and the main storage device 132, and 132 is requested by the CPU Address determination for determining cache hit / miss by comparing the data address with the address on the main storage device of the data stored in the data block on the data storage device 134 determined by the data block determination device 131 from this data address Device, 13 is a data block determination device 1
31, address determination device 132, address tag storage device 133, data storage device 134, and data transfer device 135
The reference numeral 111 denotes a read instruction described later, and the reference numeral 112 denotes a write instruction described later.

The CPU 11 is the data block determining device 1
When an access request is issued to 31 and the result of the address determination device 131 indicates a cache hit, the data in the data storage device 134 is accessed. In the case of a cache miss, the operation is stopped until the requested data is transferred to the data storage device. After the requested data is transferred to the data storage device 134, the transferred data on the data storage device 134 is accessed.

The main memory 14 stores data used by the program and the program itself. Further, the main memory device is divided into blocks of the same size as the data block which is the management unit of the data memory device on the cache memory, and data transfer between the main memory device and the cache memory is executed in this unit. It has become so.

The read instruction 111 is designed to specify the address of the data included in the data block to be read. When a read command is issued, the address specified by the read command (address requested by the CPU)
The data block of the main memory device including the data of (1) is transferred to the data memory device 134, and the address of the data block on the data memory device 134 holding the data is set in the data block register 12.

The write command 112 is designed to specify an address on the main storage device. The data of the data block pointed to by the data block register is written to the address on the main storage device 14 requested by the CPU, and the old data of the address requested by the CPU is the data storage device 134.
If it remains, the data will be invalidated.

In the data block register 12, the address of the data block on the data storage device 134 to which the data has been transferred is set by the read instruction 111.

The data block determination device 131 is a CPU
Data storage device 134 to which a data block including data to be processed is transferred from the data address requested by
It is designed to ask for the data block above.

The address determination device 132 compares the access request address from the CPU with the address on the main memory 14 of the data of the data block obtained by the data block determination device 131 from this request address, and determines a cache hit / miss. It is designed to judge.

The address tag storage device 133 stores the address of the data held in the data storage device 134 on the main storage device 14 as tag data, and when the CPU issues an access request, the requested address is sent. The address on the main storage device of the data of the data block determined by the data block determining device is passed to the address determining device. Further, each data block in the data storage device has an invalid flag indicating whether the corresponding data block is valid or invalid and a dirty flag indicating that the data of the data block has been rewritten. The invalid flag is set when there is no data in the corresponding data block and when the corresponding data block is invalidated,
It is turned off when data is transferred to the corresponding data block. The dirty flag is set when the data of the corresponding data block is rewritten, and turned off when the data of the data block is newly transferred.

The data storage device 134 is adapted to temporarily hold the data in the data transfer main storage device 14, and the address of the held data in the main storage device is stored in the address tag storage device as tag data. It is supposed to be done.

If it is necessary for the data transfer device 135 to write back the data currently held in the data block in the data storage device to the main storage device when the address determination device determines that there is a cache miss, the data transfer device 135 The data is written back, and then the data block containing the data at the address requested by the CPU is transferred to the data block on the data storage device. Further, when the write command 112 is issued, the contents of the data block pointed to by the data block register are written back to the designated address on the main storage device. The unit of data transfer is the size of the data block on the data storage device.

FIG. 3 is a flow chart showing the operation of the read command 111 and the write command 112. The operation of the read command 111 and the write command 112 of this embodiment will be described below with reference to FIG.

When the read instruction 111 is issued, the data block of the requested address is transferred to the data storage device as follows. .

<Step 301> First, from the address specified by the read command, the data block determining device determines the data block on the data storage device that is the transfer destination.

<Step 302> Next, the tag data stored in the address tag storage device and the address specified by the read command are addressed to determine whether the data of the data block is the data specified by the read command. The judging device compares and judges the cache hit / miss. If there is a cache hit, the process proceeds to step 308, and if there is a cache miss, the process proceeds to step 303.

<Step 303> Next, it is judged from the tag data of the address tag storage device whether or not data other than the data block including the data of the address designated by the read command is stored in the data block,
If other data exists, the process proceeds to step 304. If no other data exists, the process proceeds to step 306.

<Step 304> Next, it is judged whether or not the data of the data block needs to be written back to the main memory. As a result, if there is a need to write back, to <step 305>, if there is no need to write back, step 3
Proceed to 06. This step is not necessary when the data writing method of this embodiment is the store-through method.

<Step 305> Next, the data transfer device writes the data of the data block back to the main storage device. This step is not necessary in the case of the store-through method like step 304.

<Step 306> Next, the data transfer device changes the data block in the main memory device containing the data of the address specified by the read instruction to the data block in the data memory device determined by the data block determination device. Forward.

<Step 307> Next, step 306
The address of the data block transferred in the main storage device is stored as tag data in the address tag storage device. Further, the invalid flag is cleared and the dirty flag is cleared.

<Step 308> Next, step 306
In the data block register, the address on the data storage device of the transferred data block is set.

When the write command 112 is issued, the data block of the requested address is transferred to the main storage device as follows. .

<Step 309> First, the data transfer device transfers the data of the data block in the data storage device indicated by the data block register to the address in the main storage device designated by the write command.

<Step 310> Next, it is judged whether or not the data block in the main storage device of the transfer destination exists in the data storage device. If it does not exist, nothing is done and the processing of the write command 112 ends. If there is, go to the next step 311.

<Step 311> Next, in order to invalidate the corresponding data block, the invalid flag of the corresponding data block in the address tag storage device is set.

Next, the operation of the data transfer process in the embodiment thus constructed will be described.

When the data in the data block A on the main memory is transferred to the data block B, the program uses a read instruction 111 (hereinafter, “bload”) and a write instruction 112 (hereinafter, “bwrite”). It is described as b (a is the address of the data block A, b is the address of the data block B).

When bload is issued, the data block determining device 131 determines the data block A'for storing the data of the data block A on the data storage device 134, and the data of the data block A is stored in the data block A '. Whether the address tag storage device 1 has already been transferred
The address determination device 132 determines by comparing the tag data corresponding to the 33 data block A ′ with the address a.

If there is a cache hit, the address of the data block A'is set in the data block register 12. On the other hand, if it is determined to be a cache miss and it is necessary to write back the data of the data block A ′ to the main storage device, the data transfer device 135 writes the data back to the main storage device. Then, the data of the data block A is transferred to the data block A ′ by the data transfer device 135, and the address on the main storage device of the transferred data is set to the address tag storage device corresponding to the data block A ′. Then, the address of the data block A'is set in the data block register 12.

When bwrite is issued after executing bload,
The data block register points to the data block A ', and the data transfer device 135 transfers the data of this data block A'to the data block B in the main memory device 14. Then, the data block B'in the data storage device 134 used by the transfer destination address b is obtained by the data block determination device 131, and it is judged whether or not the old data of the data block B exists in the data block B ', and it exists. If so, the data in the data block B'is invalidated. Invalidation is performed by setting an invalid flag on the address tag storage device 133 corresponding to the data block B '.

As described above, the data transfer from the data block A to the data block B can be realized by issuing the bload and bwrite. A cache miss occurs during this transfer process only when bload is issued and the data in the data block A (source data) is transferred to the data block in the data storage device 134.

In the above description, the data transfer process for transferring the data of one data block in the main memory device 14 to another data block in the main memory device has been described. The data transfer process of transferring the data of the data block to a plurality of continuous data blocks can also be realized by repeatedly performing the method described above for the number of data blocks to be transferred. Further, the data transfer process of transferring data from the transfer source data block in the main storage device 14 to the plurality of data blocks in the main storage device 14 can also be realized by repeatedly issuing the write command 112. The upper limit of the number of cache misses that occurs in these data transfer processes is equal to the number of times the data of the transfer source data block is transferred to the cache memory.

The present invention is not limited to the above-mentioned embodiments, and can be carried out by appropriately modifying it within the scope of the invention. For example, in the above-described embodiment, the read instruction 111
Although a data block register was prepared as a means for storing the address of the data block in the cache memory to which the data was transferred by this, even if this register is a dedicated register for storing the address of the data block in the cache memory, It may be a general-purpose register used for program execution in the system.

[0057]

According to the present invention, the data transfer process does not require the data block in the cache memory that has been conventionally used for writing the data of the transfer destination data block. The number of times the transfer source data is transferred to the cache memory can be suppressed. As a result, the data transfer process can be executed at high speed.

Further, since the data block on the cache memory which has been used conventionally for writing the data of the transfer destination data block is not required, there is an effect of reducing the probability of occurrence of cache miss in the entire system.

[Brief description of drawings]

FIG. 1 is a block diagram showing a system configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a system configuration of a conventional technique.

FIG. 3 is a flowchart showing a processing procedure of the embodiment shown in FIG.

FIG. 4 is a flowchart showing a processing procedure of the conventional technique of FIG.

[Explanation of symbols]

11 ... CPU, 12 ... Data block register, 13 ...
Cache memory, 14 ... Main storage device, 111 ... Read command, 112 ... Write command, 131 ... Data block determination device, 132 ... Address determination device, 133 ... Address tag storage device, 134 ... Data storage device, 135 ...
Data transfer device.

Claims (3)

[Claims] 1. A computer system having a cache memory, comprising means for transferring data in a designated area on a main storage device to the cache memory, and means for storing an address of the transferred area on the cache memory. A computer system characterized by having. 2. The computer system according to claim 1, further comprising means for transferring data in a designated area of the cache memory to a designated area of the main storage device. 3. The computer system according to claim 2, wherein the data in the cache memory is transferred to a plurality of areas in the main storage device.