JP2000347941A - Cache memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the effectiveness of a cache memory by making it possible to set a LRU(least recently used) priority so as to be an appropriate priority. SOLUTION: This cache memory device 1 is provided with a LRU priority deciding means 13 which derives the next LRU priority not by making the LRU priority of data best unconditionally but by using the current LRU priority of the data, the attribute of the data, an accessing means to the data, the state of a processor or all of them or a part of information about them in the case of recording or re-recording the data in a cache memory 20. A cache controlling means 11 records or re-records data as data having the LRU priority decided by the means 13 in the memory 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for controlling a cache memory. In particular, it is used to determine data to be evicted from cache memory.
The present invention relates to a device that contributes to increasing the effectiveness of a cache memory by actively operating the LRU priority using an LRU (Least Recently Used) method.

[0002]

2. Description of the Related Art Generally, a cache memory is located between a processor and a main memory. Of the data recorded in the main memory, data used by the processor in the past is recorded, and the processor re-stores the data. When using, transfer data to the processor instead of main memory.
The cache memory operates at high speed, so data transfer to the processor can be completed in a short time.
Smaller capacity than main memory. Therefore, if the data is recorded in the cache memory and the data can be transferred from the cache memory, the data waiting time of the processor can be reduced as compared with the case where the data is transferred from the main memory, and the processing time can be reduced. Processing performance can be improved.

In order to effectively utilize the capacity of the cache memory, data recorded in the cache memory is often managed by the LRU method. The LRU method is a method based on an empirical rule that "data used recently is more likely to be used again in the near future than data not used".

[0004] Since the cache memory has a smaller capacity than the main memory, it is often the case that new data cannot be recorded unless data already recorded is deleted. FIG. 17 shows an example in which data is newly recorded in the cache memory. When new data E is recorded in the cache memory, data A having the lowest LRU priority
Is evicted from the cache memory, and the new data E is LR
The U priority is recorded in the cache memory as the highest data.

In recent years, not only data used by the processor but also data that the processor will use from now on is recorded in the cache memory, so that the chance of transferring data from the cache memory to the processor is further increased. The method has been adopted.

A typical example of this method is prefetch. The prefetch is a method in which data is transferred from a main memory to a cache memory before the processor actually uses the data, and the data is recorded in the cache memory.

When prefetching is not performed, when the processor uses data that has never been used before, no data is recorded in the cache memory, and the data is transferred from the main memory. I have to wait. However, if prefetching is used, even in such a case, data can be recorded in the cache memory. If the data is recorded in the cache memory in advance by this prefetch, it is not necessary to wait for the data to be transferred from the main memory, so that the data waiting time of the processor can be further reduced and the performance can be improved.

[0008]

However, the prior art has the following problems.

(1) Problems caused by prefetch A method of recording data in a cache memory based on the possibility of use, instead of recording the data in a cache memory when the processor actually uses the data, such as prefetch, for example. It is possible that the processor may not actually use that data, in which case,
The data recorded in the cache memory wastefully uses the capacity of the cache memory.

FIG. 18 shows an example in which the effectiveness of a cache memory is impaired by prefetching. In FIG. 18, in the state where data D, data C, data B, and data A are recorded in the cache memory in descending order of the LRU priority, after prefetching data E, the processor sequentially executes data A, data B , Data C, and data D are shown.

By prefetching data E, data A having the lowest LRU priority is evicted from the cache memory, and in the next operation of data A, data A results in a cache miss hit. Further, at the time of fetching the data A for this operation, the data B having the lowest LRU priority is evicted from the cache, and a cache miss occurs even in the operation of the next data B. In this way, operations on data C and data D also result in cache misses. This is because the data to be operated next is expelled one after another by the prefetch of the data E, and the cache memory is polluted.

FIG. 19 shows an example in which a cache memory is effectively used without prefetch. In the example of FIG. 19, data D, data C,
In the state where the data B and the data A are recorded in the cache memory, the processor sequentially operates the data A, the data B, the data C, and the data D without prefetching the data E. The results of manipulating data A, data B, data C, and data D all result in cache hits.

When data obtained by prefetching or the like is simply recorded in the cache memory, not only the capacity of the cache memory is wasted, but also the effectiveness of the cache memory may be impaired.

As a method of avoiding this, there is a method of carefully selecting data to be recorded in the cache memory and not recording data which is unlikely to be used by the processor.
According to this method, although the possibility of impairing the effectiveness of the cache memory is reduced, an opportunity for performance improvement by speculative processing is missed.

There is also a method in which data is not recorded directly in the cache memory but is recorded in a small-capacity dedicated buffer, and the data is recorded in the cache memory when the processor actually uses the data. .
According to this method, the capacity of the cache memory is not wasted, but the control of the cache memory is complicated.

(2) Problems Due to Speculative Execution As another situation, there is a problem of updating a cache memory in a processor that performs speculative execution. The speculative execution method adopted by recent processors for high-speed execution has the same problem as the above-described prefetch case.

The speculative execution method executes a memory operation instruction that may not be executed speculatively, and prevents the influence caused by the execution result from being left when it is found that the instruction should not be executed later. Is returned to the state shown in FIG. However, regarding the LRU priority of the cache memory, a logical mistake does not occur even if the priority updated by the speculative execution is not restored, so even if the wrong speculative execution is performed. , LRU priority is not restored in most cases.

As a result, there is a problem that the cache memory area is unnecessarily occupied by data that is not actually used, or the LRU priority of other necessary data is lowered.

As a method for solving this problem, a so-called rollback method is known in which the state before speculative execution is saved, and if the speculative execution is found to be incorrect, the state is returned to the state before speculative execution. ing. However, this method has a problem that control for restoring the state is complicated.

(3) Problems Due to Data Attributes As another situation, the nature of data access is as follows.
It may be better to change the cache memory control method. For example, depending on the contents of the data processing, the memory may be sequentially referred to. A typical example is erasure of data in a memory area. When the amount of data to be erased exceeds the capacity of the cache memory, in the cache memory based on the LRU method, other data recorded in the cache memory before the start of erasure is sequentially removed from the cache memory as the erasure progresses. It is evicted and eventually all is evicted from the cache memory.

In such a case, there is a method of avoiding the problem by accessing the cache memory without passing through data. However, in the case of erasing a small amount of data and in the case of erasing a large amount of data, it is often difficult to control whether the cache memory is used or not, but it is difficult to control it. There is a problem.

Further, such sequential access is recognized,
When a special mark is given to the data recorded in the cache memory and the data is expelled from the cache memory, the LR
There is also known a method of determining data to be kicked out based on the information of the mark together with the U control. However, since an area for marking is required, the control becomes more complicated than simple LRU control. That is a problem.

The present invention solves the above-mentioned problem, and uses L to determine data to be evicted from the cache memory.
An object of the present invention is to increase the effectiveness of a cache memory by enabling the RU priority to be set to an appropriate priority when recording or re-recording data in the cache memory.

[0024]

FIG. 1 is a diagram showing an example of a block configuration for explaining the outline of the present invention. 1 is a cache memory device according to the present invention, 10 is a cache controller, 20 is a cache memory that holds data, 30 is a processor that operates (reads and writes) data,
Reference numeral 40 denotes a system bus. Reference numeral 11 denotes a cache control unit for controlling recording and re-recording of data in the cache memory 20, 12 denotes a derivation method setting unit, and 13 denotes an LR.
Represents U priority determination means.

When newly recording data in the cache memory 20 or when re-recording data due to a cache hit, the cache memory device 1 unconditionally sets the LRU priority of the data to the highest. Instead, the LRU priority that derives the next LRU priority using the current LRU priority of the data, the attribute of the data, the means for accessing the data, the state of the processor, or all or some of these information The LRU priority determination means 13 includes a LRU priority determination means 13.
Is recorded or re-recorded in the cache memory 20 as data having the determined LRU priority.

Here, the data LRU priority is used to determine the order in which data should be evicted from the cache memory 20 when the data needs to be evicted. Be kicked out first. Further, as the current LRU priority of data, it is assumed that data that is not in the cache memory 20 has LRU priority of “no priority”.

Normally, the fact that the data has the highest LRU priority means that the data is the most recently used data compared to other data, and that the data has the lowest LRU priority. , Which means that there is data that has been used in the past in comparison with other data, but this is not necessarily the case here. In this specification, in order to make the explanation easy to understand in comparison with the prior art, the LRU in the prior art is described.
Although the meaning is slightly different from the priority, the function is the same, so the term LRU priority is used.

The present invention also provides an LRU priority determining means 1
3, a derivation method setting means 12 for arbitrarily changing and setting a method used for deriving the next LRU priority is provided. When data is recorded in the cache memory 20, the LRU priority of the data is set. The priority is set to an appropriate priority according to the system using the cache memory device 1 or the program running at that time.

The cache controller 10 of the cache memory device 1 has the following configuration.

In the first example, in particular, an address analysis unit for determining the priority of data from the address of the data is provided, and the LRU priority determination means 13 records the data in the cache memory (including re-recording. The same applies to the following. ), The next LRU priority of the data is determined by using the priority of the data output from the address analysis unit and the current LRU priority of the data.

In the second example, especially when the processor 30 is a processor having a prefetch instruction, a prefetch identification unit for identifying whether or not the access from the processor 30 to the cache memory 20 is an access by the prefetch instruction. LRU priority determination means 13
When the data is recorded in the cache memory 20, the identification result of the prefetch identification unit and the current LR of the data are used.
The next LRU priority of the data is determined using the U priority.

In the third example, an address of data likely to be used by the processor 30 is predicted based on the access history of the processor 30 to the cache memory 20 so far, and the data at the address is prefetched. A LRU priority determination unit 13 having a prefetch control unit;
Determines the next LRU priority of the data by using whether or not the data is loaded by the prefetch control unit and the current LRU priority of the data when recording the data in the cache memory 20.

In the fourth example, the LRU priority determining means 1 is provided with an instruction identifying unit for identifying the type of an instruction which has issued an access from the processor 30 to the cache memory 20.
3 is for recording data in the cache memory 20;
The next LRU priority of the data is determined using the identification result of the instruction identification unit and the current LRU priority of the data.

In the fifth example, especially when the processor 30 has a speculative instruction execution function, an access from the processor 30 to the cache memory 20 occurs while the processor 30 executes the speculative instruction. An LRU priority determining means 13 includes a speculative execution identifying unit for identifying whether the access is an access or not. The next LRU priority of the data is determined using the priority.

In the sixth example, when a parallel computer is connected to a bus, the LRU priority determining means 13 determines, when another processor issues a request to the bus, the type of request issued by the other processor, Using the result of the snooping and the current LRU priority of the data, the next LRU of the data is used.
The priority is determined, and the data is recorded in the cache memory 20.

In the above example, when the LRU priority determining means 13 determines the next LRU priority of the data, the LRU priority is determined according to the method set by the derivation method setting means 12.
It can be configured to determine RU priority.

As described above, according to the present invention, when data that may not be used is recorded in the cache memory 20 by prefetching or speculative processing, it is possible to prevent the really necessary data from being evicted from the cache memory 20. And the effectiveness of the cache memory 20 is improved. Further, in the cache memory 20, L
Since the method of recording the RU priority is the same as the conventional one,
The storage capacity required to record the RU priority does not increase.

For example, when new data is recorded in the cache memory 20, the data is stored in the LR
The U priority is recorded as the highest data. If the data is obtained by prefetching, the LRU
The data with the lowest priority is recorded. As a result, even if the data obtained by the prefetch is
Even if 0 is not actually used, data is recorded in a state where it is easily evicted from the cache memory 20. Therefore, the ratio of wasting capacity of the cache memory 20 is reduced, and the possibility of losing effectiveness is reduced. .

Alternatively, in the case where sequential access is performed, it is unlikely that data once accessed will be referred to later. However, in order to access new data one after another, in the control by the conventional LRU method, the cache memory 20 is filled with the data obtained by the sequential access, and the other data recorded in the cache memory 20 is evicted. Would. Therefore,
According to the present invention, data obtained by sequential access is recorded, for example, assuming that the LRU priority is set to only the lowest priority and the next priority, so that the 4-way set associative cache memory is used. Then, it is possible to impose a limitation that data is recorded only in a range not exceeding 2/4 of the total cache memory capacity.

FIG. 2 is a diagram for explaining the operation principle of the present invention. In FIG. 2, as in the case shown in FIG. 18, data E is prefetched in a state where data D, data C, data B, and data A are recorded in the cache memory 20 in descending order of LRU priority. Later, processor 3
0 indicates an operation example when data A, data B, data C, and data D are sequentially operated. The difference from the operation in the case shown in FIG. 18 is that, in the present invention, the data E to be prefetched is recorded in the cache memory 20 as data having the lowest LRU priority.

As shown in FIG. 2, in the present invention, the data E
The LRU priority is set low and prefetch is performed. When prefetching the data E, the data A is evicted from the cache memory 20, and in the case of the next operation of the data A, the data A becomes a cache miss. However, by setting the LRU priority of the prefetched data E low, the LRU
The data E having the lower priority is evicted, and the next operation on the data B results in a cache hit. Subsequent operations on data C and data D also result in cache hits.

In the case shown in FIG. 18, it can be seen that the effectiveness of the cache memory 20 is improved by the present invention as compared with the case where all the operations result in cache misses.

[0043]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Several embodiments of the present invention will be described below in order.

(1) First Embodiment FIG. 3 is a block diagram of a first embodiment of the present invention. In this example, the cache controller 110 of the cache memory device 100 has an address analysis unit 114 that determines the priority of data from the address of the data.
And the next L based on the data priority and the current LRU priority
An LRU priority determining unit 116 that determines an RU priority is provided. The derivation method setting unit 118 is a means for setting a value in the range register 115 and the LRU priority table 117. As described later, the derivation method of the LRU priority can be changed by setting a value for this. In other words, what value the LRU priority is set to in what state can be changed by setting the values in the range register 115 and the LRU priority table 117.

The cache control management unit 112 is a part that performs main control in the cache controller 110, and controls recording (or re-recording) of data in the cache memory 120. The internal structure of the cache control management unit 112 is basically the same as the conventional one. The processor interface (processor IF) 111 is an interface for exchanging data and control signals between the processor 130 and the cache control management unit 112, and the bus interface (bus IF) 113 is connected to a main memory (system IF) via a system bus 140. (Not shown) for exchanging data and control signals.

When recording (or re-recording) data in the cache memory 120, first, the address analysis unit 114 determines the priority of the data. Specifically, the address analysis unit 114 includes a range register 115 which is a register set for recording an address range and a priority of the range.
Based on the value recorded in 5, the priority of the data is derived from the address of the data. The value recorded in the range register 115 can be set arbitrarily, or can be a predetermined value.

Next, the LRU priority determining section 116 determines the next LRU priority of the data. Specifically, LR
The U priority determining unit 116 refers to the LRU priority table 117 as shown in FIG.
7, the next LRU priority is determined from the current LRU priority and the priority of the data determined by the address analysis unit 114. Here, the LRU priority table 117 indicates that the priority of the data is high (Hig
h), a high LRU priority (= 3) is set irrespective of the current LRU priority, and if the data priority is medium (Middle), the current LRU priority (3, 2, 1, 1)
(3,2,1,1,1) is set in accordance with (0, none), and if the priority of data is low (Low), the current LRU priority (3, 2, 1, 0, none) is set. Depending on,
(3, 2, 1, 0, 0) is set. The values recorded in the LRU priority table 117 can be arbitrarily set by the derivation method setting unit 118. Alternatively, it may be a predetermined value. As a method of realizing the derivation method setting unit 118, for example, a method of setting a value at the time of initial setting or at the time of starting a program from the processor 130, or at the time of mounting the cache memory device 100 using a ROM
A method of incorporating the U priority table 117 is conceivable.

Finally, the cache control management unit 112
The data is recorded (or re-recorded) in the cache memory 120 as data having the LRU priority obtained by the above procedure.

(2) Second Embodiment FIG. 5 is a block diagram of a second embodiment of the present invention. In this example, the cache controller 210 of the cache memory device 200 has an address analysis unit 214 that determines the priority of data from the address of the data.
And the next L based on the data priority and the current LRU priority
An LRU priority determining unit 216 for determining an RU priority is provided. The derivation method setting unit 218 is means for setting a value in a part of the page table 215 and the LRU priority table 217. As described later, the derivation method of the LRU priority can be changed by setting a value for this. .

The cache control management unit 212 is a part that performs main control in the cache controller 210, and controls recording (or re-recording) of data in the cache memory 220. The internal structure of the cache control management unit 212 is basically the same as the conventional one. The processor interface (processor IF) 211 is an interface for exchanging data and control signals between the processor 230 and the cache control management unit 212. The bus interface (bus IF) 213 is connected to the main memory (system IF) via the system bus 240. (Not shown) for exchanging data and control signals.

When recording (or re-recording) data in the cache memory 220, first, the address analysis unit 214 determines the priority of the data. More specifically, each entry of the page table 215 is provided with a field indicating the priority of the page. The address analysis unit 214 searches the page table 215 and determines the priority of the page entry corresponding to the address of the data. The field value is the priority of the data. The priority value of the page entry can be set arbitrarily, or can be set to a predetermined value.

Next, the LRU priority determining section 216 determines the next LRU priority of the data. Specifically, LR
The U priority determining unit 216 refers to the LRU priority table 217 as shown in FIG.
7, the next LRU priority is determined from the current LRU priority and the priority of the data determined by the address analysis unit 214. Here, the LRU priority table 217 indicates that the priority of the data is high (Hig
h), a high LRU priority is set regardless of the current LRU priority, and the data priority is medium (Mid
dle), (2, 2, 1, 1, 1) is set according to the current LRU priority (3, 2, 1, 0, none), and if the data priority is low (Low), Depending on the LRU priority (3, 2, 1, 0, none), (1,1,
(1, 0, 0). In addition, LRU
The value recorded in the priority table 217 can be arbitrarily set by the derivation method setting unit 218. Alternatively, it may be a predetermined value. As a method of realizing the derivation method setting unit 218, for example, a method of setting a value at the time of initial setting or program startup from the processor 230, or a method of incorporating the LRU priority table 217 using a ROM or the like at the time of mounting the cache memory device 200 And so on.

Finally, the cache control management unit 212
The data is recorded (or re-recorded) in the cache memory 220 as data having the LRU priority obtained by the above procedure.

It is to be noted that not only a priority field indicating the priority of data is provided in the page table 215, but also a priority field is provided in a TLB (Translation Lookaside Buffer) used for speeding up the memory mapping of the virtual memory. By using this, it is possible to speed up LRU priority update similarly.

(3) Third Embodiment FIG. 7 is a block diagram of a third embodiment of the present invention. The processor 330 in this example is a device provided with an instruction for data prefetch in its instruction set.
The cache controller 310 of the cache memory device 300 includes a prefetch identification unit 314 for identifying whether the access is performed by a prefetch instruction, and an LRU for determining the next LRU priority from the identification result of the prefetch identification unit 314 and the current LRU priority of the data. A priority determining unit 316 is provided. The derivation method setting unit 318 is means for setting a value in the LRU priority table 317, and as described later,
By setting a value for this, the method of deriving the LRU priority can be changed.

The cache control management unit 312 is a part that performs main control in the cache controller 310, and controls recording (or re-recording) of data in the cache memory 320. The internal structure of the cache control management unit 312 is basically the same as the conventional one. The processor interface (processor IF) 311 is an interface for exchanging data and control signals between the processor 330 and the cache control management unit 312, and the bus interface (bus IF) 313 is connected to the main memory (system bus 340) via the system bus 340. (Not shown) for exchanging data and control signals.

When recording (or re-recording) data in the cache memory 320, first, the prefetch identification unit 314 determines whether the access to the data is
It is determined whether or not this is due to 30 prefetch instructions. Specifically, there is a signal line for notifying the cache memory device 300 of the access by the prefetch instruction or not from the processor 330, and the signal of the signal line allows the prefetch identification unit 314 to determine whether or not the access is by the prefetch instruction. Identify.

Next, the LRU priority determining section 316 determines the next LRU priority of the data. Specifically, LRU
For example, the priority determining unit 316 performs LRU as shown in FIG.
With reference to the priority table 317, the next LRU priority is determined from the current LRU priority and the identification result of the prefetch identification unit 314 based on the value recorded in the LRU priority table 317.

Here, the LRU priority table 317
Is the current L if the access is for a prefetch instruction.
Set the LRU priority according to the RU priority (however, if there is no priority, the lowest priority = 0), and if the access is not a prefetch instruction, the LRU priority is high regardless of the current LRU priority. The degree is set. Note that the values recorded in the LRU priority table 317 can be arbitrarily set by the derivation method setting unit 318. Alternatively, it may be a predetermined value. As a method of realizing the derivation method setting unit 318, for example, a method of setting a value at the time of initial setting or starting of a program from the processor 330, or a method of incorporating the LRU priority table 317 using a ROM or the like at the time of mounting the cache memory device 300 And so on.

Finally, the cache control management unit 312
The data is recorded (or re-recorded) in the cache memory 320 as data having the LRU priority obtained by the above procedure.

(4) Fourth Embodiment FIG. 9 is a block diagram of a fourth embodiment of the present invention. In the present example, the cache controller 410 of the cache memory device 400 executes a prefetch control unit 414 that executes prefetching of data prior to the processor 430.
And an address prediction unit 415 for determining the address of the data to be prefetched, and an LRU priority determination unit 416 for determining the next LRU priority of the data. The derivation method setting unit 418 is means for setting a value in the LRU priority table 417. As described later, the derivation method of the LRU priority can be changed by setting a value for this.

The cache control management unit 412 is a part that performs main control in the cache controller 410, and controls recording (or re-recording) of data in the cache memory 420. The internal structure of the cache control management unit 412 is basically the same as the conventional one. A processor interface (processor IF) 411 is an interface for exchanging data and control signals between the processor 430 and the cache control management unit 412, and a bus interface (bus IF) 413 is connected to a main memory (system IF) via a system bus 440. (Not shown) for exchanging data and control signals.

The address prediction unit 415 determines the address of the data to be pre-read based on the access history of the processor 430 so far. Prefetch control unit 414
Determines and executes whether or not the data of the address derived by the address prediction unit 415 should be read ahead.

Access of the processor 430, or
When data is recorded (or re-recorded) in the cache memory 420 by the access of the prefetch control unit 414, the LRU priority determination unit 416 determines the next LRU of the data.
Determine priority. Specifically, the LRU priority determination unit 4
16 is an LRU priority table 41 as shown in FIG.
7, the current LRU priority and the prefetch control unit 41 based on the value recorded in the LRU priority table 417.
Then, the next LRU priority is determined from the information indicating whether or not the access is made by prefetching from L4. Here, LRU
In the priority table 417, when the access is performed by the prefetch control unit 414, the LRU priority according to the current LRU priority (however, if there is no priority, the lowest priority = 0) is set. When the access is not by the control unit 414, a high LRU priority is set regardless of the current LRU priority.

Note that the values recorded in the LRU priority table 417 can be arbitrarily set by the derivation method setting unit 418. Alternatively, it may be a predetermined value. As a method of realizing the derivation method setting unit 418, for example, a method of setting a value at the time of initial setting or program startup from the processor 430, or a method of incorporating the LRU priority table 417 using a ROM or the like at the time of mounting the cache memory device 400 And so on.

Finally, the cache control management unit 412
The data is recorded (or re-recorded) in the cache memory 420 as data having the LRU priority obtained by the above procedure.

(5) Fifth Embodiment FIG. 11 is a block diagram of a fifth embodiment of the present invention. In this example, the processor 530 sends out-of-of-
It has a speculative instruction execution unit 531 that executes in order. Cache controller 5 of cache memory device 500
In particular, the LRU 10 includes a speculative execution identifying unit 514 for identifying whether an access is being performed during speculative instruction execution and an LRU priority determining unit 516 for determining the next LRU priority. The derivation method setting unit 518 is a unit that sets a value in the LRU priority table 517. As described later, the derivation method of the LRU priority can be changed by setting a value for this.

The cache control management unit 512 is a part for performing main control in the cache controller 510, and controls recording (or re-recording) of data in the cache memory 520. The internal structure of the cache control management unit 512 is basically the same as the conventional one. A processor interface (processor IF) 511 is an interface for exchanging data and control signals between the processor 530 and the cache control management unit 512, and a bus interface (bus IF) 513 is provided via a system bus 540 for main storage ( (Not shown) for exchanging data and control signals.

When recording (or re-recording) data in the cache memory 520, first, the speculative execution identifying unit 514 determines whether or not the access to the data is an access issued during execution of the speculative instruction by the processor. Identify. Specifically, the processor 530 sends the cache memory device 5
00, there is a signal line for notifying whether or not the speculative instruction is being executed, and the speculative execution identifying unit 514 determines whether or not the access has occurred during the execution of the speculative instruction based on the signal of the signal line. I do.

Next, the LRU priority determining section 516 determines the next LRU priority of the data. Specifically, LRU
The priority determining unit 516 refers to the LRU priority table 517 as shown in FIG.
7, the next LRU priority value is determined from the current LRU priority and the result of identification by the speculative execution identification unit 514. Here, the LRU priority table 517 indicates that the LRU priority according to the current LRU priority when the access is during execution of a speculative instruction (however, when there is no priority, the lowest priority = 0) Is set, and when the access is not during execution of a speculative instruction, a high LRU priority is set regardless of the current LRU priority.

The values recorded in the LRU priority table 517 can be arbitrarily set by the derivation method setting unit 518. Alternatively, it may be a predetermined value. As a method of implementing the derivation method setting unit 518, for example, a method of setting a value at the time of initial setting or program startup from the processor 530, or a method of incorporating the LRU priority table 517 using a ROM or the like at the time of mounting the cache memory device 500 And so on.

Finally, the cache control management unit 512
The data is recorded (or re-recorded) in the cache memory 520 as data having the LRU priority obtained by the above procedure.

(6) Sixth Embodiment FIG. 13 is a block diagram of a sixth embodiment of the present invention. In the present example, the cache controller 610 of the cache memory device 600 has an instruction identification unit 614 that identifies the instruction type of the processor that is the cause of the access.
And an LRU priority determining unit 616 for determining the next LRU priority of the data. The derivation method setting unit 618 determines the
This is a means for setting a value in the U priority table 617. As described later, the LRU is set by setting a value for this.
The method of deriving the priority can be changed.

The cache control management unit 612 is a part that performs main control in the cache controller 610, and controls recording (or re-recording) of data in the cache memory 620. The internal structure of the cache control management unit 612 is basically the same as the conventional one. A processor interface (processor IF) 611 is an interface for exchanging data and control signals between the processor 630 and the cache control management unit 612, and a bus interface (bus IF) 613 is provided via a system bus 640 for main storage ( (Not shown) for exchanging data and control signals.

When recording (or re-recording) data in the cache memory 620, first, the instruction identification unit 61
4 identifies the instruction type of the processor that caused the data access. Specifically, there is a signal line for notifying the instruction type of the processor from the processor 630 to the cache memory device 600, and the instruction identification unit 614 identifies and determines the type of the instruction of the processor 630 according to the signal of the signal line. I do.

Next, the LRU priority determining section 616 determines the next LRU priority of the data. Specifically, the LRU priority determination unit 616 refers to the LRU priority table 617 as shown in FIG. 14 and, based on the value recorded in the LRU priority table 617, determines the current LRU priority and the instruction identification unit 6.
The next LRU priority is determined from the identification result of No. 14.

Here, the LRU priority table 617
Sets the LRU priority according to the current LRU priority if the instruction is prefetch (however, if there is no priority, the lowest priority = 0), and if the instruction is a block transfer, A relatively low LRU priority is set, and for other instructions, a high LRU priority is set regardless of the current LRU priority.

The values recorded in the LRU priority table 617 can be arbitrarily set by the derivation method setting unit 618. Alternatively, it may be a predetermined value. As a method of realizing the derivation method setting unit 618, for example, a method of setting a value at the time of initial setting or program startup from the processor 630, or a method of incorporating the LRU priority table 617 using a ROM or the like at the time of mounting the cache memory device 600 And so on.

Finally, the cache control management unit 612
The data is recorded (or re-recorded) in the cache memory 620 as data having the LRU priority determined by the above procedure.

As a well-known technique, there is a method of extending an instruction set of a processor, assigning a level to a memory operation instruction, and changing an LRU priority setting method according to the level. In the present invention, the instruction set is extended. Without changing the LRU priority setting method according to the existing instruction type, this is different from the above-mentioned known technology.

(7) Seventh Embodiment FIG. 15 is a block diagram of a seventh embodiment of the present invention. The system configuration of this example is a bus-coupled parallel computer in which a plurality of processors are coupled by a system bus 740, the bus is a snooping bus, and the cache coherence protocol is invalid. The cache memory device 700 includes a processor and a system bus 74.
0 (or it may be built in the processor),
It includes an other processor bus request interception unit 714 that intercepts a bus request from the other processor node 750, and an LRU priority determination unit 716 that determines the next LRU priority. The derivation method setting unit 718 is a unit that sets a value in the LRU priority table 717. As described later, the derivation method of the LRU priority can be changed by setting a value for this.

The cache control management unit 712 is a part that performs main control in the cache controller 710, and controls recording (or re-recording) of data in the cache memory 720. The internal structure of the cache control management unit 712 is basically the same as the conventional one. A processor interface (processor IF) 711 is an interface for exchanging data and control signals between the processor 730 and the cache control management unit 712, and a bus interface (bus IF) 713 is provided via a system bus 740 for main storage ( It is an interface for exchanging data and control signals with another processor node 750 (not shown).

The process of recording (or re-recording) data in the cache memory 720 in response to a request from the own processor 730 is the same as the usual cache control performed conventionally, and is a normal operation. Therefore, the description is omitted.

The request issued by the other processor node 750 to the system bus 740 is sent to the other processor bus request
4 reads. The other processor bus request interception unit 714
When the other processor node 750 intercepts the request sent to the system bus 740, the result is sent to the LRU priority determination unit 716.

The LRU priority determining section 716 has an LRU priority table 717 as shown in FIG. 16, and based on the value recorded in the LRU priority table 717, the current LRU priority is determined.
The next LRU priority of the data is determined from the priority and the information from the other processor bus request interception unit 714.

Here, the LRU priority table 717
Is set as follows. For simplicity, the type of data request is data read (READ).
And The same applies to the case of writing data (WRITE). Own processor 730 and other processor node 7
If there is no data request from either of the 50, of course, do nothing. When there is a data read request from another processor node 750 and the data is held in the cache memory 720 for the own processor 730, the current LR
The U priority remains at the original value. Other processor node 7
If there is a data read request from 50 and the cache memory 720 for the own processor 730 does not hold the data, the data is fetched into the cache memory 720 and the current LRU priority of the data is set to 0. In this example, both when the retained data is clean (that is, when the data and the value in the main memory match) and when the data that is retained is dirty (that is, when the data and the value in the main memory may not match), Although the same value is set for the LRU priority, the LRU priority can be distinguished by the value set in the LRU priority table 717. If the data request is not from the other processor node 750 but from the own processor 730, the next LRU priority is set to the highest value (=
Set to 3).

If the data is read from another processor node 750, the data is stored in the cache memory 72.
If the data is to be recorded in 0 (not a re-recording), the other processor bus request interception unit 714 reads the data transferred on the system bus 740, and
12, the data is recorded in the cache memory 720 as data having the LRU priority determined by the LRU priority determining unit 716 according to the above procedure.

For example, data read (READ) is sent from the other processor node 750 to data without the LRU priority (that is, the data has no LRU priority in its own cache memory 720), and the result of snooping is In the case of “other clean” (other processor has data in clean) or “other dirty” (other processor has data in dirty), data is given the LRU priority as shown in FIG. Is recorded in the cache memory 720 as data of the lowest “0”. Note that the data recorded in the cache memory 720 at this time is obtained by reading the data transferred on the system bus 740 by the other processor bus request interception unit 714.

The values recorded in the LRU priority table 717 can be arbitrarily set by the derivation method setting unit 718. Alternatively, it may be a predetermined value. As a method of realizing the derivation method setting unit 718, for example, a method of setting a value at the time of initial setting or program startup from the processor 730, or a method of incorporating the LRU priority table 717 using a ROM or the like at the time of mounting the cache memory device 700 And so on.

[0090]

As described above, according to the present invention,
The value of the LRU priority used when determining data to be evicted from the cache memory can be positively operated. For example, when data that is unlikely to be used is recorded (or re-recorded) in the cache memory, by setting the LRU priority of the data low,
It is possible to prevent other necessary data from being evicted from the cache memory. Since this control is realized by controlling the change of the LRU priority when accessing data, the recording capacity of information for LRU control in the cache memory can be realized as before.
Therefore, the capacity of the cache memory can be used more effectively, and as a result, the performance of the system can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of a block configuration according to the present invention.

FIG. 2 is a diagram for explaining the operation principle of the present invention.

FIG. 3 is a block diagram of the first embodiment of the present invention.

FIG. 4 is a diagram illustrating an example of an LRU priority table according to the first embodiment.

FIG. 5 is a block diagram of a second embodiment of the present invention.

FIG. 6 is a diagram illustrating an example of an LRU priority table according to the second embodiment.

FIG. 7 is a block diagram of a third embodiment of the present invention.

FIG. 8 is a diagram illustrating an example of an LRU priority table according to the third embodiment.

FIG. 9 is a block diagram of a fourth embodiment of the present invention.

FIG. 10 is a diagram illustrating an example of an LRU priority table according to a fourth embodiment.

FIG. 11 is a block diagram of a fifth embodiment of the present invention.

FIG. 12 is a diagram illustrating an example of an LRU priority table according to the fifth embodiment.

FIG. 13 is a block diagram of a sixth embodiment of the present invention.

FIG. 14 is a diagram illustrating an example of an LRU priority table according to a sixth embodiment.

FIG. 15 is a block diagram of a seventh embodiment of the present invention.

FIG. 16 is a diagram illustrating an example of an LRU priority table according to a seventh embodiment.

FIG. 17 is a diagram illustrating an example of a case where data is newly recorded in a cache memory.

FIG. 18 is a diagram illustrating an example in which the effectiveness of a cache memory is impaired by prefetching.

FIG. 19 is a diagram showing an example in which a cache memory is effectively used without prefetch.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Cache memory device 10 Cache controller 11 Cache control means 12 Derivation method setting means 13 LRU priority determination means 20 Cache memory 30 Processor 40 System bus

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Mitsuru Sato 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa F-term in Fujitsu Limited (Reference) 5B005 JJ11 KK12 MM01 NN22 QQ02 QQ04

Claims (8)

[Claims] In a cache memory device controlled by the LRU method, when new data is recorded in a cache memory or when data is re-recorded after a cache hit, the current LRU priority of the data is determined. An LRU priority determining unit for deriving the next LRU priority using the attribute of the data, the means for accessing the data, the state of the processor, or all or a part of the information; LRU determined by the department
A cache memory device characterized by recording or re-recording data in a cache memory as data having priority. 2. The derivation method setting unit according to claim 1, wherein the method used by the LRU priority determination unit to derive the next LRU priority is arbitrarily changed or set. A cache memory device comprising: 3. The cache memory device according to claim 1, further comprising: an address analysis unit that determines a priority of the data from an address of the data.
The LRU priority determining unit, when recording or re-recording data in the cache memory, uses at least the priority of the data output by the address analysis unit and the current LRU priority of the data, LRU
A cache memory device for determining a priority. 4. The cache memory device according to claim 1, wherein when the processor has a function of a prefetch instruction, whether the processor accesses the cache memory by a prefetch instruction. The LRU priority determining unit, when recording or re-recording data in the cache memory, includes at least the identification result of the prefetch identifying unit and the current LRU of the data.
A cache memory device for determining a next LRU priority of data by using the priority. 5. The cache memory device according to claim 1, wherein an address of data which is highly likely to be used by the processor is predicted based on a past access history from the processor to the cache memory,
A prefetch control unit that prefetches the data at the address; the LRU priority determination unit determines whether or not the data is loaded by the prefetch control unit when recording or re-recording the data in the cache memory; A cache memory device for determining a next LRU priority of data using a current LRU priority of data. 6. The cache memory device according to claim 1, further comprising: an instruction identification unit that identifies a type of an instruction that has issued an access from the processor to the cache memory, wherein the LRU priority determination unit includes: When recording or re-recording data in the cache memory, at least the identification result of the instruction identification unit and the current LR of the data
A cache memory device for determining a next LRU priority of data using a U priority. 7. The cache memory device according to claim 1, wherein when the processor has a speculative instruction execution function, the processor accesses the cache memory while the processor executes the speculative instruction. A speculative execution identifying unit for identifying whether the access is issued or not, wherein the LRU priority determining unit determines at least the identification result of the speculative execution identifying unit when recording or re-recording data in the cache memory. , The current LRU of the data
A cache memory device for determining a next LRU priority of data by using the priority. 8. The cache memory device according to claim 1, further comprising, when the processor is a bus-connected parallel computer, another processor bus request interception unit that intercepts a bus request of another processor. The LR
When another processor issues a request to the bus, the U priority determining unit determines at least the type of the request issued by the other processor, the result of the snooping, and the current LR of the data.
A cache memory device for determining a next LRU priority of data using a U priority.