JPH08335188A - Cache memory device capable of controlling software - Google Patents

Abstract

PURPOSE: To avoid a problem on the contamination of a cache memory caused by data having the low frequency of use and to decrease a cache error by positively using information releating to memory access provided for a programmer and a compiler. CONSTITUTION: As the means of access to the cache memory, an instruction designating a real address and a set address is received. When the cache is accessed by designating the real address and the set address, those addresses are respectively stored in a real address storage means 201 and a set address storage means 202. Concerning the respective ways of the cache memory, comparing means 215 to 217 inspect cache hit or error to a cache block uniquely decided by the real address and the block of the set address designated by the instruction. Depending on the result, a cache control circuit 222 controls the cache operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a software controllable cache memory device capable of reducing cache misses and improving processor execution efficiency.

[0002]

2. Description of the Related Art Main memory references of computer programs have locality. Utilizing this property, data in the main memory that is often referred to is copied to a high-speed, small-capacity memory called a cache memory, and the main memory is accessed to this cache memory, thereby making memory access. Speeding up is done.

The cache memory operates as follows. For memory access from the processor, it is first checked whether the data exists in the cache memory. If the data exists in the cache memory, the data in the cache memory is transferred to the processor. If it does not exist, the execution of the instruction that requires the data is suspended, and the data is transferred from the main memory to the cache memory.
When the transfer is completed, the data requested by the processor is transferred to the processor, and the execution of the interrupted instruction is restarted.

Thus, if the data exists in the cache memory, the processor can obtain the data at the access speed of the cache memory. However, if there is no data in the cache memory, the processor is kept waiting for execution while the data is transferred from the main memory to the cache memory.

A cache miss is caused by initial reference of data, lack of cache memory capacity, and cache block contention. The miss due to the initial reference of the data occurs at the first access to the data in the cache block. That is, there is no copy of the main memory in the cache at the time of first data reference, and it is necessary to transfer the data from the main memory.

A miss due to lack of capacity of the cache memory (capacitive miss) means that some blocks are evicted from the cache when the capacity of the cache is not sufficient to accommodate the blocks required for program execution. It is a mistake caused by.

The miss due to cache block conflict (competitive miss) is a miss that occurs in a direct map or set associative cache. In these methods, since the main memory address and the set in the cache correspond to each other, contention occurs when accessing the same set, and even frequently used data is forcibly removed from the block. Sometimes.

In order to reduce the above cache miss from the architecture side, the following may be done. First, by making the cache capacity large enough to contain all the data required to execute the program, capacity mistakes can be avoided. Next, by making the mapping method between the main memory and the cache block fully associative, it is possible to avoid the miss of competition.

However, the realization of the above solution is a trade-off with cost. That is, if the capacity of the cache memory is increased, the memory device becomes expensive,
If the mapping method between the main memory and the cache memory is set to the full associative method, the hardware becomes complicated and the operation clock of the cache decreases.

Methods for reducing cache misses can be considered not only from the architecture side, but also from the compiler and programmer side. The programmer
Holds information about references to data used in the program. The compiler can also obtain information about the data reference from the program by the optimization process represented by the data flow analysis. It is possible to reduce cache misses by using these data access information as hints when accessing the cache memory.

Therefore, in recent years, various methods have been proposed in which the cache is controlled by software by utilizing the characteristics of the program or based on the analysis result of the compiler. The prior art shown below is an example of an attempt to operate the cache memory device by software.

[0012] First, there is a method in which the cache block size, the number of sets, and the block transfer size can be changed at the time of execution according to the characteristics of the program. Normally, these parameters are decided at system startup. By changing this according to each program,
Memory access can be performed more flexibly.

Next, there is a method called prefetch. Prefetch is a method in which data expected to be used in the future is transferred to the cache prior to execution. By performing prefetch, cache misses due to initial reference can be reduced. As a method to realize prefetch,
There are proposed a method of clearly providing a prefetch instruction, a method of transferring data to a cache by a load instruction to a specific register, a method of transferring an adjacent block together when a block is transferred due to a cache miss, and the like.

Further, in Japanese Patent Laid-Open No. 4-2741, the above prefetch method is improved. According to this, a mode for prefetching data (prefetch mode) is provided, and in the prefetch mode for a load instruction, adjacent blocks are also prefetched into the cache at the same time. Further, a means for recording the offset of the load instruction is provided, and instead of simply prefetching an adjacent block, a block including an address obtained by adding this offset to the currently accessed address is prefetched. This is trying to solve the problem of prefetching unnecessary blocks into the cache, which has been a problem in the past. In addition, by allowing only certain blocks in the set of caches to store prefetched data, and by providing a bit in the cache block to identify if it is prefetched data, the prefetched block is cached by a normal load instruction. It prevents you from being kicked out.

Japanese Unexamined Patent Publication No. 6-202951 proposes a technique for more aggressively operating a cache memory by providing a memory access instruction for each level of the hierarchical cache memory. This technique is intended to prevent the cache memory from being contaminated by infrequently used data. Specifically, the above object is achieved by providing an instruction to access each hierarchy of the memory, that is, the main memory and the cache of each level. For example, when the cache memory device is a two-level cache, the memory access instructions include the first load instruction and the first load instruction for the first level cache memory.
A store instruction, a second load instruction and a second store instruction for the second level cache memory, and a main memory access load instruction and a main memory access store instruction for the main memory. To

In a normal cache memory having a two-layer structure, when a memory access occurs, the first level cache is checked first, and if hit, the data is returned from the first level cache to the processor. In the case of a miss, the second level cache is checked, and if the second level cache is hit, the second level cache block is first transferred to the first level cache memory. Here, the replacement of the cache blocks of the first level and the second level occurs. The data is then returned to the processor from the first level cache. When a miss is made in the second level cache, the block is first transferred from the main memory to the second level cache. The block is then transferred from the second level to the first level cache and finally the data is transferred from the first level cache to the processor.

When the cache memory is operated as described above, even data that the compiler and programmer recognize as infrequently used is transferred to the processor after being transferred to the first level cache. Here, it becomes a problem that the data on the first level cache, which is frequently used, is expelled by accessing the data which is rarely used.

In order to avoid this problem, in the technique disclosed in the above-mentioned Japanese Patent Laid-Open No. 6-202951, the first load instruction, the first store instruction, the second load instruction, the second store instruction, and the main memory access load. It has an instruction and a main memory access store instruction, and operates as follows.

First, when the first load instruction or the first store instruction is received in the cache memory, the cache memory operates in the same manner as the general memory access described above. That is, if the cache misses, the block is transferred from the lower level memory to the first level cache, and then the data is returned from the first level cache to the processor, or the data from the processor is transferred to the first cache. Will be stored in.

When the second load instruction or the second store instruction is accepted into the cache memory, the first level cache is first examined like a general cache. If the cache hits here, the data is loaded from the first level cache or the data is stored in the first level cache. If you miss in the first level cache, the second level cache is examined. If the cache hits here, the data is loaded from the second level cache, or the second
Data from the processor is stored in the level cache. When a miss is made in the second level cache, the main memory is accessed and the corresponding memory block is transferred from the main memory to the second level cache. The data is then loaded into the processor from the second level cache or the data from the processor is stored in the second level cache. In this way, when the second load instruction or the second store instruction is executed and the first level cache misses, the block transfer from the lower memory hierarchy is performed only up to the second level, and the data with the processor is transferred. The interaction is directly with the second level cache.

Similarly to the second load instruction and the second store instruction, the main memory access load instruction and the main memory access store instruction also cause the first and the second from the main memory when a miss occurs in the first and second level caches. No blocks are transferred to the two-level cache, and data is exchanged with the processor directly to / from the main memory.

From the above, the compiler and the programmer use the first load instruction and the first store instruction to access the data determined to be most frequently used, and the second load instruction to access the less frequently used data. And the second store instruction and the main memory access load instruction and the main memory access store instruction to avoid cache pollution by infrequently used data, that is, eviction of frequently used data from the upper level cache. You can

[0023]

As described above, by prefetching data into the cache prior to actual data use by using the software control of the conventional cache memory device, in particular, the method related to prefetching, an initial reference miss can be prevented. Can be reduced.

However, as long as the direct map method or the set associative method is adopted as the mapping method between the main memory and the cache memory, the miss due to the contention of the cache block that the necessary block is evicted cannot be eliminated. That is, when a large array is sequentially accessed, there is a problem in that even more frequently used data will be evicted from the cache.

Further, the technique introduced in the prior art (Japanese Patent Laid-Open No. Hei 6)
No. 202951), the contamination of the cache of a higher level can be avoided by the memory access instruction for each level, but the contamination of the cache memory of the same level cannot be avoided.

Further, in the conventional cache memory device,
Since the memory access instruction that specifies only the real address of the main memory where the data is stored is the only means to access the cache memory, the information held by the programmer and the compiler should be aggressively reduced to reduce cache misses. Cannot be utilized.

An object of the present invention is to avoid the problem of polluting the cache memory with infrequently used data,
Another object of the present invention is to provide a cache memory device capable of reducing cache misses and improving processor execution efficiency by positively using information relating to memory access held by a programmer and a compiler.

[0028]

In order to solve the above-mentioned problems, a cache memory device according to claim 1 of the present invention comprises:
A cache memory device that is located between a processor and a main memory device, and caches data stored in the main memory device to a cache memory to perform a high-speed memory access in response to a main memory access instruction from the processor. It is characterized in that it comprises first access means by a real address and second access means by a set address of the cache memory designated by an instruction.

A cache memory device according to a second aspect of the present invention is located between the processor and the main storage device, and caches the data stored in the main storage device to the cache memory, thereby allowing the main memory from the processor to operate. A cache memory device that performs a high-speed memory access by receiving a memory access instruction, receives a memory access instruction that specifies only a real address, performs a memory access operation according to the instruction, and executes a memory access instruction that is specified by the instruction. A first access unit that performs caching using a cache block determined based on an address, and a memory access instruction with a set address designating a real address and a set address that identifies the cache block are received, and in response to the instruction Specified memory access operation Characterized in that a second access means for caching with cache block is determined based on the set address.

The cache memory device of the present invention, in addition to the normal load, store, and prefetch instructions that specify only the real address to access the cache memory, sets that access the cache memory by specifying the real address and the set address. Accepts a memory access instruction with address specification. Memory access instructions with set address designation include load, store, and prefetch instructions with set address designation, and cache block invalidate instructions with set address designation.

When the set associative method is adopted as the mapping method of the main memory device and the cache memory, the second access means by the set address designation accesses one or more specific ways in the set associative method. Can be

In the cache memory device according to the present invention,
When a prefetch instruction with set address specification is received, it operates as follows. First, it is checked whether the data indicated by the real address specified by the instruction exists in the cache block determined based on the real address,
(A) If present, invalidate the cache block,
The block on the main storage device containing the data indicated by the real address designated by the instruction is transferred to the cache block of the set address designated by the instruction, and (b) if it does not exist, the set designated by the instruction It is checked whether or not the data indicated by the real address specified by the instruction exists in the cache block of the address. (B1) If it does not exist, the data specified by the instruction is specified in the cache block of the set address specified by the instruction. Transfer the block on the main memory containing the data indicated by the real address.

In the cache memory device according to the present invention,
When a load instruction with set address specification is received, it operates as follows. First, it is checked whether or not the data indicated by the real address designated by the instruction exists in the cache block determined based on the real address. (A) If it exists, the cache block is invalidated and designated by the instruction. A block on the main memory containing the data indicated by the real address specified by the instruction is transferred to the cache block of the set address, and the data in the transferred block is returned to the processor, (b) If it does not exist, it is checked whether or not the data indicated by the real address specified by the instruction exists in the cache block of the set address specified by the instruction. (B1) If it exists, the data is returned to the processor. , (B2) If it does not exist, the real address specified by the instruction is added to the cache block at the set address specified by the instruction. Transfer the blocks on the main memory device including a data indicated by the scan returns the data of the transferred block to the processor.

In the cache memory device according to the present invention,
When a store instruction with set address specification is received, it operates as follows. First, it is checked whether or not the data indicated by the real address designated by the instruction exists in the cache block determined based on the real address. (A) If it exists, the cache block is invalidated and designated by the instruction. Transfer a block on the main storage device containing data indicated by the real address specified by the instruction to the cache block of the set address, and store the data given from the processor in the transferred block,
(B) If it does not exist, it is checked whether or not the data indicated by the real address specified by the instruction exists in the cache block of the set address specified by the instruction.
1) If it exists, the data given from the processor is stored in the block. (B2) If it does not exist, it is stored in the cache block of the set address specified by the instruction.
A block on the main storage device containing the data indicated by the real address specified by the instruction is transferred, and the data given from the processor is stored in the transferred block.

Means may be provided for transferring data between cache blocks without going through the main memory. In this case, in the set-address-specified prefetch, load, and store instructions, if the data indicated by the real address specified by the instruction exists in the cache block determined based on the real address, before invalidation Causes data to be transferred between cache blocks.

[0036]

The prefetch instruction with the set address designation makes it possible to store the data in the main memory in the cache block of the set address designated by the software. Generating the code so that this prefetch instruction is executed prior to the actual use of the data reduces initial reference misses when using the actual data. Further, since any block of the main memory can be stored in any block of the cache memory device, it is possible to reduce misses due to block competition as in the case of the fully associative cache memory.

The effect of reducing competition is remarkable when sequentially accessing a large sequence. In the conventional cache memory device, the data on the main memory is uniquely mapped to the cache memory by its real address. In this case, if large array data is accessed sequentially, the data originally existing in the cache block will be forcibly expelled.
On the other hand, in the cache access with set address designation according to the present invention, since the cache block explicitly designated by the instruction can be repeatedly used, the eviction of other blocks can be minimized.

The load instruction with set address specification enables the data stored in a specific block of the cache memory to be loaded into the register by the block-specifiable prefetch instruction. Prefetch instruction with set address specification and load instruction with set address specification allow you to map any main memory block to any cache block and specify the block in the same way as in the full associative method, despite the cache memory of the set associative method. By doing so, the hardware cost can be suppressed to the level of set associative.

By providing the data transfer means between the blocks, it becomes possible to suppress the overhead caused by invalidating the cache block.

[0040]

An embodiment of the present invention will be described below with reference to the drawings. The cache memory device of this embodiment is a software-controllable cache memory device that can perform memory access by designating a real address and a set address of the cache memory.

FIG. 1 is a block diagram of a computer system to which a cache memory device according to the present invention is applied. The cache memory device 103 of the present embodiment is placed between the processor (CPU) 101 and the main storage device 102. The cache memory device 103 includes a memory unit 105 configured by a high-speed and small-capacity memory, and a memory control unit 104 that controls access to the cache memory.

FIG. 2 is a block diagram showing the configuration of the cache memory device 103. Note that FIG. 2 described here
The cache memory device 103 is a 2-way set associative type cache to which the present invention is applied.

The cache memory device 103 of this embodiment
Can accept a conventional memory access instruction conventionally used (that is, a load instruction, a store instruction, a prefetch instruction, etc., which specify only a real address of data). When such a memory access that specifies only the real address of the data occurs, the memory control unit 104 in the cache memory device 103 determines whether the data corresponding to the address exists in the cache (specifically, the memory unit). 105). If the data is in the cache, the data is transferred from the memory unit 105 to the processor 101 (in the case of a load instruction), or the data from the processor 101 is transferred to the memory unit 105 (in the case of a store instruction). If the data is not in the cache, the main memory 102 is requested for the data.

Further, in the cache memory device 103 of the present embodiment, a memory access instruction with a set address designation peculiar to the present embodiment (a load instruction and a store which specify not only the real address of data but also the set address of the cache memory) Instructions, prefetch instructions, etc.) can be accepted. The instruction with set address designation is a memory access instruction that explicitly instructs caching using the cache block designated by the set address.

For example, when a load instruction with set address designation is received, the memory control unit 104 in the cache memory device 103 first checks whether or not the data corresponding to the designated real address exists in the cache, and If it is in the cache, the block is invalidated, the data of the designated real address is transferred from the main memory 102 to the block of the designated set address, and then the block of the designated set address is concerned. Load the data. If the data corresponding to the specified real address is not in the cache, it is checked whether the block of the specified set address has the data, and if the data is in that block, the data is loaded from that block. If the block of the designated set address does not have the data, the data of the designated real address is transferred from the main memory 102 to the block of the designated set address, and then the data of the block of the designated set address is transferred. To load. In short, in the load instruction with set address specification, caching is performed using the block of the set address specified explicitly. The same applies to other instructions with set address designation.
The instruction with set address designation will be described later in detail.

The configuration of the cache memory device 103 of this embodiment will be described with reference to FIG. The real address storage unit 201 stores the real address on the main memory 102, which is passed by the memory access request from the CPU 101.
The real address is logically divided into a block address part, a set address part, and an in-block address part for accessing the memory. The block address part indicates a block address that specifies a block on the main memory 102, the set address part indicates a set address that specifies a cache block to be cached, and the in-block address part indicates a relative address within the block.

The set address storage means 202 is used when an instruction with set address designation is received. The set address storage means 202 stores the set address designated by the instruction with set address designation.

Cache memory device 1 in this embodiment
No. 03 memory unit 105 includes a way 203 and a way 2
It is composed of two ways 04. Each way
It comprises block address storage means 205, 207 and block data storage means 206, 208. The block address storage units 205 and 207 are each block of the cache (specifically, the block data storage unit 206,
Each block of 208) is a table showing which block in the main memory holds a copy. The block data storage means 206, 208 hold a copy of the data in the block of the main memory corresponding to the block address storage means 205, 207.

That is, the block address storage means 20
Reference numeral 5 has a plurality of entries for storing block addresses, and each entry has a one-to-one correspondence with each block of the block data storage means 206. That is, when a block address in an entry of the block address storage unit 205 is held, the block of the block data storage unit 206 corresponding to the entry is cached with the data of the block address in the main storage. . Block address storage means 20
7 and the block data storage means 208 are similar. A plurality of words are usually stored in each block of the block data storage means 206, 208.

The comparators 215, 216, 217 compare the block address of the main memory indicated by the block address part of the real address with the block address in the block address storage means specified by the set address part. If the block addresses match as a result of the comparison, it means that the data (for one block) of the real address (block address) indicated by the block address storage means exists in the cache (specifically, on the block data storage means). Become.

The cache control circuit 222 includes a comparator 21.
Outputs from 5,216,217 (results of cache hit inspection in each way) and control signals from the CPU are input to control the cache memory device 103 as a whole.

Next, the operation of the apparatus of FIG. 2 for a normal memory access instruction designating only a real address will be described.

In memory access by a normal load instruction designating only a real address, the CPU 101 first notifies the cache control circuit 222 of the issuance of the load instruction, and at the same time, the real address of the data to be loaded is also passed. The cache control circuit 222 sets the given real address in the real address storage means 201 (23
0). The set address in the set real address is an offset from the beginning of the block address storage unit 205.

If the block of the main memory 102 containing the data of the real address set in the real address storage means 201 is cached, the block address storage designated by the set address part of this real address storage means 201 is stored. The same block address as the block address part of the real address storage means 201 should be set in the entry 209 of the means 205, and in this case, the block data storage means 2 corresponding to the entry 209.
This means that the block 210 of the main memory 102 containing the data of the real address is copied to the block 210 of 06.

Therefore, based on the set address part of the real address storage means 201, the entry 209 of the block address storage means 205 of the way 1 (203) is accessed to store the block address and real address stored in the entry 209. The block address part of the means 201 is input to the comparator 215 for comparison. The comparison result of the comparator 215 is output as the output 223 to the cache control circuit 22.
Enter 2. If the above block addresses match as a result of comparison by the comparator 215, it means that the desired data is cached in the block 210 of the block data storage unit 206 corresponding to the entry 209. , The requested data is read from the position designated by the in-block address portion (225) of the real address storage means 201 in the block 210 and returned to the CPU 101. As a result of comparison by the comparator 215,
If they do not match, it means that the block including the desired data has not been cached in the block 210. Therefore, the cache control circuit 222 reads the data of the real address from the main memory 102 and caches it in the block 210. And returns to the CPU 101.

Although the operation of way 1 (203) has been described above, the same applies to way 2 (204). In particular, access to the block address storage means 205 and 207 and comparison of block addresses by the comparators 215 and 216 are performed in parallel in each way. Further, although the normal load instruction has been described above, the operation for a normal store instruction or a prefetch instruction that specifies only a real address is similar.

Next, the operation of the apparatus of FIG. 2 for a memory access instruction with set address designation for designating a real address and a set address will be described. First, the instruction with set address designation will be specifically described before the operation description. To do.

3 to 6 show formats of instructions with set address designation.

FIG. 3 shows a prefetch instruction with set address designation. This prefetch instruction is an instruction to transfer the block of the main memory including the designated real address to the designated block of the cache. In the prefetch address field, the real address of the prefetch target data is specified. In the set address field, a set address that specifies the cache block to which the prefetch data is transferred is explicitly specified.

FIG. 4 shows a load instruction with set address designation. In the load address field, the real address on the main memory of the data to be loaded is specified. In the target register field, specify the register to load the data. In the set address field, a set address that specifies a block used to cache the data to be loaded is explicitly specified. This load instruction loads the data of the designated real address into the designated register and forcibly caches the block containing the data into the cache block of the designated set address. If the data is cached in another block, that block is invalidated and cached in the block of the specified set address.

FIG. 5 shows a store instruction with set address designation. In the store address field, the real address of the main memory that stores the data is specified. In the source register field, the register in which the data to be stored is stored is specified. In the set address field, a set address that specifies a block used to cache the data to be stored is explicitly specified. This store instruction stores the data in the designated register at the designated real address in the main memory, and forcibly caches the block containing the data in the cache block at the designated set address. If the data is cached in another block, that block is invalidated and cached in the block of the specified set address.

FIG. 6 shows a cache block invalidating instruction with set address designation. A cache block to be invalidated is specified in the set address field. This cache block invalidation instruction invalidates the cache block of the designated set address.

Next, the cache memory device 1 of FIG. 2 for the above-mentioned instruction with set address designation of FIGS.
The operation of 03 will be described. Upon receiving these instructions, the cache control circuit 222 sets the real address specified by the instructions in the real address storage means 201 (2
At the same time, the set address designated by the instruction is set in the set address storage means 202 (231).
In the cache block invalidation instruction of FIG. 6, only the set address is set.

The cache access by the real address of the real address storage means 201 is the same as the above-mentioned normal memory access instruction designating only the real address. That is, first, the block address storage means 20 of each of the ways 1 and 2 is set by the set address portion in the real address.
5, 207 are accessed in parallel, and then the block addresses 209, 211 stored in the block address storage means 205, 207 and the block address part of the real address storage means 201 are compared by the comparators 215, 216. As a result, the output 223 of the comparator 215 determines whether the data of the real address is cached in the block 210 determined from the real address of the way 1, and the output 226 of the comparator 216 determines that the data of the way 2 is concerned. It can be seen whether or not the data of the real address is cached in the block 213 determined from the real address.

The same is true for comparison using the set address of the set address storage means 202. That is, the entry 21 of the block address storage unit 207 is based on the set address set in the set address storage unit 202.
2 is accessed, and the block address held in the entry 212 is compared with the block address part in the real address storage means 201 by the comparator 217.
If the compared block addresses are equal, it means that the data accessed at the real address is cached in the block 214 at the set address explicitly specified by the instruction. Comparison result output 22 of the comparator 217
7 is input to the cache control circuit 222 similarly to the results of the comparators 215 and 216.

The above set address storage means 20
2 accesses the block address storage means 207 and executes comparison in the comparator 207, the block address storage means 205 by the real address storage means 201,
This is performed in parallel with the access of 207 and the execution of comparison in the comparators 215 and 216.

In the instruction with set address designation (prefetch, load, store) in FIGS. 3 to 5 described above, both the real address and the set address are designated, so that the comparators 215, 216 and 217 perform the above-mentioned operation. The comparison results 223, 226, 227 are input to the cache control circuit 222. That is, the cache control circuit 2
22 indicates whether the data of the real address specified by the instruction is cached in the cache block in the way 1 specified by the set address part of the real address specified by the instruction, and the real address specified by the instruction. Whether the cache block is cached in the way 2 designated by the set address part of the cache memory, and whether the cache block is cached in the way 2 designated by the set address explicitly designated by the instruction. I can know. Cache control circuit 2
Knowing such a caching situation, the 22 performs actual data prefetching, loading, and storing. The operation of the cache control circuit 222 is shown in FIG.
~ It mentions later with reference to FIG.

In the cache block invalidating instruction with set address designation in FIG. 6 described above, only the set address is designated, so the comparison result 227 of the comparator 217 is input to the cache control circuit 222 by the above-described operation. . That is, the cache control circuit 222 determines whether or not the data of the real address designated by the instruction is cached in the cache block in the way 2 designated by the set address explicitly designated by the instruction.
You can know.

The operation of the cache control circuit 222 when receiving the prefetch instruction with set address designation shown in FIG. 3 will be described. At this time, the cache control circuit 222
By the above-mentioned operation, the comparison results 223, 226, 227 of the comparators 215, 216, 217 are input, and the status of caching the data of the designated prefetch address is known. Then, it operates as shown in FIG.

In FIG. 7, the cache control circuit 222
First, it is checked whether the cache is hit by the access by the real address (prefetch address) (step 700). The cache hit by the real address is a case where the block addresses match in either of the comparators 215 and 216. If the cache is hit by the access by the real address, the currently hit entry 209 in the block address storage means 205, 207.
(And corresponding block 210) or entry 21
Invalidate 1 (and corresponding block 213) (step 703).

This invalidation is to set an invalid flag in the valid bit corresponding to the entry in the case of the store-through type cache, and to store the block 210 or 213 of the hit entry in the store-back type cache. This is a process of writing back to the memory 102. The valid bit is bit information provided corresponding to each entry of the block address storage means 205 and 207,
When the invalid flag is set in the valid bit, it indicates that the cache block corresponding to the valid bit is empty. When the invalid flag is not set in the valid bit, it indicates that the cache block corresponding to the valid bit is in use.

After the invalidation of step 703 is completed, the block of the main memory 102 indicated by the real address of the real address storage means 201 is transferred (prefetched) to the cache block 214 designated by the set address storage means 202 (step). 705). Also, block 214
Is set to the entry 212 of the block address storage means 207 corresponding to the block address of the block that has been prefetched (that is, the block address portion of the real address storage means 201) and the corresponding valid bit is set to the invalid flag OFF (step 705).

The cache is missed due to the cache access by the real address in step 700 (comparators 215 and 21).
If the comparison of the block addresses in 6 does not coincide with each other), it is checked whether or not a cache hit is caused by the access by the set address designated by the set address storage means 202 (step 706). This judgment is made by the comparator 2.
This is done by checking whether the block addresses match in the comparison by 17. If the block addresses match in the comparison by the comparator 217, it means that a cache hit has occurred in the access by specifying the set address. A cache hit means that the block 214 designated by the set address storage means 202 has already cached the block on the main memory including the real address of the real address storage means 201. The circuit 222 ends the operation for the prefetch instruction with set address designation.

If a cache miss occurs in step 706, the process proceeds to step 705, in which the real address storage means 20.
A block of the main memory 102 indicated by a real address of 1,
The data is transferred to the cache block 214 designated by the set address storage means 202. The entry 212 of the corresponding block address storage means 207 is set, and the valid bit is also set.

The operation of the cache control circuit 222 when receiving the load instruction with set address designation shown in FIG. 4 will be described. At this time, the cache control circuit 222 causes the comparison result 2 of the comparators 215, 216 and 217 by the above-described operation.
23, 226, 227 is input to know the caching status of the data at the specified load address. After that, it operates as shown in FIG.

In FIG. 8, the cache control circuit 222
First, it is checked whether the cache is hit by the access by the real address (load address) (step 801). This is the same determination as in step 700 of FIG. When the cache is hit by the access by the real address, the block address storage means 205,
Invalidate the currently hit entry 209 (and corresponding block 210) or entry 211 (and corresponding block 213) in 207 (step 80).
4). The invalidation is the same process as step 703 in FIG. 7.

After the invalidation of step 804 is completed, the block of the main memory 102 indicated by the real address of the real address storage means 201 is transferred to the cache block 214 designated by the set address storage means 202 (step 808). Further, the block address of the block just transferred (that is, the block address part of the real address storage unit 201) is set in the entry 212 of the block address storage unit 207 corresponding to the block 214, and the corresponding valid bit turns off the invalid flag. Set (step 808). The process of step 808 is the same as that of step 705 of FIG.

After step 808, the data at the position of the in-block address portion of the real address storage means 201 is fetched from the block 214, transferred to the CPU 101, and set in the designated target register (step 8).
10).

In the cache access by the real address in step 801, the cache miss (comparators 215 and 21
If the block address comparisons in 6 are both unmatched, it is checked whether or not a cache hit is caused by the access by the set address designated by the set address storage means 202 (step 805). This determination is similar to step 706 in FIG. If there is a cache hit in the access by specifying the set address, the relevant block 2
Since the request data is already cached in 14, the process proceeds to step 810 to load the request data into the target register. If a cache miss occurs in step 805, the process proceeds to step 808, the block including the requested data is cached in the block of the designated set address, and the process proceeds to step 810.
Load the requested data into the target register.

The operation of the cache control circuit 222 when receiving the store instruction with set address designation shown in FIG. 5 will be described. At this time, the cache control circuit 222 causes the comparison result 2 of the comparators 215, 216 and 217 by the above-described operation.
23, 226, 227 are input to know the caching status of the data of the specified store address. Then, it operates as shown in FIG.

In FIG. 9, steps 801 to 808 assigned the same numbers as in FIG. 8 are the same processing, and therefore the description thereof will be omitted. However, while the load address designated by the load instruction with set address designation is used as the real address in FIG. 8, the store address designated by the store instruction with the set address designation is used as the real address in place of it in FIG. Further, step 812 of FIG. 9 is a process of writing the contents of the source register designated by the instruction to the position of the in-block address part of the real address storage means 201 in the cache block 214 of the set address designated by the instruction. .

The operation of the cache control circuit 222 when receiving the cache block invalidating instruction with set address designation shown in FIG. 6 will be described. At this time, the cache control circuit 222 inputs the comparison result 227 of the comparator 217 by the above-described operation, and knows the caching status of the block 214 having the designated set address. If the invalidation flag is set in the valid bit corresponding to the entry 212 of the block address storage unit 207 of the designated set address, it means that the block 214 has already been invalidated, and the processing is directly performed. finish.
If the invalidation flag is not set in the valid bit of the entry 212, the invalidation flag is set there to invalidate. If this cache memory device is a store-through type cache memory, the latest data is stored in the main memory, so the invalidation is completed.
If it is a store-back type cache memory, at the same time as setting the invalidation flag, the block data storage means 2
The data stored in the corresponding entry 214 of 08 is written back to the main memory 102.

In the processing of FIGS. 7 to 9, the hit block 210 or 213 is written back to the main memory 102 (in the case of the storeback method), and then the block of the main memory 102 indicated by the real address is set. Although the data is transferred to the cache block 214 designated by the address storage means 202, a method of directly transferring the data from the block 210 or 213 to the block 214 by using the data transfer means 219 and 220 between the cache blocks is adopted. You can also

Next, the problem of alias between cache blocks will be described. Aliases between cache blocks are a concern for executing set-addressed instructions. In order to avoid this aliasing problem, in the present embodiment, it is necessary to place the following restrictions on the use of the instruction with set address designation.

Constraint (1): A normal store instruction for a real address a is not executed between a prefetch instruction with a set address for a certain real address a and a load or store instruction with a set address for using prefetch data. . On the contrary, when there is a possibility of storing at the real address a, the prefetch with set address designation, load and store instructions are not used.

Constraint (2): the same block in main memory
It must not be valid in multiple blocks on cache memory. That is, the same set address is designated for the access by the instruction with the set address designation to the data in the same block on the main memory.

Restriction (3): After the desired processing is performed using the instruction with the set address designation, the designated cache block must be invalidated by the invalidation instruction with the set address designation. In particular, if there is a function call or the like after the instruction with set address designation is executed and before it is invalidated, the block is invalidated before the function call.

The constraint (1) will be described with a specific example. Consider a case where a situation occurs in which processing is performed by the following processing (A) to (E).

(A) Execution of a normal load instruction for the real address X (B) After the block corresponding to the real address X is transferred to the cache by the process (A), the set address for the cache block I for the real address X Execution of specified prefetch instruction

(C) Execution of a normal store instruction to the real address X (D) Execution of an access instruction to a block of the main memory that is mapped to the same cache block as the real address X. Occurrence of eviction of block transferred to (E) Execution of load instruction with set address designation using data prefetched to set address I by processing (B)

First, by executing the process (A), the block of the main memory 102 containing the real address X is transferred onto the cache block. The transfer destination cache block is uniquely determined by the real address X (specifically, the set address portion in the real address X). Next, when the situation of the processing (B) occurs, if the main memory block transferred to the cache in the processing (A) is prefetched to the block of the set address I of the designated cache again, if two blocks in the cache are The same main memory block will be copied to the block.

In order to avoid this, in the cache memory device 103 of this embodiment, when executing the prefetch instruction with set address designation, as described above, it is first determined whether the cache is hit by the real address given by the instruction. It checks and invalidates the hit block if it hits, then prefetches the data to the set address specified by the instruction. As a result, in the execution of the process (B), the cache block transferred by the process (A) is invalidated by the cache access by the real address X, and then the prefetch instruction of the process (B) is designated. The main memory block is transferred to the cache block of the set address I. At this point, the main memory block corresponding to the real address X exists only in the block I in the cache.

Next, consider the case where the situation of the processing (C) occurs. Since the process (C) is a normal store instruction, the cache is accessed only by the real address, the main memory block for the real address X is transferred to the cache memory, and new data is stored. At this point, the latest data will not be on the cache block indicated by the set address I. When the processing (D) situation occurs next time, the latest data for the address X is no longer in the cache. Finally, when the situation of the processing (E), that is, the situation of executing the instruction to load the data prefetched to the set address I by the processing (B) with the set address designation, old data is returned to the CPU. become.

To avoid this problem, the use of instructions with set addressing first imposes the aforementioned constraint (1). From this restriction (1), it is guaranteed that the store instruction (C) to the block does not appear between the above-mentioned principles (B) and (E), and the above problem can be avoided.

Next, the constraint (2) will be described with a specific example. Consider a case where a situation occurs in which processing is performed by the following processing (A) to (D).

(A) After the block corresponding to the real address X is transferred to the cache, the prefetch instruction with set address designation to the cache block I for the real address X is executed (B) The block corresponding to the real address X is cached To the cache block K (different from I and K) for the real address X after being transferred to

(C) Execution of store instruction of data to real address X by designation of set address I (D) Execution of load instruction of data of real address X by designation of set address K

After completion of the above processes (A) and (B), the main memory block corresponding to the real address X exists in both cache blocks I and K. After that, processing (C)
Thus, the data of the real address X held by the set address I is rewritten. At this point, the data held by the set address K is not the latest. When the process (D) occurs in this situation, the old data of the real address X is returned to the CPU.

The above problem can be avoided by imposing the constraint (2) on the code generation. That is, when the instructions (A), (B), (C), and (D) with set address designation for accessing the same main memory block are executed, the designated set addresses are made the same to avoid the above problem.

The above problem may occur even when a function is called. That is, at the time of calling a function, if a set addressing instruction is executed between the function calling side and the function side, if it is not guaranteed that the same cache block is specified for the same block in main memory, The problems mentioned above will occur. Therefore, if the above conditions are not guaranteed, the specified set address must be invalidated before the call. Constraint (3) makes it clear.

According to this embodiment, cache misses due to cache block competition can be reduced, that is, cache pollution can be prevented. Below, a suitable example of use of this example is explained.

FIG. 10 shows an example of data access using the cache memory device of this embodiment. Reference numeral 1001 represents a sequence of sequentially accessing an array on the main memory that is larger than the capacity of the cache memory. 1002
Represents the state of the cache before accessing such an array. It is assumed that four vertically arranged rectangular columns correspond to one block of the cache. Each block of the cache stores a copy of the main memory data that has been accessed so far. Some of these data include
It includes data that will be used multiple times in the future.

Reference numeral 1003 represents a normal cache memory state when the large array is accessed. Generally, a main memory block is uniquely mapped to a cache memory block. Therefore, when sequentially accessing such a large array, even if the array data is used only once, data that is originally in the cache and may be used in the future is also evicted from the cache. And when the evicted block is accessed again,
A cache miss occurs.

Reference numeral 1004 denotes the state of the cache memory when the above-mentioned prefetch with set address designation, load, store, and invalidation instruction are used in the cache memory device of this embodiment. For large arrays, the compiler or programmer decides which cache blocks 1005, 1006, 1007 to use and uses these blocks repeatedly with set-addressed instructions. This avoids existing block evictions that have occurred throughout the cache.

In the above embodiment, the set associative method is adopted as the mapping method between the main memory device and the cache memory, the number of ways is 2, and one of the ways is the access target of the memory access instruction with the set address designation. (Access with an explicitly specified set address). However, when adopting the set associative method, the number of ways is not limited to this and may be any number. The way to be accessed by the memory access instruction with set address designation may be an arbitrary number of one or more ways. When two or more ways are to be accessed by a memory access instruction with set address designation, the cache block of the set address designated in those ways is the access target, and any one of them may be used. Furthermore, it is also possible to apply to the direct map method.

[0106]

According to the present invention, the prefetch instruction with set address designation allows the data to exist in the cache before it is actually used privately. This allows
It is possible to reduce misses due to initial reference, which is one of the causes of cache misses, and improve the execution efficiency of the processor. Furthermore, the cache block to be used can be arbitrarily designated by software by the prefetch with set address designation, load, store, and invalidation instruction. As a result, it is possible to prevent the cache memory from being contaminated when, for example, a large array is sequentially accessed. From the above, it is possible to avoid the problem of cache memory pollution due to infrequently used data, and to reduce the cache misses and improve the execution efficiency of the processor by positively using the information about the memory access that the programmer and compiler have. A cache memory device capable of performing the above is provided.

[Brief description of drawings]

FIG. 1 is a block diagram of a computer system to which a cache memory device according to an embodiment is applied.

FIG. 2 is a block diagram showing a configuration of a cache memory device according to an embodiment.

FIG. 3 is a diagram showing a prefetch instruction with set address designation.

FIG. 4 is a diagram showing a load instruction with set address designation.

FIG. 5 is a diagram showing a store instruction with set address designation.

FIG. 6 is a diagram showing a cache block invalidating instruction with set address designation.

FIG. 7 is a flowchart showing the operation of the cache control circuit when a prefetch instruction with set address designation is executed.

FIG. 8 is a flowchart showing the operation of the cache control circuit when executing a load instruction with set address designation.

FIG. 9 is a flowchart showing the operation of the cache control circuit when executing a store instruction with set address designation.

FIG. 10 is a diagram showing a preferred usage example of the cache memory device according to the present invention.

[Explanation of symbols]

101 ... Processor (CPU), 102 ... Main storage device,
103 ... Cache memory device, 104 ... Memory control unit, 105 ... Memory unit, 201 ... Real address storage means,
Reference numeral 202 ... Set address storage means, 203, 204 ... Way, 205, 207 ... Block address storage means, 2
06, 208 ... Block data storage means, 215, 21
6, 217 ... Comparator, 222 ... Cache control circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoichi Takeuchi, 1099, Ozenji, Aso-ku, Kawasaki-shi, Kanagawa, Ltd. Inside the Hitachi, Ltd. System Development Laboratory (72) Inventor, Sumio Kikuchi, 1099, Ozen-ji, Aso-ku, Kawasaki, Kanagawa Hitachi Systems Development Laboratory

Claims (11)

[Claims] 1. A processor is located between a processor and a main memory,
A cache memory device for performing high-speed memory access in response to a main memory access instruction from the processor by caching data stored in the main memory device in a cache memory, the first access means using a real address. And a software-controllable cache memory device comprising: a second access means by a set address of the cache memory designated by an instruction. 2. Located between the processor and the main memory,
A cache memory device that performs high-speed memory access in response to a main memory access instruction from the processor by caching data stored in the main memory device in a cache memory. Received an order,
While performing a memory access operation according to the instruction,
First access means for performing caching using a cache block determined based on a real address designated by the instruction, and a memory access instruction with a set address designating a real address and a set address for identifying the cache block In response to the instruction, the memory access operation is performed, and second access means for performing caching using a cache block determined based on a set address specified by the instruction is provided. Software controllable cache memory device. 3. The second access means includes: (a) prefetch with set address designation for prefetching a block of the main storage device containing data of a designated real address in a cache block of a designated set address. An instruction, and (b) a load instruction with set address designation for loading data from the cache block of a designated set address to the processor, and (c) data from the processor to a cache block of a designated set address. And a set addressing cache block invalidating instruction for invalidating a copy of the block of the main storage device stored in the cache block of the designated set address. Accepted according to claim 1 or 2. Cache memory device. 4. A set associative method is adopted as a mapping method between the main memory device and the cache memory, and the second access means makes access to one or more specific ways in the set associative method. Item 3. The cache memory device according to item 1 or 2. 5. When the second access means receives the prefetch instruction with set address designation, first, the data indicated by the real address designated by the instruction is
Check whether or not the cache block exists based on the real address, and (a) if so, invalidate the cache block,
Transfer the block on the main storage device containing the data indicated by the real address designated by the instruction to the cache block of the set address designated by the instruction, and (b) if it does not exist, the set designated by the instruction Check whether the data indicated by the real address specified by the instruction exists in the cache block of the address, and (b
1) If it does not exist, the cache memory according to claim 3 which transfers a block on the main storage device containing data indicated by a real address designated by an instruction to a cache block of a set address designated by an instruction apparatus. 6. The second access means, when receiving the load instruction with set address designation, first, the data indicated by the real address designated by the instruction is:
Check whether or not the cache block exists based on the real address, and (a) if so, invalidate the cache block,
Transferring a block on the main storage device containing the data indicated by the real address specified by the instruction to the cache block of the set address specified by the instruction, and returning the data in the transferred block to the processor, (B) If it does not exist, it is checked whether or not the data indicated by the real address specified by the instruction exists in the cache block of the set address specified by the instruction.
1) If present, return the data to the processor,
(B2) If it does not exist, the block on the main storage device including the data indicated by the real address designated by the instruction is transferred to the cache block of the set address designated by the instruction, and within the transferred block 4. The cache memory device according to claim 3, wherein the data of the above is returned to the processor. 7. When the second access means receives the store instruction with set address designation, first, the data indicated by the real address designated by the instruction is:
Check whether or not the cache block exists based on the real address, and (a) if so, invalidate the cache block,
Transfer the block on the main memory containing the data indicated by the real address specified by the instruction to the cache block of the set address specified by the instruction, and transfer the data given by the processor to the transferred block. (B) If it does not exist, it is checked whether the data indicated by the real address specified by the instruction exists in the cache block of the set address specified by the instruction, and (b)
1) If it exists, the data given from the processor is stored in the block. (B2) If it does not exist, it is stored in the cache block of the set address specified by the instruction.
4. The cache memory device according to claim 3, wherein a block on the main storage device including data indicated by a real address designated by an instruction is transferred, and the data given by the processor is stored in the transferred block. 8. The cache memory device according to claim 1, further comprising means for transferring data between cache blocks without going through a main memory. 9. When the second access means receives the prefetch instruction with set address designation, first, the data indicated by the real address designated by the instruction is
It is checked whether or not the cache block determined based on the real address exists, and (a) if so, the data of the cache block is
After the transfer to the cache block of the set address specified by the instruction, invalidation is performed. (B) If it does not exist, the data indicated by the real address specified by the instruction is stored in the cache block of the set address specified by the instruction. Check if it exists, (b
1) If not present, the cache memory according to claim 8 which transfers a block on the main storage device including data indicated by a real address designated by an instruction to a cache block of a set address designated by an instruction apparatus. 10. The second access means, when receiving the load instruction with set address designation, first, the data indicated by the real address designated by the instruction is:
It is checked whether or not the cache block determined based on the real address exists, and (a) if so, the data of the cache block is
After transferring to the cache block of the set address specified by the instruction, invalidating it, and further returning the data in the transferred block to the processor and loading it into the specified register. (B) If it does not exist, It is checked whether the data indicated by the real address specified by the instruction exists in the cache block of the specified set address, and (b
1) If it exists, the data is returned to the processor and loaded into the specified register. (B2) If it does not exist, it is stored in the cache block of the set address specified by the instruction with the real address specified by the instruction. 9. The cache memory device according to claim 8, wherein a block on the main memory device containing the indicated data is transferred, and the data in the transferred block is returned to the processor and loaded into a designated register. 11. When the second access means receives the store instruction with set address designation, first, the data indicated by the real address designated by the instruction is:
It is checked whether or not the cache block determined based on the real address exists, and (a) if so, the data of the cache block is
After transferring to the cache block of the set address specified by the instruction, invalidating it, and further storing the data given from the processor in the transferred block, (b) If it does not exist, the set specified by the instruction Check whether the data indicated by the real address specified by the instruction exists in the cache block of the address, and (b
1) If it exists, the data given from the processor is stored in the block. (B2) If it does not exist, it is stored in the cache block of the set address specified by the instruction.
9. The cache memory device according to claim 8, wherein a block on the main storage device including data indicated by a real address designated by an instruction is transferred, and the data given by the processor is stored in the transferred block.