JP3006204B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus for executing a load instruction at a high speed in a memory access in an electronic computer, particularly when a load instruction has a high frequency and a long time is required for this processing. Things.

[0002]

2. Description of the Related Art FIG. 4 is a schematic block diagram of a conventional information processing apparatus. Hereinafter, a conventional information processing apparatus will be described with reference to FIG. Reference numeral 110 denotes a register unit for storing the contents of the register, 102 denotes a register file including a plurality of words, 101 denotes an arithmetic processing unit having the register file 102, and 103 denotes a data cache memory or a main memory which is a buffer memory of a main memory. 104 is a data bus for store instructions, 105 is a data bus for load instructions, 108 is a register number for indicating a register in a register file, and 109 is an address for indicating data inside the data storage unit 103. is there. The operation when the load instruction and the store instruction are executed by the arithmetic processing unit 101 in accordance with the instruction sequence represented by the following equation (Equation 1) will be described.

[0003]

(Equation 1)

Here, load indicates a load instruction, store indicates a store instruction, (100) and the like indicate data having an effective address of 100, and r0 and the like indicate a register number 108. For example, the load instruction in the first row of the instruction sequence of (Equation 1) is a process of storing data having an effective address of 100 in the register r0 of the register number 108. This corresponds to 1 indicated by the address 109 in the data storage unit 103.
In this operation, the data A at address 00 is transferred via the load data bus 105 and stored in the register r0 of the register number 108 in the register file 102. on the other hand,
The store instruction is the reverse operation of the load instruction, and the store instruction in the third row of the (1)
This is a process of storing the data of the register r2 in the data storage unit 103 at the address 300 indicated by the address 109.
This corresponds to register number 10 in register file 102.
The data C of the r2 register 8 is stored in the data bus 1 for storage.
In this operation, the data is transferred via the data storage unit 04 and stored at the address 300 indicated by the address 109 in the data storage unit 103. The load instruction in the fourth row of the instruction sequence of (Equation 1) stores the data whose effective address is 100 in r3 of the register number 108.
This is the process of storing in the register. This is an operation of transferring the data A at address 100 indicated by the address 109 in the data storage unit 103 via the load data bus 105 and storing the data A in the register r3 of the register number 108 in the register file 102. The first of the instruction sequence of (Equation 1)
The data at the same effective address as the load instruction on the line is stored in a different register. Such a load instruction is often removed by compiler optimization, but cannot be removed only by optimization.

[0005]

However, in the above configuration, when data loaded by a previous load instruction is reloaded by a subsequent load instruction, data of the same effective address as that of the previous load instruction is different. Since the data is stored in the register, the data storage unit is accessed again, which causes an increase in the processing time and a problem that the processing efficiency of the information processing apparatus is reduced.

SUMMARY OF THE INVENTION In view of the above problems, the present invention provides an information processing apparatus that does not need to be reloaded when the effective address of a load instruction matches the effective address of a previous load instruction and does not reduce processing efficiency. The purpose is to:

[0007]

In order to solve the above-mentioned problems, an information processing apparatus according to the present invention provides an information processing apparatus in which each word has a register file including a register section, an effective address storage section, and an effective bit storage section. A data storage unit comprising a processing unit and a data cache memory or a main memory, wherein data read or written to the data storage unit is read by an instruction for data transfer between the register file and the data storage unit; Are registered in the register file, and the effective address of the data according to the instruction for performing the data transfer from the data storage unit to the register file and the data previously stored in the register in the register file are stored. Is compared with the effective address corresponding to the When the valid bit of the data of the register is set, the data previously stored in the register, the effective address, and the valid bit are stored in the register and the effective address storage unit corresponding to the instruction for performing the data transfer from the memory to the register. And a process for copying and storing the data in the effective bit storage unit, and corresponding to an effective address of data by an instruction for performing data transfer from the register file to the data storage unit and data previously stored in a register in the register file. Comparing the effective address with the effective address to reset the valid bit of the register that was previously set and storing data by an instruction for performing data transfer from the register to the memory in the data storage unit, When a logical arithmetic operation instruction is executed in the arithmetic processing unit, It is characterized in that performing data valid bit reset to operation result corresponding to the register for storing over data processing to be stored in this register.

[0008]

According to the present invention, when the same data as the previously loaded data is reloaded by a subsequent load instruction, the present invention provides the same effective address as the previous load instruction instead of executing the subsequent load instruction. By copying and storing the data in a different register, the processing efficiency of the information processing apparatus can be improved without causing an increase in processing time due to accessing the data storage unit again.

[0009]

FIG. 1 is a schematic block diagram of an information processing apparatus according to an embodiment of the present invention. In FIG. 1, reference numeral 10 denotes a register unit for storing the contents of a register, 2 denotes a register file comprising a plurality of words, 1 denotes an arithmetic processing unit having a register file, and 3 denotes a data cache memory or a main memory which is a buffer memory of a main memory. , 4 is a data bus for a store instruction, 5 is a data bus for a load instruction, 8 is a register number for indicating a register in the register file 2, and 9 is data in the data storage unit 3. Address. Reference numeral 6 denotes a valid bit storage unit that stores a valid bit indicating that the data of the register is valid, corresponding to the register in the register file 2, and 7 denotes data that is read from or written to the data storage unit 3 by a load instruction or a store instruction. Is an effective address storage unit that stores the effective address of the register corresponding to the register in the register file 2.

The operation of the information processing apparatus configured as described above will be described below. The operation in the case where the load instruction and the store instruction are executed in the arithmetic processing unit 1 in accordance with the instruction sequence represented by the following equation (Equation 2) will be described.

[0011]

(Equation 2)

The load instruction in the fourth row of the instruction sequence of (Equation 2) is a process of storing data having an effective address of 100 in the register r3 of register number 8. When the effective address 100 of the data by the load instruction is compared with the effective address of the data previously stored corresponding to the register in the register file 2 and they match, and when the valid bit of the data of the register is set, That is, in this case, the load data A, the effective address 100, and the effective bit 1 previously stored in the register r0 are copied and stored in the register of the register number r3, the effective address storage unit, and the effective bit storage unit corresponding to the load instruction. I do. The load instruction in the fifth row of the instruction sequence of (Equation 2) stores the data whose effective address is 300 in the register number r4.
This is the process of storing in the register. When the effective address 300 of the data by the load instruction is compared with the effective address of the data previously stored corresponding to the register in the register file 2 and they match, and the valid bit of the data of the register is set, That is, the register r2
To previously stored data C, effective address 30
0 and valid bit 1 are copied and stored in the register of register number r4 corresponding to the load instruction, the effective address storage unit, and the valid bit storage unit, respectively.

FIG. 2 shows an operation when data is transferred from a register to a memory in the information processing apparatus shown in FIG. The operation in the case where the load instruction / store instruction and the arithmetic sum operation instruction are executed in the arithmetic processing unit 1 in accordance with the instruction sequence represented by the following equation (Equation 3) will be described.

[0014]

(Equation 3)

The store instruction in the fifth row of the instruction sequence of (Equation 3) stores the data of r3 in which the result D of the arithmetic sum operation is stored at the address 100 indicated by the address 9 in the data storage unit 3. This is the processing to be performed. First, the data D of the register r3 in the register file 2 is transferred via the storage data bus 4, and the old data A indicated by the address 100 in the data storage unit 3 is updated to D. r
The effective address 10 is stored in the effective address storage unit 7 corresponding to
0 is stored and the valid bit of the valid bit storage unit 6 is set. Further, the effective address 100 is compared with the effective address of the data previously stored in the register file 2, and the valid bit of the data of the register r0 that matches is reset.

FIG. 3 shows the operation when the arithmetic and logic operation is performed in the information processing apparatus shown in FIG.
The operation in the case where the load instruction and the arithmetic sum operation instruction are executed in the arithmetic processing unit 1 in accordance with the instruction sequence represented by the following equation (Equation 4) will be described.

[0017]

(Equation 4)

The arithmetic sum operation instruction on the fourth line of the instruction sequence of (Equation 4) is a process of storing the operation result D of r1 and r2 in the register of r0. At this time, the valid bit of the valid bit storage unit 6 of the result storage register r0 is reset.

As described above, according to the present invention, a storage unit for storing an effective address of data to be read from or written to the data storage unit by a load instruction or a store instruction and a valid bit indicating that the data is valid. By providing data corresponding to each register of the register file and registering data read / written to / from the data storage unit by a load instruction or a store instruction and an effective address and valid bit corresponding to the data in the register file, If a subsequent load instruction requires data at the same effective address as a previous load or store instruction, the data previously stored in the register corresponds to this load instruction without reloading from the data store. It can be copied and stored in the storage destination register. When updating the data at the same effective address as the previous load instruction or store instruction by the subsequent store instruction, invalidate this data and store the data at the same effective address as the previous load instruction or store instruction. By invalidating this data when the arithmetic and logic operation instruction updates the register being executed, it is possible to guarantee data consistency so that this data is not loaded again by a subsequent load instruction. As a result, when the data storage unit has a hierarchical memory configuration, when the data to be loaded exists in the lowest memory, the processing time required for the data transfer can be greatly reduced.

Although this embodiment does not consider a virtual storage mechanism, even in the case of a virtual storage information processing apparatus, when processing is switched from a currently executing process to a different process, the above-described register is not used. It goes without saying that the present invention can be effectively applied by resetting all the valid bit storage units 6 in the file 2 and invalidating the contents of the registers.

In this embodiment, a load instruction,
Although the store instruction and the arithmetic operation instruction are independent of each other, the same operation can be realized in the case of a composite instruction of arithmetic operation and load, or a composite instruction of arithmetic operation and store, and it goes without saying that the present invention can be applied. . Also,
In FIG. 2, the store data bus 4 and the load data bus 5 are provided independently of each other, but it goes without saying that one data bus can serve as both.

[0022]

As described above, according to the present invention, a storage unit for storing an effective address of data to be read from or written to a data storage unit by a load instruction or a store instruction and a storage unit for storing a valid bit indicating that the data is valid. By providing data corresponding to each register of the file and registering data read / written to / from this data storage unit by a load instruction or a store instruction and an effective address and an effective bit corresponding to the data in a register file, When a load instruction requires data at the same effective address as a previous load or store instruction, the data previously stored in the register is stored in the storage location corresponding to this load instruction without reloading from the data storage unit. It can be copied and stored in a register. Further, the data stored by the previous load or store instruction that matches the effective address of the subsequent store instruction is invalidated, and the register storing the data of the previous load or store instruction is updated by the arithmetic and logic operation instruction. Sometimes, by invalidating this data, it is possible to guarantee data consistency so that this data is not loaded again by a subsequent load instruction. Therefore, the speed of the load instruction can be increased without causing an increase in the processing time by accessing the data storage unit again, and the practical effect of application to the electronic computer is very large.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of an information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of an information processing apparatus for explaining operation in the embodiment.

FIG. 3 is a schematic configuration diagram of an information processing apparatus for explaining operation in the embodiment.

FIG. 4 is a schematic configuration diagram of a conventional information processing apparatus.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 arithmetic processing unit 2 register file 3 data storage unit 4 store data bus 5 load data bus 6 effective bit storage unit 7 effective address storage unit 10 register unit

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 12/00 560 G06F 9/34

Claims (1)

(57) [Claims] Each word has an arithmetic processing unit having a register file including a register unit, an effective address storage unit, and an effective bit storage unit, and a data storage unit including a data cache memory or a main memory. According to an instruction for performing data transfer between the register file and the data storage unit, data read or written to the data storage unit and an effective address and an effective bit corresponding to the data are registered in the register file. An effective address of data according to an instruction for performing data transfer from the storage unit to the register file is compared with an effective address corresponding to data previously stored in a register in the register file, and the effective address of the data of the register matches. If is set, the corresponding register The previously stored data, effective address, and valid bit are stored in the register file corresponding to the instruction for performing data transfer from the memory to the register .
Said register unit and performs processing for copying stored in the effective address storing unit and the valid bit storage section, the effective address of the data by the instruction for performing data transfer of the data storage unit from said register file register file Compares with the effective address corresponding to the data previously stored in the register in the middle register, and when there is a match, resets the valid bit of the previously set register and resets the effective bit of the register to transfer data from the register to the memory. When a logical arithmetic operation instruction is executed in the arithmetic processing unit, a valid bit corresponding to a register for storing data of the arithmetic result is reset and the data of the arithmetic result is reset. An information processing apparatus, which performs a process of storing in a register.