JPH0769862B2 - Cache memory device - Google Patents

Description

The present invention relates to a cache memory that stores data read from a main storage device in blocks, and one or more blocks of data read from the main storage device at a time. The present invention relates to a buffer memory device for storing and a cache memory device having a store data buffer for storing store data to a main memory device.

[Conventional technology]

Conventionally, this type of cache memory device requires writing from the buffer storage device to the cache memory, and the next block read following the block read from the main storage device to the data block held in the buffer storage device. At that time, only during the access time until the data is transferred from the main storage device to the buffer storage device.

[Problems to be Solved by the Invention]

In the conventional cache memory device described above, when writing from the buffer storage device to the cache memory, when the block read from the main storage device is newly required, the first data is buffered after the read request is issued to the main storage device. Since it is performed in the free time of the cache memory until it is written to the storage device, the state in which data is held in the buffer storage device but not written to the cache memory may continue for a long time. When there is a store request from the operation execution unit for the held block-corresponding data, access to the cache memory after the store request is interrupted, and after all writing from the buffer storage device to the cache memory is completed, To the cache memory until the store request is executed to the cache memory Can not access, there is a drawback that cause performance degradation of the system.

[Means for Solving the Problems]

A cache memory device of the present invention includes a data array that stores data read from a main storage device in block units, a buffer storage device that stores one or more blocks of data read from the main storage device at a time, In a cache memory device having a store data buffer for storing store data to a storage device, idle state detection means for detecting an idle state in which the data array is not used, and a store data buffer in the store data buffer when a read request is accepted. First detecting means for detecting that there is store data in the same area as the read request; and for detecting whether or not the write request is for a block on the buffer storage device when the write request is accepted. The idle state is detected by the second detecting means and the idle state detecting means. And the transfer of data from the buffer storage device to the data array is started, and when the first detection means detects that the store data buffer has store data in the same area as the read request, the store data is stored. The read request is made to wait until the write processing according to the above is completed, and when the write request is detected by the second detection means to be a block on the buffer storage device, the read request is still in the buffer storage device. And a control means for activating the transfer of entries whose transfer to the cache memory is not completed and activating the write request after the transfer processing is completed.

[Action]

When the cache memory is idle due to an instruction that does not require access to the cache memory and the cache memory is not used, data is written from the buffer storage device to the cache memory at any time, so the data retention period in the buffer storage device is shortened. The performance of the system can be prevented from being degraded.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a cache memory device of the present invention.

The request register 10 is a register that holds a request code including the type, instruction content, and validity of the access request and the address of the access request. The request code is output to the control circuit 70 by the connection 107, the request code is analyzed, and the first Required control signals are generated and distributed to the respective parts shown in the figure. On the other hand, the address output of the request register 10 is distributed to each unit as needed.

The address of the address array 20, which is the address portion of the cache memory that stores the correspondence between the block registered in the cache memory and the block of the main memory, is read via the connection 201 by the set address (connection 101), and the detection circuit At 21 a match is made to the key address in the request register 10 (line 102) and the V bit (line 202) indicating the validity of the entry stored in the address array 20 is examined. If the key addresses match and the V bit is on, the FDB signal of the connection 211 called a found block is turned on to notify the control circuit 70 that the target data exists in the cache memory. The detection circuit 53 is
Block address consisting of key address and set address held in request register 10 (connection 106)
And the output of the block address register 52 holding the block address of the data registered in the buffer storage device 51, and the entry valid bit held in the buffer control buffer 50 for each entry of the buffer storage device 51. (Hereinafter referred to as BEV bit) is checked, and if the BEV bit is on and a match of the above block address is detected, a buffer storage device match signal (hereinafter referred to as BBM signal)
Is sent to the control circuit 70 via connection 531. Also, BEV
The bits are simultaneously output by the connection 501 to the control circuit 70.

When the request register 10 receives the read request, the control circuit 70 checks the FDB signal and the BBM signal, and basically executes the following processing.

(1) When the FDB signal is off. In this case, since the requested data does not exist in the cache memory, the control circuit 70 sends a block read request to the main storage device. The request register 10 is held as it is until the read data is returned from the main memory, and the key address (connection 102) and the block address (connection 102) in the request register 10 are respectively stored in the address array 20 and the block address register 52. Ten
6) Register and if the buffer storage device 51
If the BEV bit is turned on by the previous request and valid data exists, the data in the buffer storage device 51 is transferred to the data array 40 that stores the data in the cache memory through the switching circuit 64, the connection 641, and the switching circuit 61. To do. In addition, the control circuit 70 monitors whether the data array 40 is in an idle state, that is, when there is no access request in the request register 10 and whether there is a request that does not require access to the data array 40, and in the idle state. If so, the BEV bit in the buffer control buffer 50 is written to the data array 40 via the connection lines 511 and 641, and when the writing is completed, the corresponding BEV bit in the buffer control buffer 50 is turned off. Further, the block read is a transfer request for one block of the main storage device. In the present embodiment, the buffer storage device 51 has a size of 64 bytes, and the data transfer width with the main storage device is 8 bytes. Main memory read data is output. The first main memory read data is the switching circuit
At the same time as being registered in the buffer storage device 51 via 63, it is returned to the request source via the switching circuit 64 and the switching circuit 62, and the read data from the second time onward is registered in the buffer storage circuit 51.

(2) When the FDB signal is on. In this case, the BBM signal is referred to, and if the BBM signal is off, connection 6 is made via the switching circuit 66.
The data read from the data array 40 via the data array address (connection 104) via 61, and the data read from the buffer storage device 51 at the intra-block data array address (connection 105) if the BBM signal is turned on. And is sent back to the request source.

The outline of the read request process is as described above. However, at the time of the read request, the data being processed by the store request remains in the store data buffer 33, and the area of the store is the same area as the read request. In this case, the detection circuit 34 for comparing the block address and the detection circuit 35 for comparing the data array address in the block (8-byte address)
Connect the address data of the store address buffer 31 with
The block address is input at 311 and the intra-block data array address is input at connection 312, and the block address of the read request (connection 106) and the block data array address (connection 105) are compared and there is store data in the same area. This is detected, and the control circuit 70 is notified by the connections 341 and 351 so that the control circuit 70 waits until the processing of the store request in the middle of processing is completed. When the store request is accepted by the request register 10, the block address (connection line 106) and the in-block data array address (connection line 105) are registered in the store address buffer 31, and the form of the store decoded by the control circuit 70 is designated. Store form information and a V bit (hereinafter referred to as SAV) indicating validity of the entry in the store data buffer 33.
Registered in the store control buffer 30.
At this time, the SAV bit is registered as ON, is transmitted to the detection circuits 34, 35 and the control circuit 70 via the connection 301, and is turned OFF when the store request processing is completed. When the store data (8 bytes) prepared by the operation execution unit (not shown) and the store mask indicating whether or not the store can be executed in byte units are sent after the registration of the address of the store request, each store is performed. After being registered in the data buffer 33 and the store mask buffer 32, the store control buffer 30, the store address buffer 31, the store mask buffer 32, and the store data buffer 33 are read at the same time to the main memory device.
The information read from the store control buffer 30 as the main memory request code passes through the connection 313 as the main memory request address, passes through the switching circuit 65, and the output of the store address buffer 31 is the output of the store mask buffer as the main memory store mask. However, the output of the store data buffer 33 is sent as the main memory store data, and the processing of the store request ends. If the FDB signal at the time of store request is on,
Prior to sending to the main memory device, writing of store data to the data array 40 is executed via the switching circuit 61 via the connection line 331 or is directly returned to the request source via the switching circuit 62. Further, in the store request processing, it is checked whether or not the store request address is for a block on the buffer storage device 51, and if the BBM signal is on, the data storage array from the buffer storage device 51 precedes the processing of the store request. The entry (the BEV bit in the buffer control buffer 50 is turned on) in the buffer storage device 51 which has not yet been transferred to the cache memory is transferred to 40,
After that, the store request is processed and controlled so that the data on the data array 40 and the data on the main storage device do not become inconsistent.

〔The invention's effect〕

As described above, according to the present invention, by performing writing from the buffer storage device to the cache memory at any time in an idle state where the cache memory is not used, access to the cache memory that may occur due to writing from the buffer storage device to the cache memory is performed. This has the effect of reducing the dead time and preventing system performance degradation.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a cache memory device of the present invention. 10 …… Request register, 20 …… Address array, 30 …… Store control buffer, 31 …… Store address buffer, 32 …… Store mask buffer, 33 …… Store data buffer, 40 …… Data array, 50 …… Buffer Control buffer, 51 ... Buffer storage device, 52 ... Block address register, 21,34,35,53 ... Detection circuit, 61,62,63,64,65,66 ... Switching circuit, 70 ... Control circuit .

Claims (1)

[Claims] 1. A data array for storing data read from a main storage device in block units, a buffer storage device for temporarily storing one or more blocks of data read from the main storage device, and a main storage device. In a cache memory device having a store data buffer for storing the store data, and an idle state detecting means for detecting an idle state in which the data array is not used; and a read request to the store data buffer when a read request is accepted. And first detection means for detecting that there is store data in the same area, and for detecting, when a write request is received, whether or not the write request is for a block on the buffer storage device. Means and the buffer storage device when an idle state is detected by the idle state detection means. Data transfer from the storage device to the data array, and when the first detection means detects that the store data buffer has store data in the same area as the read request, a write process for the store data is performed. Waits until the read request is completed, and when the second detection means detects that the write request is for a block on the buffer storage device, the buffer memory device still stores it in the cache memory. And a control means for activating a transfer of an entry whose transfer has not been completed and activating the write request after the transfer processing is completed.