JP3136681B2 - Data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device,
In particular, the present invention relates to a data processing device having a cache system.

[0002]

2. Description of the Related Art In recent years, demands for high-speed data processing apparatuses have been increasing. A cache system is used as one means for that.

[0003] The cache system has a cache memory, in which instructions and / or instructions in the main memory are stored.
Or a part of data is copied. When an access to the main memory is issued from the microprocessor,
The cache system detects whether the data based on the access is stored in the cache memory,
When it is detected that the data is stored (that is, when a cache hit occurs), the data is transferred from the cache memory to the microprocessor. On the other hand, if the cache system detects that the data is not stored (that is, if a cache miss occurs), the cache system reads necessary data from the main memory and transfers it to the microprocessor, and stores the data in the cache memory in preparation for the next access request. I do.

As described above, the cache system is an effective means for realizing a high processing speed for a data processing device using a memory having a low access speed such as a dynamic memory (DRAM) as a main memory. One.

[0005]

The access speed of a DRAM is certainly slow if it is for an address having no continuity. However, in accesses to consecutive addresses, a high-speed access mode called a high-speed page mode or a static column mode can be used for the second access, and data can be accessed at high speed. The access speed in the high-speed access mode is equal to the access speed of the cache memory.

However, the data processing device using the conventional cache system does not effectively use the above-described high-speed access mode of the DRAM. That is, data which can be used in the high-speed access mode of the DRAM despite the high continuity of addresses accessed by the microprocessor is registered in the cache memory. This means that a cache memory having a small storage capacity is not effectively used.

Accordingly, it is an object of the present invention to provide a data processing device having an improved cache system.

Another object of the present invention is to provide a data processing device having a cache system that can use a cache memory efficiently.

It is still another object of the present invention to provide a data processing apparatus which uses a DRAM as a main memory, effectively utilizes a high-speed access mode of the DRAM, and increases the use efficiency of a cache memory.

[0010]

According to the present invention, there is provided a data processing apparatus comprising: a main memory having a high-speed access mode; a microprocessor for issuing an access request to the memory; High-speed access mode is detected by detecting whether the address is
An access cycle identifying means for generating a block head signal indicating whether or not the block head can be used ; a cache memory; and the block head signal using a high-speed access mode in response to an access request from the microprocessor.
In the case where the data cannot be used, the data is transferred from the cache memory to the microprocessor based on the cache hit and the high-speed access mode to the main memory is prepared, while the data is transferred from the main memory to the microprocessor based on the cache miss. And register it in the cache memory,
The above block start signal can use the high-speed access mode.
Control means for transferring data from the main memory to the microprocessor in the high-speed access mode.

Thus, when the addresses by the access request from the microprocessor are consecutive, the data is transferred from the main memory in the high-speed access mode based on the request, and there is no need to register the data in the cache memory. A small cache memory can be used effectively.

The access cycle identification means may be built in a microprocessor as a single chip. Further, the cache memory and the control means may be built in the microprocessor.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The data processing device is a microprocessor 10
1. Access cycle identification circuit 100, cache system 302, main memory 30 composed of DRAM
4 and a bidirectional buffer 203. Address information and control signal information output from the microprocessor are stored in a system address / control bus 10.
2, the identification circuit 100 and the cache system 3
02. In the control signal information, B indicating at low level that the bus cycle is activated is included.
It includes a CY signal, an MRQ signal indicating that the access target is the main memory 304 at a low level, and an R / W signal indicating whether data is read or written at a high level and a low level, respectively. A clock signal 107 is supplied to the microprocessor 101 and the cache system 302.

The cache system 302 has a cache memory 303, and reads data requested by the processor 1 from the cache memory 303 based on access information from the microprocessor 101 and a block head signal 14 from the access cycle identification circuit 100. It controls whether to read from the main memory 304. Data read from the cache memory 303 is supplied to the microprocessor 1 via the system data bus 408. At this time, the buffer enable (BUFEN) signal 406 is set to the inactive high level to deactivate the buffer. On the other hand, access to the main memory 304 includes a row address strobe (RAS) signal 401, a column address strobe (CAS) signal 404, a write enable (WE) signal 404, and an output enable (O).
E) The data read from the memory 304 is executed by using the signal 405 and the address bus 407, and the data is read out from the processor via the memory data bus 409, the buffer 203 activated by the low-level BUFEN signal 406, and the system data bus 408. It is transferred to 101.

Referring to FIG. 2, the access cycle identification circuit 100 has a previous address register 131, an address comparator 133, two delay circuits 201 and 203, and a flip-flop 202,
It is connected as shown in the figure together with the address information from the control bus 102, the MRQ signal 104, the R / W signal 105 and the BCY signal 103. The address information supplied to the circuit 100 includes a microprocessor 101
Out of the access addresses from the number of data that can be accessed using the high-speed access mode of the main memory 304,
That is, the remaining upper address bits are supplied by removing the lower bits by the number of bits corresponding to the number of data in one block. For example, assuming that the number of data in one block is 8, the remaining addresses except the lower 3 bits including the least significant bit are supplied. This address information is supplied to the previous address register 131 and to one input of the comparator 133. The other input of the comparator 133 is supplied with the output of the previous address register 131. Comparator 133 determines that MRQ signal 104 is active low and R
Activated when the / W signal 105 is high (ie, data read mode), the two inputs are compared, and they match (ie, data from the previous access and data from the current access exist in the same block). ) And set its output to high level. The output of the comparator 133 is
The BCY signal is taken into the flip-flop 202 by a delay signal from the delay circuit 201. The inverted output is extracted as a block head signal 14. The delay circuit 201 is further delayed by the delay circuit 203, and the previous address register 131 takes in address information from the bus 102 by the delay signal and the active low of the MRQ signal 104.

Therefore, the access cycle identification circuit 100 operates according to the timing shown in FIG. Note that the microprocessor 101 of the present embodiment has four of T1 to T4.
One bus cycle is executed in the state. That is, in the data read access to the main memory 304, the microprocessor starts outputting the low-level, low-level and high-level BCY signal 103, MRQ signal 104, and R / W signal 105 and address information at the start of the T1 stator, respectively. The level of these signals is T
It is determined almost in the middle of one state. When it is determined, a comparison output is generated from the address comparator 133. When both addresses match, the level is high as indicated by the solid line, and when they do not match, the level is low as indicated by the dotted line. The delay circuit 201 then outputs the delayed BCY signal, and the comparison output is latched by the flip-flop 202. After that, a low active signal is output from the delay circuit 203, and the current access address information is taken into the previous address register 131. As a result, the output of the address comparator 133 goes high even if it outputs a low level, but the state of the flip-flop 202 does not change.

Referring to FIG. 4, the cache system 3
02 denotes a cache memory controller 306 for controlling the cache memory 303, a main memory controller 305 for controlling the main memory 304, and a data ready (READY) signal 106 to the microprocessor 101 based on ready signals 501 and 502 from both controllers. And an AND gate 503 that generates The block head signal 14 is supplied to both controllers 306 and 305. The cache hit signal 504 and the cache mishit signal 505 from the cache memory controller 306 are supplied to the main memory controller 305, and it is known whether or not the data requested by the processor 101 is stored in the cache memory 303. The BUFEN signal 406 for the buffer 203 (FIG. 1) is output by the main memory controller 305. Less than,
The operation will be described with reference to the timing charts of FIGS. 1 to 4 and FIG.

When the microprocessor 101 activates the data read bus cycle A for the main memory 304, the access cycle identification circuit 100 compares the address information in the cycle A with the address in the access executed before as described above. I do. If these addresses do not match, that is, if the access is to a block in which the high-speed page mode as the high-speed access mode of the main memory 304 cannot be used, the identification circuit 100 generates a high-level block head signal 14. As a result, the cache memory controller 306 is activated, and detects whether the data requested in the bus cycle A is registered in the cache memory 303. If it is registered, the controller 306 sets the cache HIT signal 504 to the active high level, and sets the cache READY signal 501, and thus the data READY signal 106, to the active low level in the T3 state, while the cache memory 303 requests the requested data 303 from the cache memory 303. Is read. The data is transferred to the microprocessor 101 via the system data bus 408.
Is forwarded to

On the other hand, the main memory controller 305 starts a data read operation for the main memory 304 in preparation for a cache miss. That is, the RAS signal 401 is made active low while outputting a row address to the main memory address bus 407,
After that, while outputting the column address to the bus 407, CA
The S signal 402 is set to active low. WE signal 404
And OE signals are set to high and low levels, respectively. Since the active high cache hit signal 504 is received during the data read operation, the controller 30
5 holds the BUFEN signal 406 at a high level and deactivates the buffer 203.

Thus, the data in the memory read bus cycle A is transferred from the cache memory 303 to the microprocessor 101. The main memory controller 305 determines that the bus cycle following the bus cycle A is the main memory. In addition, in preparation for accessing other data in the same block as the data in the cycle A, the RAS signal 401 is kept at the active low level, and only the CAS signal is reset to the high level.

The microprocessor 101 activates the next memory read bus cycle B, and it is assumed that the data in the same cycle B exists in the same block as the data in the previous cycle A. Then, the access cycle identification circuit 10
0 outputs a low-level block head signal 14 in the future.

Thus, the cache controller 3
06 is in an inactive state.

On the other hand, the main controller 305 knows from the low level signal 14 that the data in the present bus cycle B exists in the same block as the data in the previous bus cycle A. Therefore, based on the address information supplied via the system bus 102 and since the main memory 304 is already in the high-speed page mode,
The CAS signal 402 is set to active low while outputting the column address. Of course, OE signal 405 and BUF
The EN signal 406 is also made active low. Since the target data is immediately read from the main memory 304 in the high-speed page mode, the cache controller 3
As in the case of reading data from the cache memory 303, the main memory READY signal 502, that is, the data READY signal 106 is made active low in the state T3 of the bus cycle B. As a result, the target data is transferred from the main memory 304 to the microprocessor 1 at the same access speed as the cache memory 303.
01. The data is not registered in the cache memory 303 because the cache controller 306 is in an inactive state.

Assuming that the data in the memory read bus cycle C following the bus cycle B is also in the same block, the data is transferred from the main memory 304 to the microprocessor 101 in the high-speed page mode as described above.

Assuming that the data in the next memory read bus cycle D is in a different block, the cache controller 306 checks whether the data is registered in the cache memory 302, as in the bus cycle A. On the other hand, the main memory controller 305 supplies a row address and a column address to the main memory 304 in preparation for a cache mishit. If a cache miss occurs, the cache controller 306 sets the miss HIT signal 505 to active high,
The control is shifted to the main memory controller 305.

In the main memory controller 305, since this data read operation is a normal low-speed access,
In state T3, READY signal 502, and thus 1
06 is held at a high level. That is, the wait state TW is requested to the microprocessor 101. Since the target data is prepared during the state T3, the BUFEN signal 406 and the READY signal 502
(106) are sequentially set to the active low level, and data from the main memory 304 is transferred to the bus 409 and the buffer 20.
3 and the microprocessor 101 via the bus 408.
Transfer to

R at the high level of the block head signal 14
By the active low of the EADY signal 502, the data at that time is registered in the cache memory 303.

Since data in the next memory read bus cycle E exists in the same block, target data is transferred from the main memory 304 to the microprocessor 101 in the high-speed page mode.

As described above, the present embodiment focuses on the reproducibility that a plurality of data in the same block of the memory is accessed and the same access is performed again in the memory read access of the microprocessor 101. Since only the data is registered in the cache memory 303 and other data is accessed using the high-speed access mode of the main memory, the use efficiency of the cache memory 303 can be increased without substantially lowering the access speed.

The above description has been made for memory read.
In the case of a memory write, the output signal 14 of the access cycle identification circuit 100 is invalid as described above. Although the data to be written is written to the main memory 304, only the registered data is rewritten in the cache memory 303.

In the above embodiment, the access cycle identification circuit 100 may be configured as a single chip together with the microprocessor 101. Further, the cache memory 303 and the cache controller 306 can also be incorporated in the single chip.

[0033]

As described above, according to the present invention, the high speed performance of the cache memory and the high speed access mode of the main memory are effectively utilized, and the cache memory can be effectively used without substantially reducing the processing speed. A data processing device that can be used for a computer is provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing an access cycle identification circuit of FIG. 1;

FIG. 3 is a timing chart showing the operation of FIG.

FIG. 4 is a block diagram illustrating the cache system of FIG. 1;

FIG. 5 is a timing chart showing the operation of FIG.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 12/08-12/12 G06F 12/00 550-12/06 G11C 11/401

Claims (2)

(57) [Claims] 1. A main memory having a high-speed access mode, a microprocessor for issuing an access request to the memory, and an address of the issued access request being a high-speed access of the main memory to an address of a previously issued access request. means for generating a block start signal which indicates whether or not the detected use or range may be used mode, and the cache memory, in response to an access request from said microprocessor, said <br/> block top The signal must be able to use the fast access mode.
And control means for prohibiting the registration to the cache memory of the data transfers the data by high-speed access mode from said main memory to said microprocessor when showing the bets, the block start signal is high-speed access
Access request to indicate that
Data is registered in the cache memory
Data processing apparatus comprising: a means for detecting that. 2. A main memory having a high-speed access mode, a microprocessor for issuing an access request to the memory, and an address of the issued access request being a high-speed access of the main memory to an address of a previously issued access request. means for generating a block start signal indicating whether detected using can Rukado whether the scope may be used mode, and the cache memory, in response to an access request from said microprocessor, said block top signal Fast access mode cannot be used
When a cache hit occurs, data is transferred from the cache memory to the microprocessor and a high-speed access mode for the main memory is prepared. Transfer to the processor, register in the cache memory and prepare a high-speed access mode for the main memory, and use the high-speed access mode for the block head signal.
Control means for transferring data from the main memory to the microprocessor in a high-speed access mode when it indicates that the data processing is possible.