JPH0512121A - Data processor - Google Patents

Abstract

PURPOSE:To improve the efficiency of a cache memory by utilizing a high-speed access mode provided for a main memory. CONSTITUTION:When the access cycle of memory reading is actuated from a microprocessor 101, an access cycle identification circuit 100 generates information 14 of whether or not the address of the access cycle is within the range capable of utilizing the high-speed access mode of a main memory 304 with respect to the address of a previous access cycle. A cache system prepares the high-speed access mode of the main memory 304 based on the information 14 and transfers data to the microprocessor 101 by means of the same mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device,
In particular, it relates to a data processing device having a cache system.

[0002]

2. Description of the Related Art The demand for speeding up of data processing devices has been increasing in recent years. A cache system is used as one means for that purpose.

The cache system is provided with a cache memory to which instructions and / or instructions in the main memory are stored.
Or a part of the data is copied. When the microprocessor issues an access to the main memory,
The cache system detects whether the data based on the access is stored in the cache memory,
When it is detected as stored (that is, when a cache hit occurs), the data is transferred from the cache memory to the microprocessor. On the other hand, when the cache system detects that the data has not been stored (that is, when a cache miss occurs), the cache system reads necessary data from the main memory and transfers it to the microprocessor, and stores the data in the cache memory in preparation for the next access request. To do.

As described above, the cache system is an effective means for increasing the processing speed of a data processing device using a memory having a slow access speed such as a dynamic memory (DRAM) as a main memory. Is one.

[0005]

The access speed of a DRAM is certainly slow if it is for addresses having no continuity. However, in access to consecutive addresses, a high-speed page mode or a high-speed access mode called a static column mode can be used for the second access, and data can be accessed at high speed. The access speed in the high speed access mode is equal to the access speed of the cache memory.

However, the data processing device using the conventional cache system does not effectively use the above-mentioned high-speed access mode of the DRAM. That is, even though the address accessed by the microprocessor has high continuity, data that can be used in the high speed access mode of the DRAM is also registered in the cache memory. This means that the cache memory with a small storage capacity is not being used effectively.

Accordingly, it is an object of the present invention to provide a data processing device with an improved cache system.

Another object of the present invention is to provide a data processing device having a cache system capable of efficiently using a cache memory.

Still another object of the present invention is to provide a data processing device which uses a DRAM as a main memory and effectively utilizes a high speed access mode of the DRAM to improve the use efficiency of a cache memory.

[0010]

A data processor according to the present invention comprises a main memory having a high speed access mode,
A microprocessor that issues an access request to this memory and whether the address of the access request issued by the microprocessor is continuous with the address of the previously issued access request is detected, and a block start signal that becomes active when it is not generated is generated. In response to an access request from the microprocessor, the access cycle identifying means, the cache memory, and when the block head signal is active, the data is transferred from the cache memory to the microprocessor based on the cache hit and the main memory A high-speed access mode for the block is prepared, while data is transferred from the main memory to the microprocessor and registered in the cache memory based on the cache miss, and the block start signal is reset. For an active and a control means for transferring data by high-speed access mode from the main memory to the microprocessor.

Thus, when the addresses requested by the access request from the microprocessor are continuous, the data is transferred from the main memory in the high-speed access mode based on the request, and it is not necessary to register the data in the cache memory. A small cache memory can be effectively used.

The access cycle identifying means may be incorporated in the microprocessor as a single chip. Furthermore, the cache memory and the control means can be incorporated in the microprocessor.

[0013]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. This data processing device is a microprocessor 10
1. Access cycle identification circuit 100, cache system 302, main memory 30 composed of DRAM
4 and bidirectional buffer 203. The address information and control signal information output from the microprocessor are the system address / control bus 10
Identification circuit 100 and cache system 3 via 2
02. In the control signal information, B indicating that the bus cycle is activated is at a low level.
It includes a CY signal, an MRQ signal indicating at low level that the access target is the main memory 304, and an R / W signal indicating at high and low levels whether to read or write data, respectively. The clock signal 107 is supplied to the microprocessor 101 and the cache system 302.

The cache system 302 has a cache memory 303. Whether the data requested by the processor 1 is read from the cache memory 303 based on the access information from the microprocessor 101 and the block head signal 14 from the access cycle identification circuit 100. It controls whether to read from the main memory 304. The data read from the cache memory 303 is supplied to the microprocessor 1 via the system data bus 408. At this time, the buffer enable (BUFEN) signal 406 is set to inactive high level to inactivate the buffer. On the other hand, to access the main memory 304, a row address strobe (RAS) signal 401, a column address strobe (CAS) signal 404, a write enable (WE) signal 404, and an output enable (O) are used.
E) Data executed by the signal 405 and the address bus 407 and read from the memory 304 is processed through the memory data bus 409, the buffer 203 activated by the low-level BUFEN signal 406, and the system data bus 408. 101 is transferred.

Referring to FIG. 2, the access cycle identification circuit 100 has a front address register 131, an address comparator 133, two delay circuits 201 and 203, and a flip-flop 202, and has a system address /
The address information from the control bus 102, the MRQ signal 104, the R / W signal 105, and the BCY signal 103 are connected as shown. The address information supplied to this circuit 100 is the microprocessor 101.
Number of data that can be accessed using the high-speed access mode of the main memory 304 among the access addresses from
In other words, the remaining upper address bits are supplied by removing the lower bits by the number of bits corresponding to the number of data in one block. For example, if the number of data in one block is 8, the remaining addresses except the lower 3 bits including the least significant bit are supplied. This address information is supplied to the previous address register 131 and also to one input of the comparator 133. The output of the previous address register 131 is supplied to the other input of the comparator 133. In the comparator 133, the MRQ signal 104 is active low and R
The / W signal 105 is activated when the signal is high (that is, the data read mode), and both inputs are compared, and they match (that is, the data by the previous access and the data by the current access exist in the same block). Yes) and its output to high level. The output of the comparator 133 is
The delay signal of the BCY signal from the delay circuit 201 is taken into the flip-flop 202. The inverted output is taken out as the block head signal 14. The delay circuit 201 is further delayed by the delay circuit 203, and the preceding address register 131 takes in the address information from the bus 102 by the delayed signal and the active low of the MRQ signal 104.

Therefore, the access cycle identifying circuit 100 operates according to the timing shown in FIG. It should be noted that the microprocessor 101 of the present embodiment has four T1 to T4
Execute one bus cycle in the state. That is, in the data read access to the main memory 304, the microprocessor starts to output the low-level, low-level, and high-level BCY signal 103, the MRQ signal 104, the R / W signal 105, and the address information at the start of the T1 stator. The level of these signals is T
It is set in the middle of one state. When confirmed, the comparison output is generated from the address comparator 133. When the two addresses match, the level is high as shown by the solid line, and when they do not match, the level is low as shown by the dotted line. The delay circuit 201 then outputs the delayed BCY signal, and the comparison output is latched by the flip-flop 202. After that, a low active signal is output from the delay circuit 203, and the current access address information is taken into the previous address register 131. The output of the address comparator 133 becomes high level even if it outputs low level, but the state of the flip-flop 202 does not change.

Referring to FIG. 4, the cache system 3
Reference numeral 02 denotes a cache memory controller 306 that controls the cache memory 303, a main memory controller 305 that controls the main memory 304, and a data ready (READY) signal 106 to the microprocessor 101 based on ready signals 501 and 502 from both controllers. AND gate 503 for generating The block head signal 14 is supplied to both controllers 306 and 305. The cache hit signal 504 and the cache mishit signal 505 from the cache memory controller 306 are supplied to the main memory controller 305, and it is known whether or not the data requested by the processor 101 is stored in the cache memory 303. The BUFEN signal 406 to the buffer 203 (FIG. 1) is output by the main memory controller 305. Less than,
The operation will be described with reference to the timing charts of FIGS. 1 to 4 and FIG.

When the microprocessor 101 activates the data read bus cycle A for the main memory 304, the access cycle identification circuit 100 compares the address information in the same cycle A with the address in the access executed before as described above. To do. If these addresses do not match, that is, if it is an access to a block in which the high-speed page mode as the high-speed access mode of the main memory 304 cannot be used, the identification circuit 100 generates the high-level block head signal 14. As a result, the cache memory controller 306 is activated and detects whether the data requested in this bus cycle A is registered in the cache memory 303. If it is registered, the controller 306 sets the cache HIT signal 504 to the active high level and sets the cache READY signal 501, and thus the data READY signal 106 to the active low level in the T3 state, while the requested data 303 from the cache memory 303. Read out. The data is transferred to the microprocessor 101 via the system data bus 408.
Transferred to.

On the other hand, the main memory controller 305 activates a data read operation for the main memory 304 in preparation for a cache miss. That is, while outputting the row address to the main memory address bus 407, the RAS signal 401 is set to active low,
Then, while outputting the column address to the bus 407, CA
The S signal 402 is set to active low. WE signal 404
And OE signals are set to high and low levels, respectively. Since the active-high cache hit signal 504 is received during the data read operation, the controller 30
5 holds the BUFEN signal 406 at a high level and deactivates the buffer 203.

Thus, the data in the memory read bus cycle A is transferred from the cache memory 303 to the microprocessor 101. However, in the main memory controller 305, the bus cycle next to the bus cycle A is the main memory. In addition, in preparation for access to other data in the same block as the data in cycle A, the RAS signal 401 is held at the active low level and only the CAS signal is reset to the high level.

It is assumed that the microprocessor 101 starts the next memory read bus cycle B, and the data in the same cycle B exists in the same block as the data in the previous cycle A. Then, the access cycle identification circuit 10
0 will output the low level block head signal 14 from now on.

As a result, the cache controller 3
06 is in a deactivated state.

On the other hand, the main controller 305 knows from the low level signal 14 that the data in the main bus cycle B exists in the same block as the data in the previous bus cycle A. Therefore, based on the address information supplied via the system bus 102, and since the main memory 304 is already in the high speed page mode state,
The CAS signal 402 is set to active low while outputting the column address. Of course, OE signal 405 and BUF
The EN signal 406 is also made active low. Since the target data is immediately read from the main memory 304 in the high speed page mode, the cache controller 3
The main memory READY signal 502, and thus the data READY signal 106, is set to active low in the state T3 of the bus cycle B, as when 06 reads data from the cache memory 303. As a result, the target data is transferred from the main memory 304 at the same access speed as the cache memory 303.
01. The data is not registered in the cache memory 303 because the cache controller 306 is inactive.

Assuming that the data in the memory read bus cycle C following the bus cycle B is also in the same block, as described above, the data is transferred from the main memory 304 to the microprocessor 101 in the fast page mode.

Assuming that the data in the next memory read bus cycle D is in a different block, the cache controller 306 checks whether the data is registered in the cache memory 302 as in the bus cycle A. On the other hand, the main memory controller 305 supplies the row address and the column address to the main memory 304 in preparation for a cache miss. If a cache miss occurs, the cache controller 306 activates the miss HIT signal 505,
Control is transferred to the main memory controller 305.

In the main memory controller 305, since this data read operation is a normal low speed access,
READY signal 502, and therefore 1 in state T3
06 is held at a high level. That is, the wait state TW is requested to the microprocessor 101. Since the target data is prepared in the state T3, the BUFEN signal 406 and the READY signal 502 are prepared.
(106) is sequentially set to active low level to transfer data from the main memory 304 to the bus 409 and the buffer 20.
3 and the bus 408 to the microprocessor 101
Transfer to.

R at the high level of the block head signal 14
By the active low of the EADY signal 502, the data at that time is registered in the cache memory 303.

Since the data in the next memory read bus cycle E exists in the same block, the target data is transferred from the main memory 304 to the microprocessor 101 in the fast page mode.

As described above, in the present embodiment, in the memory read access of the microprocessor 101, paying attention to the reproducibility of accessing a plurality of data in the same block of the memory and performing the same access again, necessary data Since only the cache memory 303 is registered and the other data is accessed by using the high speed access mode of the main memory, the utilization efficiency of the cache memory 303 can be improved without substantially reducing the access speed.

The above description has been made for the memory read.
In the case of memory write, the output signal 14 of the access cycle identification circuit 100 is invalid as described above. Although the data to be written is written in the main memory 304, only the registered data is also rewritten in the cache memory 303.

In the above embodiment, the access cycle identifying circuit 100 may be constructed as a single chip together with the microprocessor 101. Furthermore, the cache memory 303 and the cache controller 306 can also be incorporated in the above-mentioned single chip.

[0033]

As described above, according to the present invention, the high speed of the cache memory and the high speed access mode of the main memory are effectively utilized, and the cache memory is effective without substantially reducing the processing speed. A data processing device that can be utilized for

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing an access cycle identification circuit of FIG.

FIG. 3 is a timing chart showing the operation of FIG.

FIG. 4 is a block diagram showing the cache system of FIG. 1.

5 is a timing chart showing the operation of FIG. 1. FIG.

Claims (2)

[Claims] 1. A main memory having a high-speed access mode, a microprocessor for issuing an access request to this memory, and a high-speed access of the main memory to an address of the previously issued access request. The block head signal is activated in response to an access request from the cache memory and the microprocessor, which detects whether the mode is within a usable range and generates an active block head signal when the mode can be used. In this case, the data processing device further comprises control means for transferring data from the main memory to the microprocessor in a high-speed access mode and for prohibiting registration of the data in the cache memory. 2. A main memory having a high-speed access mode, a microprocessor for issuing an access request to this memory, and an address of the issued access request to the high-speed of the main memory with respect to an address of the previously issued access request. Means for detecting whether or not the access mode can be used and generating a block head signal which becomes active when it cannot be used; cache memory; and a block head signal in response to an access request from the microprocessor. When there is a cache hit, the data is transferred from the cache memory to the microprocessor, and a high-speed access mode for the main memory is prepared. Control for transferring to the microprocessor and registering in the cache memory and preparing a high-speed access mode for the main memory, and transferring data from the main memory to the microprocessor in the high-speed access mode based on the inactivity of the block head signal. And a data processing device.