JP3299147B2 - Cache control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a cache control circuit, and more particularly to a cache control circuit used in a computer system for controlling an address comparison result.

[0002]

2. Description of the Related Art When a cache control is performed in a computer system, when a cycle is started, the control is changed depending on whether or not the data of the cycle exists in the cache or the cache. Therefore, there is an address comparator. Here, the conventional address comparator compares all bits of the address of the cache or the data of the cache and the address of the cycle. That is, it is strictly determined whether or not the data itself requested in the cycle exists in the cache or the cache. For this reason, the number of bits of the address to be compared is large,
The address comparator was large or slow.

[0003] As an example, an address of a data transfer request from an input / output control device described in a common bus transfer control system of JP-A-63-127352 is compared with an address stored in an address cache, and subsequent control is performed. To change the address comparator.

[0004]

As described above, the address comparator used for cache control in the prior art is large-scale or low-speed.

[0005] This is because, if the bus address width is M bits and the address width per cache unit is N bits, a comparator circuit for comparing (MN) bits is required. If this comparator circuit is to be constructed with a high-speed circuit, the circuit scale increases in proportion to 2 × (M−N), and the cost of the circuit increases and the circuit area increases, resulting in a large overall system. It leads to scale. Further, if this comparator is to be constructed with a small-scale circuit, the time until the comparison result is output becomes longer in proportion to (M−N), which leads to a slower operation of the entire system. .

SUMMARY OF THE INVENTION It is an object of the present invention to provide a cache control circuit in which a small and high-speed address comparator circuit is mounted in a computer system and the comparison result is used for control.

[0007]

According to the present invention, when a first bus requests a data read at an arbitrary read address of a second bus, the cache control means according to the present invention stores the read address in the write cache. A read-time write cache address comparing means for checking whether or not the address is within an address range; and when the first bus requests data write to an arbitrary write address on the second bus, the write address is stored in the write cache. Receiving the comparison result of the write cache address comparing means for checking whether or not the data is within the address range of the write cache address comparing means at the time of reading, and setting the read address to the address range of the data in the write cache. When there is a write cache When the write address is not within the address range of the data in the write cache, and when the write cache is full, the data in the write cache is written to the second bus in response to the comparison result of the write address comparing means. A write cache-second bus transfer unit, wherein the write cache-second bus transfer unit operates according to a condition when the first bus requests data writing to an arbitrary write address of the second bus. And a first bus-write cache transfer means for writing the data on the first bus to a write cache, and when the first bus requests data read at an arbitrary read address on the second bus. After the write cache-second bus transfer means operates according to the condition, A second bus-first bus transfer unit for transferring data from the second bus to the first bus, wherein the read-time write address comparison unit includes an address range of data in the write cache. The upper part of the bits indicating the address range of the data in the write cache is compared with the corresponding bits of the read address without comparing all the bits indicating the read address with the corresponding bits of the read address. It is characterized by the following.

When the first bus requests data read at an arbitrary read address of the second bus, the read-time write cache checks whether or not the read address is within the address range of the data in the write cache. Address comparing means for determining whether the write address is within an address range of data in a write cache when the first bus requests data write to an arbitrary write address on the second bus; Receiving the comparison result between the write cache address comparing means and the write cache address comparing means when the read address is within the address range of the data in the write cache; In response to the comparison result, A write cache-second bus transfer means for writing the data in the write cache to the second bus when the write address is not in the address range of the data in the write cache and when the write cache is full; A read cache address comparing means for checking whether the read address is within an address range of data in a read cache, and the read cache address comparing means after the write cache-second bus transfer means operates according to a condition. A second bus-read cache for reading data in the address range from the second bus when the read address is not in the address range of the data in the read cache and storing the read address in the read cache Transfer means After the write cache-second bus transfer means and the second bus-read cache transfer means operate according to the conditions, the data of the read address is read from the read cache and transferred to the first bus. A read cache-first bus transfer unit, wherein the write cache-second bus transfer unit operates according to a condition when the first bus requests data writing to an arbitrary write address of the second bus. And a first bus-write cache transfer means for writing the data on the first bus to a write cache, wherein the read-time write address comparison means comprises an address of data in the write cache. All bits indicating the range and the corresponding bit of the read address Without comparing the bits, the higher order bits of the bits indicating the address range of the data in the write cache are compared with the corresponding bits of the read address. All bits indicating the address range of the data in the write cache correspond to some upper bits of the bits indicating the address range of the data in the write cache, even when the corresponding read address matches. When the read addresses match, the data in the write cache is transferred to the second bus.

[0009]

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows two buses (A) in one embodiment.
1 shows a configuration of a bus bridge 1 of a bus 2 and a B bus 3).

In this system, the data amount assigned to one address unit is K bits. The A bus 2 is a bus having an address width of M bits. The B bus 3 is a bus having an address width of M bits.

The A bus interface block 4 receives a cycle executed on the A bus 2 via an A bus connection signal q, analyzes the cycle, and outputs a cache control start command a to the control circuit 5. The A bus interface block 4 outputs an A bus cycle address b to the address comparator 6, the read address cache 7, the write address cache 8, and the B bus interface block 11. Further, when the cycle executed on the A bus 2 is a write cycle, the A bus write data c is output to the write data cache 10. If the cycle is a read cycle, the read data cache output m is received from the read data cache 9 and the read data is output to the A bus 2 via the A bus connection signal q.

The control circuit 5 receives a cache control start instruction a from the A bus interface block 4 and sends a read cache control signal e to the read address cache 7 and read data cache 9 according to the value of the address comparison result d, and the write address cache 8. Write cache control signal f for write data cache 10
To the B bus interface block 11 and the control circuit status h to the A bus interface block 4. Also, B
The B bus interface block status p is received from the bus interface block 11. Further, it manages the number of data inputs / outputs of the read data cache 9 and the write data cache 10, and determines whether data exists in the read data cache 9 and whether there is free space in the write data cache 10. With the ability to

The read address cache 7 is a cache that receives the read cache control signal e from the control circuit 5 at the time of reading and stores the A bus cycle address b output by the A bus interface block 4. The value stored in the cache is output to the address comparator 6 as a read address cache output i.

The write address cache 8 is a cache that receives the write cache control signal f from the control circuit 5 at the time of writing and stores the A bus cycle address b output by the A bus interface block 4. The value stored in the cache is output to the B bus interface block 11 and the address comparator 6 as a write address cache output j.

The read data cache 9 receives a read cache control signal e from the control circuit 5 at the time of reading, and
This is a cache for storing the B bus read data k. The amount of data that can be stored in the cache is (K × 2 ＾ N) bits. The value stored in the read data cache 9 is A
It is output to the bus interface block 4 as a read data cache output m.

The write data cache 10 is a cache that receives the write cache control signal f from the control circuit 5 at the time of writing and stores the A bus write data c. The amount of data that can be stored in the cache is (K × 2 ＾ N)
Is a bit. The value stored in the cache is output to the B bus interface block 11 as a write data cache output n.

The address comparator 6 compares the A bus cycle address b from the A bus interface block 4 with the read address cache output i, or the A bus cycle address b with the write address cache output j, respectively. 5, the address comparison result d is output. Here, considering the optimum address range 2 ＾ L for a system where M>L> N, the address comparator 6 compares the A bus cycle address b and the write address cache output j with the higher (ML) Bits shall be compared. This corresponds to (L−N) for the (M−N) bit comparison circuit.
The number of bits to be compared is small by N) bits. For this reason,
The circuit is smaller than the comparator of (MN) bits. The comparison between the A bus cycle address b and the read address cache output i is performed using (MN) bits.

The B bus interface block 11 receives a B bus cycle start command g from the control circuit 5, starts a cycle for the B bus 3 via a B bus connection signal r, and sends the result to the control circuit 5 for the B bus. Output as bus interface block status p. At the time of writing, a write address cache output j from the write address cache 8 and a write data cache output n from the write data cache 10 are received. Further, at the time of reading, the A bus cycle address b from the A bus interface block 4 is received, and the read data cache 9
To output B bus read data k.

Next, the operation of the embodiment will be described in detail with reference to FIG.

First, a case where a read cycle occurs on the A bus 2 will be described.

The A bus interface block 4 having received the read cycle occurring on the A bus 2 via the A bus connection signal q outputs a read data request to the cache control start instruction a to notify the control circuit 5. At this time, the address comparator 6 compares the A bus cycle address b with the read address cache output i, and compares the A bus cycle address b with the write address cache output j, and outputs an address comparison result d. Here, the comparison between the A bus cycle address b and the write address cache output j is performed not on the address itself but on whether or not it matches the address range in which one unit is 2 @ L. In other words, the upper (M-
L) Bit comparison. Therefore, this comparison circuit is (M
Compared with the (N) -bit comparator, the number of bits to be compared is smaller by (LN) bits. Therefore, it is possible to output the address comparison result d faster than the (MN) -bit comparator.

While the A bus cycle address b and the write address cache output j match in the address comparison result d, the read cycle on the A bus is temporarily suspended, and the write data cache output j is used as an address for the write data cache. After the data in the write data cache 10 is output to the B bus, the data in the B bus is read using the A bus cycle address b as an address, and the read data is not output to the A bus. Data output to the bus may be inconsistent. This is because while the A bus cycle address b matches the write address cache output j in the address comparison result d, the B
This is because the output to the bus is suspended. If the contents are kept suspended, inconsistency will occur between the contents of the write address cache 8 and the contents read from the B bus 2 and transferred to the A bus 2.

Then, a series of operations described below are performed. Upon receiving the address comparison result d, the control circuit 5 activates a write cycle to the B bus 3 and writes the write data cache output n which is the data stored in the write data cache 10 to the address indicated by the write address cache output j.
Instruction to the B bus interface block 11 to activate a cycle for writing
Is output. In response, the B bus interface block 11 activates a write cycle for the B bus 3 via the B bus connection signal r.

When the write cycle ends, the B bus interface block 11 notifies the control circuit 5 of the end of the cycle based on the B bus interface block status p. The control circuit 5 receiving this outputs a data read request from the address indicated by the A bus cycle address b to the B bus cycle start instruction g. The B bus interface block 11 that has received the B bus cycle start instruction g executes a read cycle from the address indicated by the A bus cycle address b via the B bus connection signal r.
It starts on the bus 3.

At the end of the cycle, the B bus interface block 11 receiving the data from the B bus 3 outputs the received data to the B bus read data k and outputs a signal indicating the cycle end to the B bus interface block status p. . Upon receiving this signal, the control circuit 5 outputs a data write command to the read address cache 7 and the read data cache 9 as a read cache control signal e, and further, sends the A bus cycle address b to the A bus interface block 4 as an address. The control circuit status h is notified that the data to be read is readable.

A receiving the control circuit status h
The bus interface block 4 outputs the read data cache output m on the A bus 2 via the A bus connection signal q, and the cycle ends. Thus, a series of operations is completed.

Next, when the A bus cycle address b and the write address cache output j do not match when a read cycle occurs, the control circuit 5, which has learned from the address comparison result d that the comparison result does not match, uses the A bus. Look at the address comparison result d to know the comparison result between the cycle address b and the read address cache output i. Where A
When the bus cycle address b matches the read address cache output i, and the read data exists in the read data cache 9, the control circuit 5 determines that the data is output to the read data cache output m. The A bus interface block 4 receiving the control circuit status h outputs the read data cache output m on the A bus 2 via the A bus connection signal q, and the cycle ends.

When the A bus cycle address b does not match the read address cache output i, the control circuit 5 having received the address comparison result d issues a data read request from the address indicated by the A bus cycle address b to the B bus cycle. Output to instruction g. The B bus interface block 11 that has received the B bus cycle start instruction g starts a read cycle from the address indicated by the A bus cycle address b on the B bus 3 via the B bus connection signal r. When the read cycle is completed, the B bus interface block 11, which has received the data from the B bus 3 via the B bus connection signal r, outputs the received data to the B bus read data k and outputs a signal indicating the cycle end to the B bus.
Output to the bus interface block status p to notify the control circuit 5 of the end of the cycle. Upon receiving this signal, the control circuit 5 outputs a data write command to the read address cache 7 and the read data cache 9 as a read cache control signal e, and further, sends the A bus cycle address b to the A bus interface block 4 as an address. The control circuit status h is notified that the data to be read is readable. The A bus interface block 4 having received the control circuit status h outputs the read data cache output m on the A bus 2 via the A bus connection signal q, and the cycle ends.

Next, a case where a write cycle occurs on the A bus 2 will be described. When a write cycle occurs on the A bus 2, the write cycle is received via the A bus connection signal q, and the A bus interface block 4 that has analyzed the cycle outputs the occurrence of the write cycle to the cache control start instruction a. If there is a free space in the write data cache 10, the control circuit 5 outputs a write cache control signal f to write the A bus cycle address b to the write address cache 8 and the A bus write data c to the write data cache 10, respectively. . However, when the address of the new data does not match the output of the write address cache as described later, the data is transferred from the write data cache 10 to the B bus 3 before the write data cache is emptied. It is done after. Upon receiving this, the write address cache 8 stores the A bus cycle address b, and the write data cache 10 stores the A bus write data c. At this time, the control circuit 5 simultaneously sets the control circuit status h indicating the end of the cycle.
Is output. The A bus interface block 4 receiving this informs the A bus 2 of the end of the cycle via the A bus connection signal r.

When there is no free space in the write data cache 10, the control circuit 5 executes a cycle for writing the write data cache output n which is data in the write data cache 10 to the address indicated by the write address cache output j on the B bus 3. A B bus cycle start instruction g is output to the B bus interface block 11 for activation. In response to this, the B bus interface block 11 activates a write cycle for the B bus 3 via the B bus connection signal r, where the address is the write address cache output j and the data is the write data cache output n. When this write cycle ends, the B bus interface block 11 notifies the control circuit 5 of the end of the cycle using the B bus interface block status p. The control circuit 5 receiving this outputs a write cache control signal f to write the A bus cycle address b to the write address cache 8 and the A bus write data c to the write data cache 10, respectively. Upon receiving this, the write address cache 8 stores the A bus cycle address b, and the write data cache 10 stores
The bus write data c is stored. Here, the control circuit 5 simultaneously outputs a control circuit status h indicating the end of the cycle. Upon receiving this, the A bus interface block 4
The end of the cycle is notified to the A bus 2 via the bus connection signal q.

The comparison between the A bus cycle address b and the write address buffer output j is performed by the address comparator 6 in the range of the upper (ML) bits. The transfer of data from the write data cache 10 to the B bus 3 is performed.

Up to this point, the operation in the case where a read cycle and a write cycle have occurred on the A bus has been described. Particularly, it should be noted that the write address cache output j from the write address cache 8 used in the read cycle and the A bus are used. This is an address comparison circuit of the address comparator 6 with the A bus cycle address b from the interface block 4. This comparison circuit is a comparison circuit for comparing (M−L) bits in order to perform an address comparison in an address range of 2 ＾ L. This comparison circuit is a small-scale and high-speed comparison circuit as compared with a comparison circuit for comparing (MN) bits.

Although the embodiment used for the cache control in the bus bridge has been described, the present invention replaces the buffer control in the bridge between the memory and the input / output control device, the cache control in the bridge between the memory and the central processing unit, and the like. The same can be done.

[0035]

As described above, according to the present invention, there is an effect that the size and performance of the integrated circuit can be reduced, and further, the size and performance of the entire computer system can be reduced.

This is because the number of bits to be compared by the address comparator used for cache control is reduced, and the address comparator is reduced in scale and speed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Bus bridge 2 A bus 3 B bus 4 A bus interface block 5 Cache control circuit 6 Address comparator 7 Read address cache 8 Write address cache 9 Read data cache 10 Write data cache 11 B bus interface block a Cache control start command b A Bus cycle address c A bus write data d address comparison result e read cache control signal f write cache control signal g B bus cycle start instruction h control circuit status i read address cache output j write address cache output k B bus read data m read data Cache output n Write data cache output p B bus interface block status q A bus connection signal r B bus connection signal

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 13/36 310 G06F 12/08 G06F 13/12 330

Claims (2)

(57) [Claims] When a first bus requests data read at an arbitrary read address of a second bus, a read-time write cache checks whether the read address is within an address range of data in the write cache. Address comparing means, and the first bus is connected to the second bus.
A write cache address comparing means for checking whether the write address is within the address range of the data in the write cache when requesting data writing to an arbitrary write address on the bus of In response to the comparison result of the address comparison means, when the read address is in the address range of the data in the write cache, and when the comparison result of the write cache address comparison means is received, the write address is A write cache-second bus transfer unit that writes data in the write cache to the second bus when the address is not within the address range of the data in the write cache and when the write cache is full; Any of the second bus A first bus-write cache transfer for writing data on the first bus to the write cache after the write cache-second bus transfer means operates according to a condition when requesting data writing to a write address; And when the first bus requests data read at an arbitrary read address of the second bus, the write cache-second bus transfer means operates according to a condition. And a second bus-first bus transfer means for transferring data from the first bus to the first bus, wherein the read-time write address comparison means determines an address range of data in the write cache. Without comparing all the indicated bits with the corresponding bits of the read address, Cache control circuitry, characterized in that compared to some of the bits of the upper of the bits indicating the address range over data corresponding bit of the read address. 2. The read-time write cache for checking whether or not the read address is within an address range of data in the write cache when the first bus requests data read at an arbitrary read address of the second bus. Address comparing means, and the first bus is connected to the second bus.
A write cache address comparing means for checking whether the write address is within the address range of the data in the write cache when requesting data writing to an arbitrary write address on the bus of In response to the comparison result of the address comparison means, when the read address is in the address range of the data in the write cache, and when the comparison result of the write cache address comparison means is received, the write address is Write cache-second bus transfer means for writing data in the write cache to the second bus when the address is not within the address range of the data in the cache and when the write cache is full; A read cache address comparing unit for checking whether the data is within the address range of the data, and after the write cache-second bus transfer unit operates according to a condition, receiving an output of the read cache address comparing unit, Second bus-read cache transfer means for reading data in the address range from the second bus when the read address is not in the address range of the data in the read cache, and storing the read data in the read cache; Cache-second bus transfer means and said second bus
A read cache-first bus transfer unit that reads data of the read address from the read cache and transfers the read address data to the first bus after the bus-read cache transfer unit operates according to the condition; When the bus requests data writing to an arbitrary write address on the second bus, the data on the first bus is written to the write cache after the write cache-second bus transfer means operates according to a condition. A first bus-write cache transfer unit that writes data to the first cache; and the read-time write address comparison unit includes all bits indicating an address range of data in the write cache and corresponding bits of the read address. Without comparing the data in the write cache Cache control circuitry, characterized in that compared to some of the bits of the upper of the bits indicating the address range of the corresponding bits of the read address.