JPH0652056A - Cache memory system - Google Patents

Abstract

PURPOSE:To improve the efficiency of cache memory by attaching another cache directory on one of cache memory controllers. CONSTITUTION:A secondary cache memory controller 1 is equipped with secondary cache memory 4, a primary cache directory, 2 and a secondary cache directory 3. Also, the secondary cache memory 4 corresponds to the secondary cache directory 3. Furthermore, the primary cache directory 2 is not provided with corresponding cache memory in the secondary cache memory controller 1, and is provided with the same information as that of a primary cache directory 9 in a magnetic memory device 12. Therefore, the secondary cache memory controller 1 can be set as a condition whether or not the primary cache directory 2 and the secondary cache directory 3 should be registered on the cache memory 4. Therefore, the data other than that in primary cache memory 10 can be registered on the secondary cache memory 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory system having a plurality of cache memories, and more particularly to a cache memory having means for effectively utilizing the cache memories when the plurality of cache memories are connected in series. Regarding memory system.

[0002]

2. Description of the Related Art In a conventional computer system, a cache memory control device is connected between a host device having a high-speed memory such as a main storage device and a magnetic disk device having a low-speed memory for speeding up. It was common. When the host device issues a command to the magnetic storage device to read data, the read data is sent to the host device via the cache memory controller. At the same time, the cache memory controller kept the data and kept it resident.

Inside the cache memory controller,
Although it has a small data storage capacity, it is provided with a cache memory that can be accessed at high speed, a cache directory indicating the directory of the cache memory, and a means for controlling these, and when the data once held is read again, the magnetic disk device is accessed. Instead, the processing speed of the entire system is improved by reading the data held in the cache memory.

When the storage capacity of the cache memory becomes full, old, infrequently used data is purged,
LRU (least recently used) to write new data
A method algorithm is generally used.

By the way, some magnetic storage devices of recent years have the cache memory control device built-in, and an increasing number of computer systems have the magnetic storage device and the cache memory control device arranged in series. The configuration is shown in FIG. 2 and will be described.

The secondary cache memory controller 1, which is connected to the host device 13 via the bus 5 and the magnetic storage device 12 via the bus 6, comprises a secondary cache directory 3 and a secondary cache memory 4. The secondary cache directory 3 and the secondary cache memory 4 are usually composed of SRAM. The secondary cache directory 3 has an address or the like indicating the holding position of the data held in the secondary cache memory 4.

The magnetic storage device 12 comprises a primary cache memory control device 8 and a magnetic disk device 11. The magnetic disk device 11 is connected to the primary cache memory control device 8 by the internal bus 7. The primary cache memory control device 8 including the primary cache directory 9 and the primary cache memory 10 is a secondary cache memory control device 1
Since the same processing operation is performed, the details are omitted.

Here, the operation of this system will be briefly described. A data read command and an address are sent from the host device 13 to the secondary cache memory control device 1 via the bus 5. The sent address is compared with the secondary cache directory 3 in the secondary cache memory controller 1. If there is a match in the comparison result, the data in the secondary cache memory 4 corresponding to the address is output to the host device 13 via the bus 5. If there is no match in the comparison result, the read command and address are sent to the primary cache memory control device 8 in the magnetic storage device 12 via the bus 6. The sent address is compared with the primary cache directory 9 in the cache memory controller 8. If there is a match in the comparison result, the data in the primary cache memory 10 corresponding to the address is output to the higher-level device 13 via the bus 6, secondary cache memory control device 1 and bus 5. If there is no match in the comparison result, the read command and address are set to the magnetic storage device 12.
It is sent to the internal magnetic disk device 11 via the bus 7. The magnetic disk device 11 outputs data to the host device 13 based on the sent address. At this time, if there is a free storage area in each of the passing cache memory control devices 1 and 8, the read data and its address are held. If the storage capacity of each of the cache memory control devices 1 and 8 passing through is full, the old data that is infrequently used infrequently is wiped out based on the LRU method, and the cache memory is registered after the capacity is secured.

Although the magnetic storage device incorporating the primary cache memory control device is shown here, the same processing is performed even if the primary cache memory control device is external.

[0010]

A cache memory system including a plurality of cache memory control devices connected in series between the host device and the magnetic disk device in this manner is held by each cache memory control device. The cache memory is not effectively utilized because the storage capacity is almost the same and even if a plurality of cache memory controllers are provided, the storage capacity is almost the same as the capacity of a single cache memory controller.

When a magnetic memory device incorporating a cache memory control device is used, the size of the cache memory incorporated in the magnetic memory device becomes fixed, and when it is desired to increase the size, as described above, the two memory cells are connected in series. Although the secondary cache memory control device is connected, the secondary cache memory almost contains the data existing in the primary cache memory, resulting in waste of the cache memory. In view of the above points, the present invention provides a cache memory system that effectively utilizes the storage capacity of a cache memory control device having a plurality of stages in series.

[0012]

In order to achieve the above object, the cache memory system of the present invention comprises:

A cache memory control device having a cache memory for holding data and a cache directory indicating a holding position of the data is serially arranged between a host device such as a CPU having a high processing speed and a storage device having a low processing speed. In the cache memory system connected to a plurality of cache memory control devices, one of the cache memory control devices has a cache directory in another cache memory control device. The cache memory system of the second invention of the present application is

A magnetic storage device including a host device such as a CPU, a cache memory that holds data, and a cache memory control device that includes a cache directory indicating a holding position of the data, the host device and the magnetic storage device. 2 connected to the cache memory control device.
In a cache memory system including a secondary cache memory controller, in the secondary cache memory controller,
A cache directory identical to the cache directory in the magnetic storage device is added.

[0015]

As described above, since a cache directory other than the primary directory is added to the inside of the primary cache memory device, the secondary cache is added to the cache memory other than the secondary cache memory (for example, the primary cache). It can be controlled not to store the same data as the memory.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the cache memory control device according to the present invention will be described below with reference to FIGS. It should be noted that the same components as those of the conventional configuration are designated by the same reference numerals and detailed description thereof is omitted.

The secondary cache memory control device 1 includes a secondary cache memory 4, a primary cache directory 2 and a secondary cache directory 3. The secondary cache memory 4 corresponds to the secondary cache directory 3.
The primary cache directory 2 does not have a corresponding cache memory in the secondary cache memory control device 1, but has the same information as the primary cache directory 9 in the magnetic storage device 12. Next, the operation of the circuit shown in FIG. 2 will be described.

Since the cache memories 4 and 10 are both empty in the initial state, the primary cache memory 10 reads the corresponding data from the magnetic disk 11 when there is a request from the host device 13. Primary cache directory 9
Is set to that state, and then the same information is set to the primary cache directory 2.

On the other hand, the secondary cache memory control device 1 also
The same operation as the primary cache memory control means 8 may be performed using the secondary cache directory 3. This is a process similar to the process in the conventional cache memory control devices 1 and 8. However, for simplification of description, it is assumed that the secondary cache directory 3 is invalidated. When data transfer is repeated, the primary cache memory 10
Since there is no space left in the cache memory, it is necessary to discharge old data from the primary cache memory 10.

If the request data from the host device 13 does not exist in the primary cache memory control device 8 (miss hit) and is full, the magnetic disk 1 is passed through the bus 7.
Data from 1 enters the primary cache memory 10. At the same time, the data discharged from the primary cache memory 10 by the LRU passes through the bus 6 to generate the secondary cache directory 3 and is stored in the secondary cache memory 4.
At the same time, the changed portion of the primary cache directory 9 is also changed in the primary cache directory 2.

As described above, by having the primary cache directory inside the secondary cache memory control device 1, the secondary cache memory control system 1 stores the primary cache directory 2 and the secondary cache directory in the cache memory 3. Since it can be a condition of whether or not to register in the secondary cache memory 3,
Other data can be registered. Further, the use of the magnetic storage device having a built-in cache as in this embodiment is more effective because the capacity of the built-in cache cannot be changed.

[0022]

As described above, according to the cache memory system of the present invention, by adding another cache directory in any one cache memory control device, the cache memory control device is able to operate the entire cache memory. Therefore, it is possible to avoid holding duplicated data in each cache memory and improve the efficiency of the cache memory.

[Brief description of drawings]

FIG. 1 shows a cache memory system of the present invention using a magnetic storage device with a built-in cache memory control device.

FIG. 2 shows a conventional cache memory system using a magnetic storage device with a built-in cache memory control device.

[Explanation of symbols]

 Primary cache memory controller 2 ... Primary cache directory 3 ... Secondary cache directory 4 ... Secondary cache memory 5, 6, 7 ... Bus line 8 ... Primary cache memory controller 9 ... Primary cache directory 10 Primary cache memory 11 Magnetic disk unit 12 Magnetic storage unit 13 Host device

Claims (2)

[Claims] 1. A cache memory control device having a cache memory for holding data and a cache directory indicating a holding position of the data between a high-order device such as a CPU having a high processing speed and a storage device having a low processing speed. In a cache memory system in which a plurality of cache memory control devices are connected in series, one of the cache memory control devices has a cache directory of another cache memory control device. . 2. A magnetic storage device comprising a host device such as a CPU, a cache memory holding data, and a cache memory control device having a cache directory indicating a holding position of the data, the host device and the magnetic storage. 2 connected to the device and separate from the cache memory control device.
In a cache memory system including a secondary cache memory controller, in the secondary cache memory controller,
A cache memory system characterized by adding a cache directory identical to the cache directory in the magnetic storage device.