JPH0421222B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a storage device for a computer.

The capacity of main storage devices continues to increase due to the need for larger-scale software and lower memory element prices. As capacity increases, minimizing access overhead becomes an increasingly important issue. Cache memory is used to shorten the apparent main memory access time by storing frequently referenced data in a small capacity memory that is more expensive but faster than main memory.

In the conventional cache memory control method,
Cache memory was transparent to the processor, and all main memory space could be loaded into cache memory. For this reason, there is usually a single cache memory, and the stored contents are accessed sequentially. Furthermore, since the main memory address or the virtual address itself is used as the address at the time of reference, there is a drawback that the address length increases due to the increase in storage space, and the address calculation load on the processor increases.

In addition, in conventional cache memory control systems, the algorithm for expelling data from the cache memory is usually uniquely determined by the system, and it is not possible to apply multiple algorithms to a single cache memory. was difficult.

SUMMARY OF THE INVENTION An object of the present invention is to improve the drawbacks of the conventional cache memory control system as described above.

That is, according to the present invention, (1) a main memory device consisting of a plurality of banks, a plurality of cache memories each of which can be accessed independently, and a main memory bank specified for each of the plurality of cache memories; A bank specification register to
A control unit including a cache memory content replacement control means is provided, and a storage device is obtained in which each of the cache memories can accommodate only the contents of the bank of the main storage device designated by the bank designation register.

Furthermore, (2) a main memory device comprising a plurality of banks, a plurality of cache memories each of which can be accessed independently, and a bank specification register for specifying a bank of the main memory device for each of the plurality of cache memories. and a cache memory content replacement control unit for each of the cache memories, wherein each of the cache memories can accommodate only the contents of the bank of the main storage device designated by the bank designation register, and A storage device is obtained in which the contents replacement control unit for each cache memory can perform replacement control using a different algorithm for each cache memory depending on the access characteristics to each cache memory.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. In the figure, 10 is the main memory, 11 is the main memory address register (hereinafter referred to as MAR), and 20 is the first
30 is a second cache memory, 21 and 31 are bank specification registers (hereinafter referred to as BSR) corresponding to the first and second cache memories 20 and 30, respectively, and 22 and 32 are the first and second cache memories, respectively. a cache address register (hereinafter referred to as CAR) corresponding to the second cache memory 20, 30;
41 is a selector that selects the contents of either BSR21 or BSR31 and applies it to the bank specification section of MAR11; 42 is a selector that selects the contents of either CAR32 and applies it to the intra-bank relative address specification section of MAR11; 60 is a register BSR21 ，
31 is a control section (hereinafter sometimes referred to as a processor) including an updating means and a cache memory content replacement control means 61.

In the apparatus of the present invention, each cache memory is uniquely associated with the bank of the main storage device to be accommodated at that time. In the embodiment, the upper three bits of MAR11 are used as bank designation bits, and the main memory 1
0 address 0...0 to 0001...1 (total n bits)
Bank 000 up to the address, address 0010...from 0
0011...1 (n bits each) addresses up to bank 001,
Thereafter, banks 010, 011, 100, 101, 110, 111, total 8
Divided into banks and managed (Figure 1 Main storage device 1)
(indicated by a dashed line within 0). In the initialization phase, these three bits are set in the BSRs 21 and 31 provided for each cache memory, thereby associating the main memory bank with the cache memories 20 and 30. For example, while the BSR 21 is set to 111, the cache memory 20 can store only the contents of the main memory bank 111. CAR22 and CAR32 are composed of the lower n-3 bits of an n-bit main memory address, and specify a relative address within the main memory bank.

The output of BSR21 is given as one input to selector 41 via bus 2101, and BSR
The output of 31 is sent to selector 41 via bus 3101.
given as the other input to. selector 41
follows the signal sent from processor 60 via line 6041 to BSR2 via bus 4101.
1 or the contents of BSR31 are applied to the bank designation section of MAR11.

The contents of CAR22 and CAR32 are similarly applied to selector 42 via buses 2201 and 3201, respectively, to processor 60 and to line 6.
According to the selection signal sent via 040, CAR
Either 22 or CAR32 is bus 4201
The data is sent to the intra-bank relative address specification section of MAR11 via.

The contents of MAR11 are given to main memory 10 as its address via bus 1101. Data in main storage device 10 is connected to cache memories 20 and 30 via bus 1001. The contents of cache memories 20 and 30 are stored on bus 2, respectively.
It is connected to the processor 60 via 001 and 3001. main storage device 10 and cache memory 20,
Data transfer between 30 and 30 is performed in the same manner as in a normal cache memory, except that the cache memory corresponds to a specific main memory bank. The control unit 6 also maintains the correspondence between the cache memory contents and the main memory contents and replaces the cache memory contents.
It is controlled by the replacement control unit 61 included in 0. This part is completely similar to a conventional cache memory controller, so a description thereof will be omitted.

The operation of this embodiment will be explained in more detail.
In the initialization phase, correspondence is established between the main memory bank and the cache memory. This processing is performed under the control of processor 60 in FIG. As an example, the cache memory 20 corresponds to main memory bank 000, and the cache memory 30 corresponds to main memory bank 001.
In order to correspond to the output bus 6 of the processor 60,
000 is sent to BSR 21 via bus 6031 and set, and 001 is sent to BSR 31 via bus 6031 and set.

When the above initialization is completed, processor 60 accesses main memory 10 via cache memories 20 and 30. In other words, to access the contents of bank 000, check whether the desired data exists in the cache memory 20, and if it exists, access the bus 60.
The cache memory address is sent via bus 2001 and data is accessed via bus 2001. If not present, selector 41 via line 6040
and 42, respectively, to select buses 2101 and 2201, send an address in bank 000 to MAR11, and access main memory 10. Main memory data is transferred via the cache memory 20.

The contents of bank 001 are accessed via the cache memory 30, and the selector 4 is used when accessing the main memory.
This is done in the same way as above by sending signals to select buses 3101 and 3201 to buses 1 and 42, respectively.

This concludes the description of the first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the invention. In FIG. 2, only the minimum necessary elements are shown for explanation, and the same components as in FIG. 1 are given the same numbers. Only the parts different from the embodiment shown in FIG. 1 will be explained. 23 in Figure 2
3 is a content replacement control unit of the cache memory 20;
3 is a content replacement control unit for the cache memory 30; The internal configuration of the content replacement control units 23 and 33 is exactly the same as the conventional method, so details will not be described. There are several replacement algorithms that can be used to increase the cache memory hit rate (the probability that the desired data will be found in the cache memory), depending on the access characteristics to the data stored in the cache. Traditionally used.
For example, LRU is a method that selects the data that was accessed at the earliest point in time for eviction, and FIFO
is how to purge the oldest loaded data,
LIFO is a method of expelling the most recently loaded data, etc.

The main feature of the second embodiment of the present invention is that a content replacement control section for controlling the above-mentioned replacement algorithm is provided for each of a plurality of cache memories, so that a different replacement algorithm can be applied to each cache memory. do. That is, in FIG. 2, for example, the content replacement control unit 23 is configured to replace the content of the cache memory 20 using the LRU algorithm, and the content replacement control unit 33 is configured to replace the content of the cache memory 30 using the FIFO algorithm. . Since only the contents of a specific bank of the main memory are loaded into each cache memory, a cache memory with a high hit rate can be constructed by storing data that makes the access characteristics the same for each bank in advance. be able to.

This concludes the description of the second embodiment of the present invention.

As is clear from the above description, the present invention is a storage device that can access a large-capacity main storage device faster than conventional systems.

In the first embodiment of the present invention, by providing independent cache memories corresponding to specific banks of the main storage device, each cache memory can be accessed independently from the processor side. As long as you hit it, you can get a big performance improvement.

In the past, there was a method in which the contents of main memory were divided into attributes of instructions and data, and separate cache memories were provided for each to be loaded. This is completely different from the method of providing a storage memory. In other words, the conventional method described above cannot cope with the increase in address calculation load when the storage space increases. Further, in the conventional method described above, the access parallelism is limited to a maximum of 2 because there are only two cache memories at most.

In addition to the above invention, the second embodiment of the present invention is configured so that a content replacement algorithm can be applied independently to each cache memory, so it is possible to perform more fine-grained control according to data access characteristics. This is an efficient storage device that can improve the hit rate to cache memory.

Although the present invention has been described above using examples, these are merely examples and do not limit the scope of the claims of the present application. That is, in the embodiment, an example is shown in which two cache memories are provided, but the number may be three or more. Further, for the sake of explanation, an example is shown in which the main memory bank is divided into eight banks, but any number of banks may be used.

Furthermore, the plurality of cache memories can be configured to have different read widths, capacities, speeds of constituent elements, etc., thereby providing a more efficient storage device. In particular, if a fixed-width table is stored in each main memory bank and a cache memory with a word width that matches the width is provided, one entry of the table can be given to the processor with one access to the cache memory. . Furthermore, if this width is an integral multiple of the main memory read width, the cache memory address register length can be shortened, further reducing the address calculation load.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention. In the figure, 10 is a main memory device consisting of a plurality of banks, and 20 and 30 are independently accessible cache memories 21 and 31, respectively, bank designation registers that specify the main memory banks corresponding to the cache memories 20 and 30. , 60 is a control section that includes means for updating the bank designation registers 21 and 31 and a cache memory content replacement control section 61, and controls the entire storage device. FIG. 2 is a block diagram showing a second embodiment of the invention. In the figure, 10 is a main memory device consisting of a plurality of banks, 20 and 30
are cache memories that can be accessed independently,
23 and 33 are bank specification registers that specify main memory banks corresponding to the cache memories 20 and 30, respectively; 23 and 33 are content replacement control units that control content replacement of the cache memories 20 and 30, respectively; 60 is a bank specification register; This is a control unit that includes means for updating registers 21 and 31 and controls the storage device.

Claims (1)

[Scope of Claims] 1. A main memory device consisting of a plurality of banks, a plurality of cache memories each of which can be accessed independently, and a bank specification register that specifies the main memory bank for each of the plurality of cache memories. and a control section including a cache memory content replacement control means, and each of the cache memories is capable of storing only the contents of the bank of the main storage device designated by the bank designation register. storage device. 2. A main memory device consisting of a plurality of banks, a plurality of cache memories each of which can be accessed independently, a bank specification register that specifies a bank of the main memory device for each of the plurality of cache memories, and Each cache memory is provided with a cache memory content replacement control unit, each of the cache memories can accommodate only the contents of the bank of the main storage device specified by the bank designation register, and each of the cache memories A storage device characterized in that the content replacement control unit for each memory can perform replacement control using a different algorithm for each cache memory depending on the access characteristics to each cache memory.