JPH0573419A - Virtual storage device - Google Patents

Abstract

PURPOSE:To improve the reduction of the processing speed of a system caused by a virtual storage processing. CONSTITUTION:By providing a real memory 7 having back constitution at every page of about 64K bytes, and data lines 18, 19, address lines 14, 15, and bank selectors 5, 6 by two systems, respectively, a CPU 2 can make access to different banks simultaneously with a CPU 1. Also, the CPU 2 monitors a virtual address outputted by the CPU 1 and writes that of high access frequency in a reference memory 3, it is resolved into a bank address and a real memory address by an address decoder 4 and the rear/write of data in executed to a real memory 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device (virtual storage device) for controlling virtual storage.

[0002]

2. Description of the Related Art In a conventional virtual storage device, as shown in FIG. 2, one CPU 1 performs normal arithmetic processing and virtual storage processing. Then, in order to output the virtual memory address, the address conversion table in the real memory 9 is referred to,
If the address is on the real memory 9, the real memory 9 is directly accessed.

If it does not exist in the real memory 9, the block that is used less frequently in the real memory 9 is saved in the virtual area and the necessary block is loaded from the virtual storage area 8 onto the real memory 9.

[0004]

In the above-mentioned conventional virtual memory device, when performing virtual memory control, the original arithmetic processing is temporarily suspended to perform address conversion processing, and there is no corresponding address in the real memory. In this case, since the process of loading the block including the corresponding address from the virtual storage area is performed, the processing of the virtual storage control takes time, and the processing speed is slower than that of the information processing device that does not perform the virtual storage control. There is.

It is an object of the present invention to provide a virtual memory device that improves the above-mentioned decrease in processing speed.

[0006]

In order to achieve the above object, in the virtual storage device according to the first invention of the present application,
It has a fixed main storage capacity having a bank structure for each page of a fixed page capacity, has two lines of address lines, two lines of data lines, and two bank selectors. A second CP including a real memory that can access one address, a first CPU that performs normal arithmetic processing, and a second CPU dedicated to virtual memory processing.
U is a WAIT for temporarily stopping the first CPU
It has a dual CPU configuration consisting of signals, and the second CPU selects a bank which is not being accessed by the first CPU independently of the first CPU by using the bank selector to select a page having the memory. It has a function of page-out to the virtual area and page-in from the virtual area to the memory.

According to a second invention of the present application, the virtual memory device according to the first invention, wherein the first CP
The second CPU monitors the virtual address output by U,
A reference memory for writing a bank address that is frequently accessed and a bank address for selecting a bank of the memory according to the contents of the reference memory are output to a bank selector, and the memory address in the bank selected by the bank selector is output. And an address decoder for generating.

Further, in the virtual memory device according to the second aspect of the invention, the reference memory has an N-word register structure, and the contents can be changed by the second CPU.

[0009]

As shown in FIG. 1, a real memory 7 having a bank structure for each page of about 64 Kbytes and a data line 1 are provided.
8 and 19, address lines 14 and 15, and bank selectors 5 and 6 each have two systems, so that the CPU 2 has a CP.
Different banks can be accessed at the same time as U1. The CPU 2 monitors the virtual address output by the CPU 1 and writes the frequently accessed address in the reference memory 3, and the address decoder 4 decomposes the address into a bank address and a real memory address. Write.

[0010]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 3 is a diagram showing a configuration of a virtual address output by the CPU 1, and FIG. 4 is a diagram showing a register configuration of the reference memory 3.

In FIG. 1, the CPU 1 performs normal arithmetic processing, and the read / write operation of the memory at that time is performed in the following procedure. The CPU 1 outputs the virtual address to the CPU 2 and the address decoder 4 using the address line 11.

The address decoder 4 decomposes this virtual address into addresses A and B as shown in FIG. 3 and compares it with the register contents of the reference memory 3 shown in FIG. 4 to select a bank address that matches the address A. Output to 5.

The selector 5 selects a bank of the real memory 7, and the address decoder 4 outputs the address B to the real memory 7 through the address 1 line 14 to select the physical address of the real memory 7, thereby Read / write is performed through the line 18.

On the other hand, the CPU 2 monitors the virtual address output by the CPU 1 and counts the number of times of the address A portion of the virtual address in the internal memory, and creates the N word table shown in FIG. 5 from the one having the highest access frequency. Then, the contents are written in the register of the reference memory 3 shown in FIG.

When the CPU 1 outputs a virtual address which is not in the reference memory 3, the CPU 2 outputs the WAIT signal 10
Of the table of N words in the reference memory 3 is activated to output the address A having a low access frequency to the selector 6 using the bank address line 17 to select a bank, The contents are saved in the virtual storage area 8 (page out), and the page including the new virtual address is loaded from the virtual storage area 8 to the real memory 7 (page in).

At the same time, the contents of the reference memory 3 and the CPU
WAIT signal 1 is updated by updating the table in the internal memory of 2.
Make 0 inactive. The above is the CPU 2 in the real memory 7
And virtual storage area 8 is a virtual storage process.

However, in the above processing, the CPU 2 outputs the WAIT signal 10 to the CPU 1 (active).
When this time increases, the execution speed of the entire system decreases and the CPU2
Is capable of suppressing a decrease in processing speed by performing virtual storage processing with the algorithm shown in FIG.

According to the algorithm of FIG. 6, the CPU 2
Is page-in to the real memory 7 the page next to the page of the virtual storage area 8 currently being accessed by the CPU 1. If the next page has already been paged in to the real memory 7, nothing is done.

As a result, the CPU 2 executes the virtual memory processing in C
Since it can be performed even while PU1 is accessing the memory,
The time during which the CPU 1 is stopped due to the virtual memory processing can be reduced. The CPU 1 is stopped in the following cases. First, when the virtual addresses are continuously output in sequence, when the CPU 2 rewrites the contents of the register of the reference memory 3,
1 outputs a discontinuous virtual address due to a jump instruction or the like, and when the address A portion does not exist in the reference memory 3, the CPU 2 activates the WAIT signal 10 and C
PU1 is stopped and virtual memory processing is performed.

In most cases, the CPU 1 outputs consecutive virtual addresses during processing, so that the processing speed of the CPU 1 is not much lower than that of the one without virtual memory.

In FIG. 1, the real memory 7 has a capacity of 1
Although M bytes and page capacity are set to 64 Kbytes, this is an example and the capacity is not limited.

[0023]

As described above, the present invention has the effect that the virtual memory processing can be performed in the information processing apparatus for virtual memory without reducing the processing speed of the system.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional virtual storage device.

FIG. 3 is a diagram showing a configuration of a virtual address output to an address line 11 of FIG.

FIG. 4 is a diagram showing register contents of a reference memory 3 of FIG.

FIG. 5 is a diagram showing a configuration of an internal memory table of the CPU 2.

FIG. 6 is a diagram showing an algorithm of virtual storage processing of the CPU 2.

FIG. 7 is a diagram showing an algorithm of virtual storage processing of the CPU 2.

FIG. 8 is a diagram showing an algorithm of virtual storage processing of the CPU 2.

[Explanation of symbols]

 1 CPU 2 CPU 3 Reference Memory Register 4 Address Decoder 5 Selector 6 Selector 7 Real Memory 8 Virtual Storage Area 9 Real Memory (of Conventional Virtual Storage Device) 10 WAIT Signal 11 Address Line (Virtual Address) 12 Reference Memory Register Number 13 reference memory write data line 14 address line (real memory address) 15 address line (real memory address) 16 bank address line 17 bank address line 18 data line 19 data line

Claims (3)

[Claims] 1. A bank having a fixed main storage capacity having a bank structure for each page and having two lines of address lines, two lines of data lines, and two bank selectors. If so, it includes a real memory that can access two addresses at the same time, a first CPU that performs normal arithmetic processing, and a second CPU that is dedicated to virtual memory processing. It has a dual CPU configuration consisting of a WAIT signal for temporarily stopping, and the second CPU uses the bank selector to set a memory independently of the first CPU for a bank which is not being accessed by the first CPU. A virtual storage device having a function of selecting a page in a memory to page out to a virtual area and a page from a virtual area to a memory. 2. The virtual memory device according to claim 1, wherein the second CPU monitors a virtual address output from the first CPU and writes a bank address that is frequently accessed. And outputs a bank address for selecting a bank of the memory to the bank selector according to the content of the reference memory,
A virtual memory device having an address decoder for generating a memory address in a selected bank by a bank selector. 3. The virtual memory device according to claim 2, wherein the reference memory has a register configuration of N words,
A virtual storage device, the contents of which can be changed by a second CPU.