JP3701951B2 - Processor system using processor, main memory controller and synchronous dynamic memory - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a processor and a controller using a synchronous dynamic memory as a memory device for storing data or instructions.
[0002]
[Prior art]
In a conventional processor system, a main storage device that stores data or instructions is configured using a general-purpose dynamic memory that is inexpensive. For example, a typical configuration example of a main storage device of a workstation using a plurality of dynamic memories can be seen on pages 132 to 133 of ICCD'91 (International Conference on Computer Design) proceeding.
Such general purpose dynamic memory specifications can be found on pages 389 to 393 of the Hitachi IC Memory Handbook 2 ('91 .9). As described above, the conventional dynamic memory does not have a clock input as an input signal of the chip, and generates an internal operation clock from another control input signal in the chip at the time of reading / writing. In addition, there is no mode register for defining the operation mode of the dynamic memory inside, so that the operation mode is basically single in the conventional dynamic memory. In addition, the inside of the dynamic memory is composed of a single bank.
On the other hand, Non-Patent Document 1 has a plurality of banks as a dynamic memory that can be accessed 2 to 4 times faster than conventional ones, and the operation mode (delay from / RAS transition or / CAS transition, continuous with a built-in register). Thus, a synchronous dynamic memory in which the number of accessible words (wrap length), the order of addresses of input / output data when continuously accessed, and the like can be set is introduced.
[Non-Patent Document 1]
Nikkei Electronics 1992.5.11 (no.553) pp.143-147
[0003]
[Problems to be solved by the invention]
As described above, in a processor system that constitutes a main storage device using a general-purpose dynamic memory that does not have a clock input, a clock signal cannot be directly input to each dynamic memory chip, and each chip cannot be moved in synchronization therewith.
Therefore, it is necessary to generate a control signal for general-purpose dynamic memory on the basis of the system clock of the processor system at a timing suitable for the AC characteristics of the chip.
On the other hand, in the general-purpose dynamic memory, an internal operation clock is further generated from this control signal to control the internal operation. As described above, the processor system using the general-purpose dynamic memory has a large overhead from the system clock to the internal operation clock, and it has been difficult to construct a main storage device that operates at high speed in synchronization with the system clock.
In a processor system in which the main memory is configured with a single-mode general-purpose dynamic memory that does not have a mode register that defines the operation mode of the dynamic memory therein, it is necessary to configure the main memory according to the mode of the general-purpose dynamic memory. For this reason, it is difficult to construct a main storage device that is optimal for the processor system in terms of performance or cost.
In addition, in a processor system in which the main storage device is configured by a general-purpose dynamic memory that is internally configured by a single bank, in order to configure the main storage device in a plurality of banks, a plurality of general-purpose dynamic memories are provided accordingly. Therefore, it is difficult to construct an optimum main storage device for the processor system in terms of performance or cost.
On the other hand, the above-mentioned problem is solved by using a synchronous dynamic memory having a clock input, having a plurality of banks, and capable of setting the operation mode by a built-in register for the main memory. It becomes possible.
On the other hand, the conventional processor is based on the premise that the main memory is composed of a general-purpose dynamic memory with a single bank, so it actually has multiple banks and its operation mode is set by the built-in register. If a synchronous dynamic memory that can be used for the main memory is used, a specific means for realizing the access control of the plurality of banks and the setting of the operation mode to the built-in register is the same as that of the conventional processor. There is a problem that it is not located in any of the memories. Further, if this specific means is arranged in either a conventional processor or a synchronous dynamic memory, there is a problem that a highly versatile processor or a synchronous dynamic memory cannot be obtained.
[0004]
[Means for Solving the Problems]
In order to solve the above problems, a processor according to an exemplary embodiment of the present invention includes:
A processor core and a control device core for controlling a synchronous memory that operates based on an input clock signal, the synchronous memory having a plurality of banks including a first bank and a second bank; The processor core outputs an access address to the synchronous memory, the access address includes a row address field, a column address field, and a bank field, and the control device core is configured to store the bank field in the first access. The bit and the bit of the bank field in the second access following the first access are compared, and if they do not match, a control signal for operating the first access and the second access in parallel is It is possible to output.
More preferably, the controller core includes a first register that stores an access address in the first access, a second register that stores an access address in the second access, and a bit of a bank field in the first access. And a comparator for comparing the bank field bit in the second access.
[0005]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0006]
Overall configuration of the processor system
FIG. 1 is a block diagram of a processor system.
Reference numeral 101 denotes a microprocessor unit (hereinafter abbreviated as MPU) composed of a single chip.
Reference numeral 102 denotes a main storage device (hereinafter abbreviated as “MS”), which is composed of a plurality of synchronous dynamic memories.
A control unit 104 of the MS 102 is configured by a single chip.
Reference numeral 103 denotes a clock generator (hereinafter abbreviated as CG) of this processor system. The CG 103 supplies clock signals 150, 151, and 152 to the MPU 101, MS 102, and MC 104. These clock signals are synchronized with each other. In this embodiment, reference numerals 150, 151 and 152 denote clock signals synchronized at the same frequency. However, 150 and 151 and 150 and 152 may have a relationship of 1: N (N is an integer) or N: 1, respectively. Reference numerals 150, 151, and 152 denote synchronized signals. Therefore, each part of the processor system operates in synchronization with one system clock.
Reference numeral 153 denotes a processor bus that connects the MPU 153 and the MC 104 and includes an address, data, and a control signal. Of these, the data bus 154 is also connected to the MS 102. The data from the MS 102 is directly sent to the MPU 101 via this data bus 154.
Reference numeral 156 denotes an address or control signal from the MC 104 to the synchronous dynamic memory MS102.
The MC 104 is also connected to the input / output bus 157. The input / output bus 157 is connected to an input / output device 106 and a read only memory (hereinafter abbreviated as ROM) 105 in which programs for initial program loading, operating system boot and system initial setting are stored.
[0007]
MPU internal configuration and processor bus
FIG. 2 shows an internal configuration of the MPU 101 and a breakdown of the processor bus 153. An instruction processing unit 201 is a part that decodes an instruction and performs operations such as calculation, data (operand) extraction, data (operand) storage, and branching based on the decoded information. An instruction cache unit 202 temporarily stores instructions and supplies the instructions at high speed according to a request from the instruction processing unit 201. A data cache unit 203 temporarily stores data and supplies the data at high speed according to a request from the instruction processing unit 201. Both the cache lengths of the instruction cache unit 202 and the data cache unit 203 are 16 bytes. That is, since the data width of the processor bus 153 is 4 bytes, 16 bytes of a block corresponding to a cache miss are divided into four times and transferred from the MS 102 to each cache. A bus control unit 204 controls the processor bus. In response to a request from the instruction cache unit 202, the data cache unit 203, or the instruction processing unit 201, the processor bus 153 is activated, and necessary instructions and data are fetched from the outside or transferred to the outside.
The breakdown of the processor bus 153 is as follows.
PD0-PD31 (154): Data bus, 4 byte width. Input / output signal. The data bus 154 is directly connected to the MS 102. PD0 is the most significant bit and PD31 is the least significant bit.
PA0-PA31 (250): Address bus, 32-bit width, 4 gigabyte addressing is possible. Output signal. PA0 is the most significant bit and PA31 is the least significant bit.
PBS (251): Bus start signal. Output signal.
PR / W (252): Read / write instruction signal. When H, lead. When L, light. Output signal.
PBL (253): Block transfer instruction. Output signal.
PDC (254): Transfer end instruction. input signal.
[0008]
Allocation of processor bus space
In this system, the 4-gigabyte space addressed by PA0 to PA31 (250) is divided into four areas as shown in FIG. 3 by the upper 2 bits of the address.
MS area (301): Area to which the MS 102 is assigned.
MC register area (302): An area to which an internal register of the MC 104 is allocated.
I / O register area (303): An area to which an internal register of the I / O device 106 is allocated.
ROM area (304): Area to which the ROM 105 is allocated.
[0009]
Internal allocation of MS area and MC register area
FIG. 4 shows the internal allocation of the MS area 301 and the MC register area 302. H'00000000 to H'003FFFFF are sub-regions for bank 0. This bank corresponds to one bank in the synchronous dynamic memory. H'00400000 to H'007FFFFF are sub-regions for bank 1. This bank corresponds to the other bank in the synchronous dynamic memory. An 8-bit length MODE register is assigned to the address H′40000000 in the MC register area 302. When the MPU 101 writes an appropriate value to the MODE register, a value is set in the mode register inside the synchronous dynamic memory, and the operation mode of the synchronous dynamic memory is determined.
[0010]
Internal structure of synchronous DRAM
FIG. 5A shows the internal configuration of a single-chip synchronous dynamic memory 501 constituting the MS 102. The MS 102 is composed of four chips. The memory of this chip consists of two memory banks, bank 0 (502) and bank 1 (503). Each memory bank has a structure of 1,048,576 words × 8 bits. For this reason, the entire chip has a capacity of 16 Mbits (= 8 Mbytes). The RFADR 504 is an address counter that creates a refresh row address. A CMR 505 is a mode register that determines the operation mode of the chip 501. Reference numeral 506 denotes an internal control circuit of the chip 501. This circuit generates an internal operation signal in synchronization with a clock signal input from the outside of the chip in accordance with a control signal from the outside of the chip and a value set in the CMR 505.
[0011]
Synchronous DRAM interface signal
The interface signals of the synchronous dynamic memory 501 are as follows.
A0-A10 (550): Address signal. input. A row address and a column address are entered. The row address uses 11 bits of A0-A10. The column address uses 9 bits A0-A8. A10 at the time of column address input is used for bank designation. The mode information when CMR 505 is set is input from A0-A7.
I / O0-I / O7 (551): Data signal. Input / output. Data signal interface for read / write.
CLK (552): Clock signal. input. The value on the input signal of this chip is taken in in synchronization with the rising edge of this signal. The output is sent to the outside of the chip in synchronization with the rising edge of this signal.
/ WE (553): Write enable signal. input. Assert (Low level, hereinafter, L) when instructing data writing.
/ CAS (554): Column address strobe signal. input. Assert (L) when sending a column address.
/ RAS0, / RAS1 (555): row address strobe signals. input. Assert (L) when a row address is sent. This signal is an operation start instruction signal for each bank corresponding to each bank.
/ DQM (556): Data mask signal. input. At the time of reading, it becomes an output enable signal of I / O0-I / O7 (551). When this signal is not asserted (L) at the time of reading, the output 551 remains in a high impedance state. When writing, it becomes a write enable signal. When writing, this signal is asserted (L) to actually write data.
[0012]
Mode register field configuration
FIG. 5B shows the field structure of the CMR 505 and its contents. The RL field, CL field, and WL field are addresses A0-A2, A3-A4, and A5-A7, respectively, and the values on the corresponding address bits are taken in when the mode is set. The RL field represents a / RAS delay. For example, if 100 is set here, data is read after reading 4 clocks after assertion of / RAS. The CL field represents a / CAS delay. For example, when 10 is set here, data is read at the time of reading, two clocks after the assertion of / CAS. The WL field represents the wrap length. This chip has a function of continuously reading out data of a row designated by the same row address from a location designated by a column address in synchronization with a clock. At this time, the column address wraps around with the length specified in the WL field. For example, if 000 is specified in the WL field, the wrap length becomes 4, and 0-1-2-3, 1-2-3-0, 2-3-0-1, 3-0-1-2, etc. Wrap around.
[0013]
Main memory configuration
FIG. 6 shows the configuration of the MS 102 using four synchronous dynamic memories 501 (601, 602, 603, 604). The 8-bit data signal of each chip is connected to each byte position on the data bus 154. The clock signal 151 is the CLK552 of each chip, and A0-A10 (651), / WE, / CAS (652), / RAS0, / RAS1 (653), and / DQM (654) are input signals corresponding to each chip. Connected. Reference numerals 651, 652, 653, 654 are output signals from the MC 104.
[0014]
Internal configuration of main memory controller and bit assignment of row, column, bank
FIG. 7 shows the internal configuration of the MC 104. The inside includes a request control unit 701, an internal register control unit 702, an MS control unit 704, and an I / O control unit 709. The request control unit 701 analyzes the high-order address 2 bits of the bus cycle issued from the MPU 101 onto the processor bus 153 and determines which of the MS area 301, MC register area 302, I / O register area 303, and ROM area 304 It is determined whether it is a cycle, and control is transferred to each corresponding control unit.
In the internal register control unit 702, a control register in the MC 104 is placed. One of them is a MODE register 703 for designating an operation mode of the synchronous dynamic memory. The internal register control unit 702 monitors the address signals of the address buses PA0 to PA31 (250), detects that the address from the processor 101 accesses the mode register 505 of the synchronous dynamic memory 501, and responds to the detection result. Then, the setting information at the time of access (information from the data buses PD0 to PD31 (154)) is transferred to the mode register 505 of the synchronous dynamic memory 501. That is, when a value is written from the MPU 101 to the MODE 703, the internal register control unit 702 issues an instruction to the MS control unit 704, and sends the information written in the MODE 703 to the A0-A7 via the selector 706. A cycle for writing to the CMR 505 of the dynamic memory 501 is executed.
The MS control unit 704 controls the address signals A0 to A10 (651) of the synchronous dynamic memory 501 constituting the MS 102, and the DRAM access control unit 707 controls the control signals / WE, / CAS (652), / RAS0, / RAS1 ( 653), / DQM (654) is generated.
MADR0 (705a) and MADR1 (705b) are registers that hold access addresses of bus cycles issued from the MPU 101 to the MS area. These two registers have a FIFO (first-in first-out) configuration. The address of the first bus cycle is latched in MADR1 (705b), and the address of the subsequent bus cycle is latched in MADR0 (705a). When it is no longer necessary to hold the address of the first bus cycle, the contents of MADR0 (705a) are moved to MADR1 (705b). The contents of 705b are divided into a row address field, a column address field, and a bank field.
[0015]
The bit position of each field is shown in FIG. The 9th bit is a bank field CA10, the 10th to 20th bits are row address fields RA0 to RA10, and the 21st to 29th bits are column address fields CA0 to CA8.
When the MS control unit 704 sends out the row address, the selector 706 transfers RA0-RA10 to A0-A10 (651).
When the MS controller 704 sends a column address, CA0-CA8 is transferred to A0-A8 (651) by the selector 706, and at the same time, the bank field CA10 is transferred to A10 (651).
The CMP 714 is a comparator that compares the bank fields of MADR0 (705a) and MADR1 (705b). If the comparisons match, the access is made to the same bank, so two cycles of one synchronous dynamic memory cannot be operated in parallel. However, if the comparison does not match, it is an access to a different bank of one synchronous dynamic memory, so that two cycles can be operated in parallel. Therefore, a control signal (// RAS0, / RAS1) are generated. As a result, the throughput of the MS 102 is improved.
RFTIME 708 is a refresh timer. This issues a refresh request to the DRAM control 707 at regular time intervals in order to execute the refresh cycle of the synchronous dynamic memory 501.
The I / O control unit 709 generates an I / O control signal 758 that controls the bus cycle on the input / output bus 157.
[0016]
In addition to the present embodiment, the bit allocation of the row address field, the column address field, and the bank field as shown in FIG. 8B is also possible.
During the initial operation of the processor system, an initial operation program is read from the ROM 105 and executed. In this program, the mode setting of the synchronous dynamic memory 501 is first performed.
During the initial operation of the processor system
FIG. 9 shows a time chart at this time. The MPU 101 issues a write bus cycle of the address MA of the MODE register 703 in the MC 104 and the mode setting value MD on the processor bus 153 (clocks 2-4). In response to this, the MS control unit 704 of the MC 104 issues a mode setting cycle to the MS 102 by asserting / RAS0, / RAS1, / CAS, / WE and flowing a set value to A0-A7. This completes the mode setting of all the synchronous dynamic memories 501 (clock 5). Clock 10 indicates a refresh cycle. This is done by asserting / RAS0, / RAS1, / CAS.
[0017]
Parallel operation of two accesses in two different memory banks
FIG. 10 shows the case of two read block transfer cycles. This is the case of / RAS delay 4 clocks, / CAS delay 1 clock, and wrap length 4. A read block transfer cycle request (PBL is asserted) is issued from the MPU 101 at clocks 2 and 6. This is issued when the internal cache of the MPU 101 misses. Since the first block transfer cycle is for bank 0, / RAS0 is asserted to MS 102 at clock 3 and bank 0 is activated. At this time, the row address Ar is simultaneously sent from A0-A10. In clock 6, / CAS is asserted, and at the same time, the row address Ac is supplied. / DQM is asserted from the clock 7 in order to pass read data to the data buses PD0 to PD31. The read data A, A + 1, A + 2, and A + 3 of one block of 4 words are continuously read in synchronism with clocks 8, 9, 10, and 11. While the one block is being read, the next bus cycle (access to bank 1) starts to be activated (/ RAS1 is asserted at clock 8), and the data B, B + 1, B + 2, and B + 3 corresponding thereto start from clock 13. Read continuously for 4 clock periods. The MPU 101 is informed that read data has been received by asserting the PDC.
[0018]
FIG. 11 shows a case where a write block transfer cycle of data B, B + 1, B + 2, and B + 3 is issued after a read block transfer cycle of data A, A + 1, A + 2, and A + 3. This is the case of / RAS delay 4 clocks, / CAS delay 1 clock, and wrap length 4. A write block transfer cycle (PR / W = L) request is issued from the MPU 101 at clock 6. This is issued when the internal cache of the MPU 101 misses. Since the first block transfer cycle is for bank 0, / RAS0 is asserted to MS 102 at clock 3 and bank 0 is activated. At this time, the row address Ar is simultaneously sent from A0-A10. In clock 6, / CAS is asserted, and at the same time, the row address Ac is supplied. / DQM is asserted from the clock 7 in order to pass read data to the data buses PD0 to PD31. The read data is continuously read out in synchronization with the clocks 8, 9, 10, 11 and the clock. During the reading, the next bus cycle (access to bank 1) starts to be activated (/ RAS1 is asserted at clock 8), and when PDC is asserted at clock 12, the MPU 101 starts from the clock 13 for 4 clock periods. Data is continuously output on the data buses PD0 to PD31.
As shown in FIGS. 10 and 11, since two banks can be operated in parallel, a high-throughput main storage device can be constructed.
[0019]
Other examples
Although the embodiments of the present invention have been described above, the present invention is not limited to these specific embodiments, and it goes without saying that various modifications are possible within the scope of the basic technical idea. In the present invention, for example, the following embodiments can be employed.
[0020]
FIG. 12 is a block diagram of a processor system according to another embodiment of the present invention. The difference from the embodiment of FIG. 1 is that the processor (MPU) and the main memory controller (104) are independent cores in the same chip. Each is composed. Therefore, by adding the core of the main memory controller (MC) in the same chip, it becomes possible to use a conventional processor core and a conventional memory chip with high versatility.
As described above, according to the representative embodiment of the present invention, the means for realizing the access control of the plurality of banks of the memory constituting the main memory unit (MS) and the setting control of the operation mode of the internal register is the processor (MPU). And a main memory controller (MC) connected to the main memory device (MS), it is possible to use a conventional processor and a conventional memory with high versatility.
In the preferred embodiment of the present invention, since the processor (MPU) and the main memory control unit (104) are configured as separate chips, adding a main memory control unit (MC) enables versatility. It is possible to use a conventional processor chip and a conventional memory chip having a high height.
Further, in another preferred embodiment of the present invention, the processor (MPU) and the main memory control unit (104) are respectively constituted by independent cores in the same chip, so that the main memory control unit ( By adding a core of MC), it becomes possible to use a conventional processor core and a conventional memory chip with high versatility.
[0021]
【The invention's effect】
According to the present invention, since two banks can be operated in parallel, a high-throughput main storage device can be constructed.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a processor system according to an embodiment of the present invention.
FIG. 2 is an internal configuration diagram of an MPU.
FIG. 3 is a diagram showing area allocation of a processor bus space;
FIG. 4 is an explanatory diagram of an MS area and an MC register area
FIG. 5 is a diagram showing an internal configuration of a synchronous dynamic memory and a field configuration of a command register in the synchronous dynamic memory.
FIG. 6 is a diagram showing a configuration of a main storage device (MS).
FIG. 7 is a diagram showing an internal configuration of a main storage device control unit (MC).
FIG. 8 is a diagram showing bit allocation of row, column, and bank address.
FIG. 9 is a time chart of mode setting and refresh cycle.
FIG. 10 is a time chart of two read block transfer cycles.
FIG. 11 is a time chart of a read block transfer cycle / a write block transfer cycle.
FIG. 12 is a configuration diagram of a processor system according to another embodiment in which a processor and a main storage device are configured by independent cores in the same chip.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 101 ... Microprocessor (MPU), 102 ... Main memory unit (MS) using synchronous dynamic memory, 103 ... Clock generator (CG), 104 ... Control part (MC) of main memory device, 105 ... ROM, 106 ... I / O device, 202 ... MPU instruction cache unit, 203 ... MPU data cache unit, 501 ... Synchronous dynamic memory, 502 and 503 ... Banks in synchronous dynamic memory, 504 ... Refresh address counter, 505 ... Synchronous type Mode register in dynamic memory, 552... Clock input signal of synchronous dynamic memory, 601, 602, 603, 604... Synchronous dynamic memory constituting MS, 703... Mode register for synchronous dynamic memory in MC, 705 a. 705b ... S access address register, 714 ... MS bank field comparator for the address register access, 708 ... refresh timer.

Claims (5)

A processor core and a controller core for controlling a synchronous memory that operates based on an input clock signal;
The synchronous memory has a plurality of banks including a first bank and a second bank,
The processor core outputs an access address to the synchronous memory;
The access address includes a row address field, a column address field, and a bank field,
The control device core has a mode register that is designated by an address signal supplied from the processor core and in which information is written by a data signal in order to designate a mode of the synchronous memory,
The control device core outputs either the access address to the synchronous memory output from the processor core or the information of the mode register to the synchronous memory,
The control device core compares the bank field bit of the access address in the first access with the bit of the bank field of the access address in the second access following the first access. A processor capable of outputting a control signal for operating the first access and the second access in parallel. In claim 1,
The controller core includes a first register that stores an access address in the first access, a second register that stores an access address in the second access, a bit of a bank field in the first access, and the second access And a comparator for comparing with the bits of the bank field. In claim 2,
The first register and the second register have a FIFO configuration;
An access address in the second access stored in the second register after completion of the first access is stored in the first register. In any one of Claim 1 to 3,
The controller core first outputs the bit of the row address field, and then outputs the bit of the column address field and the bit of the bank field with respect to the access address output by the processor core. Processor. In any one of Claims 1-4,
The processor is characterized in that the control signal is a row address strobe signal.

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