JPH11212867A - Information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To use an extension bus even to an information processor which has its internal memory having capacity larger than the memory capacity that is assigned to the extension bus by always accessing the extension bus if a CPU does not access the internal memory when the CPU accesses a memory space that has a higher rank than the memory space of the extension bus. SOLUTION: This information processor includes a CPU 1, an address decoder 8, a DRAM control circuit 11, an ISA bus control circuit 13, a DRAM 12, an ISA bus 14 and a clock generation circuit 17. The CPU 1 has the DRAM 12 of 16M bytes in a PC with 80486 and can access the bus 14 by accessing an address larger than 16M bytes. In such cases, the addresses of the CPU 1 which are larger than 24 bits are disregarded since the relevant address of the bus 14 has 23 bits. Thus, it's decided that the address 000000h of the bus 14 is accessed if the CPU 1 accesses the address 01000000h.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to an information processing apparatus having an expansion bus.

[0002]

2. Description of the Related Art In a computer system such as a PC (personal computer), an expansion bus (hereinafter referred to as an ISA (InDU) is provided so that a user of the PC can expand its functions.
strial standard architect
ure) written as a bus). Various controllers or option boards corresponding to the ISA bus have been developed.

The memory space that can be used in such an ISA bus is the lower 16 Mbytes of the memory space of the CPU of the PC. Even when the lower 16 MB space is used, when a DRAM or the like exists in the PC and the memory space is used, the ISA bus access does not occur when the CPU accesses the memory space.
The ISA bus could not use that memory space. In a space above 16 Mbytes, if a DRAM or the like exists in the PC, the CPU accesses the DRAM or the like.
Will not access anything.

FIG. 12 shows a general memory map in a PC having an 80286 made by Intel and having a 4 Mbyte DRAM inside in an IBM-PC / AT compatible machine. 80286 has 16 memory spaces
M bytes. First 6 of 16 Mbytes of memory space
40K bytes (000000h to 09FFFFh) is D
Access RAM. Next 256 Kbytes (0A00
00h to 0DFFFFh) are ISA buses. Next one
28K bytes (0E0000h-0FFFFFh) is D
RAM, next 3M bytes (100000h to 3FFFF
Fh) also DRAM, next 400,000h ~ FEFFFF
h is the ISA bus, the remaining 64 Kbytes (FF0000h
To FFFFFFh) are DRAMs. FIG. 13 shows a case of a PC having a 16 Mbyte DRAM inside. 4M
The difference from the byte DRAM is 400,000h
The space of FEFFFFh also becomes a DRAM.

FIG. 14 shows that the CPU is 8048 manufactured by Intel.
6, which is a general memory map in a PC having a 4-Mbyte DRAM inside. 80486 is 4G
Although it has a memory space of bytes, the memory space of 16 Mbytes or less is the same as that of 80286.
No memory space above 16 Mbytes can be accessed by the CPU except the last 64 Kbytes. If CPU
When this memory space is read, undefined data is read, and when it is written, there is no target, so no writing is performed.

[0006]

The development of the personal computer includes increasing the speed of the CPU and increasing the capacity of the internal memory. As internal memory capacity increases, IS
The following problems have occurred in the A bus.

As described in the prior art, the memory space that can be used by the ISA bus is only an area in the lower 16 Mbytes of the memory space of the CPU that is not used by the DRAM or the like inside the PC. That is, as the internal memory increases, the area that can be used on the ISA bus decreases. In particular, as shown in FIG.
In the case of M bytes or more, the memory space that can be used on the ISA bus is 256K of 00A0000h to 00DFFFFh.
Only bytes. Moreover, in this memory space, 00A0
000h-00BFFFFh and 00C0000h-00
C7FFFFh is a VGA (Video Graphics)
The use of an array controller is standard, so the area that can actually be used on the ISA bus is even smaller.

[0008] In addition, as shown in FIG.
If the internal DRAM becomes 16 Mbytes or more, this area becomes a DRAM, and this option board cannot be used for an option board that uses all or a part of FEFFFFh. In this case, there is a method of enabling the use of the option board by disabling the internal DRAM in the area used by the option board.However, since the DRAM in the disabled portion cannot be used at all, an effective method is used. Absent.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to use an extended bus in an information processing apparatus having a memory larger than the memory capacity allocated to the extended bus. It is to provide a means.

[0010]

According to the present invention, when a CPU accesses a memory space higher than the memory space of an expansion bus, if the access is not an internal memory, the present invention always uses the expansion bus. It is characterized by accessing.

[0011]

According to the present invention, if the CPU accesses a memory space above the internal memory, the CPU can access the expansion bus regardless of the capacity of the internal memory.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a memory map according to an embodiment of the present invention. The CPU 1 is 80486 and has a 16 Mbyte D
The RAM 12 is provided inside the PC. CPU1 is 16M
By accessing the address above the byte, I
The SA bus 14 can be accessed. At this time, I
In the SA bus 14, since the address is 23 bits, the bits above the 24 bits of the CPU address are ignored. As a result, when the CPU 1 accesses the address 10000000h, the CPU 1 accesses the address 000000h of the ISA bus 14.

FIG. 2 shows the configuration of this embodiment. This embodiment includes a CPU 1 (80486), an address decoder 8, a DRAM control circuit 11, an ISA bus control circuit 13, a DRAM 12, an ISA bus 14, and a clock generation circuit 17. The clock generation circuit 17 generates a clock 16 (CLK) that serves as a reference for the operation of this embodiment. The operation of the CPU 1 is shown in FIGS. CPU
1 is valid CPU address 2, byte enable 3
(BE3 # -BE0 #), W / R # 5 is output, and ADS # 4 is activated at the same time as CP.
Start U cycle. This CPU cycle is based on ISA
The bus control circuit 13 activates RDY # 15 or BLAST # 7 output from the CPU 1 and the DRAM.
When both BRDY # 6 output from the control circuit 11 become active, the process ends. The address decoder 8 determines whether the CPU cycle is a cycle for reading / writing the DRAM 12 or a cycle for reading / writing the ISA bus 14.
Is activated, and if it is the ISA bus 14, the CISA1
Activate 0. The DRAM control circuit 11 uses the CS
When the DRAM 9 is activated, the memory address 18 and the RA for reading / writing the DRAM 12 are read.
S # 19 (Row Address Strobe),
CAS # 20 (Column Address Str)
ove). The ISA bus control circuit 13 uses the CS
When ISA 10 becomes active, ISA bus 14
ISA address 22, MEMR # 23
(Memory Read), MEMW # 24 (Mem
ory Write), ALE25 (Address)
Latch Enable) is generated. The SCLK 26 output from the ISA bus control circuit 13 is used as a reference clock of the ISA bus 14 and generally has a CL
K16 is divided to a frequency close to 8 MHz. Note that the SCLK 26 in the present embodiment is obtained by dividing CLK16 by two.

FIG. 5 shows CPU address 2 when CSDRAM 9 and CISA 10 become active.
As shown in FIG. 5, a feature of the present embodiment is that there is an area where the CISA 10 is activated even in a memory space of 16 Mbytes or more.

FIG. 6 shows CPU address 2 and CSDRAM.
9 is a timing chart showing the relationship between CISA9 and CISA10. CSDRAM 9 and CISA 10 are:
It is determined after a certain time from when the CPU address 2 becomes valid. This time is the time required to decode the address.

FIGS. 7 and 8 are timing charts showing the operation of the DRAM control circuit 11 when the CSDRAM 9 is active. FIG. 7 shows a DRAM read, and FIG. 8 shows a DRAM write. DRAM control circuit 11
Is 2CLK after ADS # 4 becomes active (FIG. 7).
Then, it is determined whether the CSDRAM 9 is active in C1) of FIG. At this time, if the CSDRAM 9 is active, it is determined that the DRAM is read / write, and the operation shown in FIG. 7 or FIG. 8 is performed. FIG. 7 and FIG.
6 burst transfers, one CPU
In the cycle, four data transfers are performed.
The lower two bits of the column address (MA1 and MA1)
0) changes as shown in FIG. CSDR at the time of C1
If AM9 is inactive, the DRAM control circuit 11
Determines that the access is not for the DRAM, and the circuit does not operate.

FIGS. 10 and 11 are timing charts showing the operation of the ISA bus control circuit 13 when the CISA 10 is active. FIG. 10 shows reading from the ISA bus 14, and FIG. 11 shows writing to the ISA bus 14. The ISA bus control circuit 13 outputs the signal 2 CLK after ADS # 4 becomes active (C in FIGS. 10 and 11).
In 2), it is determined whether the CISA 10 is active. At this time, if CISA 10 is active, IS
It is determined that the A bus 14 is to be read / written. ISA bus 1
If the read / write is 4, the CPU address is latched. The latched address is output as the address 22 of the ISA bus. 1 SCLK after C2, ALE
25 is active for 0.5 SCLK. ALE2
0.5 SCLK after 5 becomes active, MEMR # 23 becomes active in a read cycle, and MEMW # 24 becomes active in a write cycle. M
EMR # 23 or MEMW # 24 is 4.5SCL
After K, the CPU cycle returns to inactive and RDY # 15 returns to active, ending the CPU cycle.

[0019]

As described above, according to the information processing apparatus of the present invention, the option board corresponding to the expansion bus created on the assumption that the built-in memory is small can be obtained by increasing the built-in memory. Even when the internal memory uses the memory address used by the option board, the option board can be used.

[Brief description of the drawings]

FIG. 1 is a memory map according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an embodiment.

FIG. 3 is a timing chart showing the operation of a CPU in the embodiment.

FIG. 4 is a timing chart showing the operation of a CPU in the embodiment.

FIG. 5 shows CSDRAM and CSIS in the embodiment.
FIG. 6 is a diagram illustrating a condition under which A becomes active.

FIG. 6 shows CSDRAM and CSIS in the embodiment.
6 is a timing chart showing the movement of A.

FIG. 7 is a timing chart showing how the DRAM is accessed in the embodiment.

FIG. 8 is a timing chart showing how the DRAM is accessed in the embodiment.

FIG. 9 is a diagram showing a movement of lower two bits of a DRAM address in the embodiment.

FIG. 10 is a timing chart showing how an ISA bus is accessed in the embodiment.

FIG. 11 is a timing chart showing how an ISA bus is accessed in the embodiment.

FIG. 12 is a memory map in a conventional example.

FIG. 13 is a memory map in a conventional example.

FIG. 14 is a memory map in a conventional example.

[Explanation of symbols]

1 CPU (80486) 2 CPU address bus 3 CPU byte enable signal 4 ADS # signal 5 W / R # signal 6 BRDY # signal 7 BLAST # signal 8 Address decoder 9 CSDRAM signal 10 CISA signal 11 DRAM control circuit 12 DRAM 13 ISA bus Control circuit 14 ISA bus 15 RDY # signal 16 Clock signal 17 Clock generation circuit 18 DRAM address bus 19 DRAM Row Address Strob
e signal 20 DRAM Column Address St
probe signal 21 DRAM Write Enable signal 22 ISA bus address 23 ISA bus memory read signal 24 ISA bus memory write signal 25 ALE 26 SCLK

Claims (1)

[Claims] 1. An information processing apparatus including a CPU, a main storage device, and an expansion bus, wherein the main storage device can be arranged inside the information processing device and on the expansion bus, and the CPU is a main storage device. An information processing apparatus characterized in that when there is no main storage device to be accessed inside the information processing, the main storage device on the expansion bus is always accessed.