JP4772975B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a burst transfer mode in which a plurality of data is continuously transferred by one address designation.
[0002]
[Prior art]
When reading / writing data from / to the semiconductor memory device, it is necessary to specify an address to be accessed.
[0003]
By the way, in the semiconductor memory device having the burst transfer mode, when accessing consecutive addresses, it is possible to access all the addresses only by designating the head address.
[0004]
In a semiconductor memory device having such a burst transfer mode, there is a device that can set a burst length for writing data. FIG. 10 is a diagram for explaining the operation of such a semiconductor memory device. It is assumed that the physical maximum burst length of the target semiconductor memory device is “4”.
[0005]
A WR1 command (see FIG. 10B) requesting writing is input in synchronization with the 0th rising edge of the CLK (Clock) signal shown in FIG. 10A, and the burst length is designated. Suppose that VW = 1 (burst length = 1) (FIG. 10D) is input from the address input terminal as a VW (Variable Write) signal.
[0006]
Then, after the time corresponding to the latency (see FIG. 10C) has elapsed, the data D11 to D14 are read from the DATA input terminal. In this example, since the burst length is set to “1”, the data D11 is only in the internal data bus # 1 among the internal data buses # 1 to # 4 (FIGS. 10E to 10H). Will be sent out.
[0007]
The data D11 sent to the internal data bus # 1 is stored for a predetermined bit at a predetermined address.
When a time corresponding to the bank access interval (see FIG. 10B) has elapsed since the input of the WR1 command, the WR2 command is input in synchronization with the second rising edge, and after the time corresponding to the latency has elapsed, Data D21 to D24 are input and VW = 4 is input. As a result, D21 to D24 are sent to the internal data buses # 1 to # 4, respectively. The data D21 to D24 sent to the internal data buses # 1 to # 4 are stored for predetermined bits of successive addresses, respectively.
[0008]
When a time corresponding to the bank access interval elapses after the WR2 command is input, the WR3 command and VW = 2 are input. As a result, data D31 and data D32 are sent to the internal data buses # 1 and # 2, respectively.
[0009]
Data D21 and D22 sent to internal data buses # 1 and # 2 are respectively stored for predetermined bits of consecutive addresses.
[0010]
[Problems to be solved by the invention]
By the way, in the case of a semiconductor memory device having a plurality of DATA input terminals, there are many cases in which the DATA input terminal group is divided into an upper bit group and a lower bit group, and the burst length is set independently for each.
[0011]
In such a semiconductor memory device, there are cases where it is required to write only to either the upper or lower bit group. In such a case, the conventional semiconductor memory device has a problem that unnecessary data is written because there is no means for prohibiting data writing to any one of these bit groups.
[0012]
Also, in the case of a semiconductor memory device having latency for a write operation, when a write command is first input, data is not written to the cell but is held, and when the next write command is input Therefore, there are many cases having a function of writing data corresponding to the first write command to the cell.
[0013]
Incidentally, when performing an operation test as to whether or not the write operation of such a semiconductor memory device is normal, it is necessary to issue a write command twice in order to write data to the cell. In this case, in the case of the conventional semiconductor memory device, there is no means for prohibiting data writing as described above, and thus writing by the first writing command may interfere with writing by the next writing command. In order to eliminate such interference, there is a problem that the operation test becomes complicated.
[0014]
The present invention has been made in view of the above situation, and an object of the present invention is to provide a semiconductor memory device that enables data to be written to a cell in units of bit groups.
[0015]
[Means for Solving the Problems]
  According to one aspect of the invention, in a semiconductor memory device having a burst transfer mode in which a plurality of data is continuously input from outside and transferred to an internal cell area by one address designation from outside, Address input means for receiving an input of an address, data input means for receiving the input of the data from the outside, and the cells corresponding to a plurality of consecutive addresses starting from the address input via the address input means Burst transfer means for burst-transferring the data input via the data input means to a region, burst transfer length designation means for receiving designation of burst transfer length of the burst transfer means from the outside, and burst transfer If “0” is designated as the burst transfer length from the outside by the length designation means, the data Data input prohibiting means for prohibiting input of the data from the outside by a force means, and the data input means inputs the plurality of bits of data that can be input from the outside via a plurality of data input terminals. The burst transfer length designating means is divided into two by a predetermined bit group unit and inputted.In response to designation of the two burst transfer lengths in units of the predetermined bit group from the outside,There is provided a semiconductor memory device in which the burst transfer length of the data is set in units of the predetermined bit group, and the data input prohibiting unit prohibits the input of the data in units of the predetermined bit group.
[0016]
  According to one aspect of the invention, in a semiconductor memory device having a burst transfer mode in which a plurality of data is continuously input from outside and transferred to an internal cell area by one address designation from outside, Address input means for receiving the input of the address from, data input means for receiving the input of the data from the outside, and a plurality of consecutive addresses starting from the address input via the address input means Burst transfer means for burst-transferring the data input via the data input means to the area of the cell; burst transfer length specifying means for receiving designation of the burst transfer length of the burst transfer means from the outside; When "0" is designated as the burst transfer length from the outside by the burst transfer length designation means Transfer hold means for holding the transfer by the burst transfer means, and the data input means receives a plurality of bits of data that can be input at a time from the outside via a plurality of data input terminals. The burst transfer length designating means is divided into two bit groups and input.In response to designation of the two burst transfer lengths in units of the predetermined bit group from the outside,There is provided a semiconductor memory device in which the burst transfer length of the data is set in units of the predetermined bit group, and the transfer holding unit holds the transfer of the data in units of the predetermined bit group.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
  Hereinafter, embodiments of the present invention will be described with reference to the drawings.
  FIG. 1 is a principle diagram illustrating the operating principle of the present invention. As shown in this figure, the semiconductor memory device of the present invention comprises an address input means 1, data input means 2, burst transfer means 3, burst transfer length designation means 4, data input.BanIt is constituted by means 5 and cell 6.
[0020]
Here, the address input means 1 receives an input of a transfer destination address.
The data input means 2 receives input of data to be transferred. In this example, data # 1 corresponding to the upper bit group and data # 2 corresponding to the lower bit group are input.
[0021]
The burst transfer means 3 burst-transfers the data # 1 and # 2 input via the data input means 2 to the area of the cell 6 corresponding to the address input via the address input means 1.
[0022]
The burst transfer length designation unit 4 receives designation of the transfer length of the burst transfer unit 3. In this example, burst transfer length # 1 corresponding to data # 1 and burst transfer length # 2 corresponding to data # 2 are input.
[0023]
  Data entryBanThe means 5 inputs the data from the data input means 2 when the burst transfer length “0” is designated by the burst transfer length designation means 4.BanTo do.
[0024]
Next, the operation of the above principle diagram will be described.
The address indicating the transfer destination of the burst transfer is input to the address input means 1, the “4” bit is used as the burst transfer length # 1, and the “0” bit is used as the burst transfer length # 2. Is input.
[0025]
The burst transfer means 3 acquires the transfer destination address input via the address input means 1 and the burst transfer lengths # 1 and # 2 input via the burst transfer length designation means 4, and sets the internal circuit. I do.
[0026]
  Data entryBanThe means 5 refers to the burst transfer lengths # 1 and # 2 supplied from the burst transfer length specifying means 4 and the burst transfer length # 2 is set to “0”. Input for data # 2BanRequest to do.
[0027]
The data input means 2 inputs only the data # 1 and supplies it to the burst transfer means 3 when a predetermined time (time corresponding to the latency) has passed since the input of the address or the like.
[0028]
The burst transfer means 3 burst-transfers only the data # 1 supplied from the data input means 2 to a predetermined area of the cell 6 corresponding to the address supplied from the address input means 1.
[0029]
As a result, only the upper bit group of data is transferred to the cell 6. In this example, the case where only the upper bit group is transferred has been described as an example, but only the lower bit group can be transferred.
[0030]
As described above, according to the semiconductor memory device of the present invention, only the upper bit group or the lower bit group of data can be transferred to the cell.
In the above example, the upper bit group and the lower bit group are divided, but it is needless to say that other division methods may be employed.
[0031]
In the above example, data input is restricted according to the burst transfer length, but burst transfer may be restricted according to the burst transfer length.
Next, an embodiment of the present invention will be described.
[0032]
FIG. 2 is a diagram showing a configuration example of the semiconductor memory device of the present invention. As shown in this figure, the semiconductor memory device of the present invention includes a control unit 31, cells 32, a row decoder 33, a column decoder 34, an SA (Sense Amplifier) 35, and an I / O circuit 36.
[0033]
Here, the control unit 31 inputs a CLK (Clock) signal, a CMD (Command) signal, an ADD (Address) signal, a DS (Data Strobe) signal, and a DATA signal, and supplies them to each unit of the apparatus and writes them. In this case, DATA is read at a predetermined timing. When reading, DATA is read from a predetermined address and output.
[0034]
The cell 32 is composed of a group of storage elements arranged in a matrix and stores input data.
The row decoder 33 designates a predetermined row of the cell 32 based on the row address.
[0035]
The column decoder 34 designates a predetermined column of the cell 32 based on the column address.
The SA 35 amplifies the signal read from the cell 32 with a predetermined gain and converts it to a digital level.
[0036]
The I / O circuit 36 performs control related to data input / output.
FIG. 3 is a diagram illustrating a detailed configuration example of the control unit 31 illustrated in FIG. 2.
As shown in this figure, the control unit 31 includes a CLK input terminal 31a, a CMD input terminal 31b, an ADD input terminal 31c, a DS input terminal 31d, a DATA input terminal 31e, a CLK input circuit 31f, a CMD input circuit 31g, and an ADD input circuit. 31h, DS input activation determination circuit 31i, DS input circuit 31j, DATA input circuit 31k, CMD decoder 31m, and burst length determination circuit 31n. A portion surrounded by a broken line is provided for each of the upper bit group and the lower bit group.
[0037]
Here, the CLK input terminal 31a receives an input of the CLK signal. The CMD input terminal 31b receives an input of a CMD signal. The ADD input terminal 31c receives an ADD signal. The DS input terminal 31d receives a DS signal. The DATA input terminal 31e receives a DATA signal.
[0038]
The CLK input circuit 31f is configured by a buffer or the like, and supplies the CLK signal input from the CLK input terminal 31a to the CMD input circuit 31g, the ADD input circuit 31h, and the DS input activation determination circuit 31i.
[0039]
The CMD input circuit 31g acquires the CMD signal input from the CMD input terminal 31b in synchronization with the CLK signal, and supplies it to the CMD decoder 31m.
The ADD input circuit 31h acquires the ADD signal input from the ADD input terminal 31c in synchronization with the CLK signal, and supplies the ADD signal to the burst length determination circuit 31n.
[0040]
The DS input activation determination circuit 31i activates a DSE (Data Strobe Enable) signal according to the burst length (VW) determined by the burst length determination circuit 31n.
[0041]
When the DSE signal supplied from the DS input activation determination circuit 31i becomes active, the DS input circuit 31j inputs the DS signal from the DS input terminal 31d and supplies it to the DATA input circuit 31k.
[0042]
When the DS signal is supplied from the DS input circuit 31j, the DATA input circuit 31k inputs data from the DATA input terminal 31e and supplies it to the I / O circuit 36 shown in FIG.
[0043]
The CMD decoder 31m decodes the CMD signal input from the CMD input circuit 31g, and supplies it to the burst length determination circuit 31n when it is a command for setting a burst length (hereinafter referred to as a burst length setting command).
[0044]
When a burst length setting command is supplied from the CMD decoder 31m, the burst length determination circuit 31n determines the burst length with reference to the data supplied from the ADD input circuit 31h, and supplies it to the DS input activation determination circuit 31i. To do.
[0045]
Next, the operation of the above embodiment will be described. In the following, first, the basic operation of the present embodiment will be briefly described with reference to FIG. 4, and then the detailed operation will be described with reference to FIG.
[0046]
FIG. 4 is a diagram showing a state in which data is transferred from a DATA input terminal (corresponding to DATA input terminal 31e shown in FIG. 3) to a cell (corresponding to cell 32 shown in FIG. 2).
As shown in this figure, 8-bit data input to the DATA input terminals T1 to T8 is divided into an upper bit group and a lower bit group and stored as upper bit groups and lower bit groups of consecutive addresses ADD1 and ADD2. The
[0047]
Here, the maximum burst length is a physical maximum length and is determined by the configuration of the semiconductor memory device. The burst length (MRS: Mode Register Set) is a burst length set by an initial setting MRS command supplied when the apparatus is started up. The burst length (VW) is a burst length specified by the VW command when writing data, and has a length equal to or shorter than the burst length set by the MRS command.
[0048]
Note that FIG. 4 shows an example in which 8-bit data is input in order to simplify the drawing. However, in this embodiment, 16-bit data is input, and upper 8 bits and lower 8 bits are input. It is divided into.
[0049]
Next, detailed operation of the present embodiment will be described.
When the semiconductor memory device shown in FIG. 2 is activated, a control device (not shown) supplies a command for setting the burst length to “4” to the CMD input terminal 31b.
[0050]
The CMD decoder 31m acquires a burst length setting command via the CMD input circuit 31g, and detects that a burst length setting is requested.
Subsequently, the control device supplies data indicating “4”, which is the burst length to be set, to the ADD input terminal 31c.
[0051]
The burst length determination circuit 31n acquires this data via the ADD input circuit 31h, determines that the burst length is “4”, and determines that BL = 4 is the DS input activation determination circuit 31i and the DATA input. This is notified to the circuit 31k. The CMD decoder 31m sets the I / O circuit 36 so that the burst length becomes “4”.
[0052]
With the above operation, setting of the burst length (burst length (MRS) shown in FIG. 4) is completed.
Next, a data write operation when the burst length is set to “4” by MRS will be described with reference to FIG.
[0053]
At the 0th rising edge of the CLK signal shown in FIG. 5A, the WR1 command (see FIG. 5B) is input to the CMD input terminal 31b, and VWU = 1 (see FIG. 5D) to the ADD input terminal 31c. ) And VWL = 1 (see FIG. 5I) are input. Here, VWU (Variable Write Upper) is a command for setting a burst length of upper 8 bits, and VWL (Variable Write Lower) is a command for setting a burst length of lower 8 bits.
[0054]
The CMD input circuit 31g supplies the CMD input from the CMD input terminal 31b to the CMD decoder 31m.
The CMD decoder 31m decodes the CMD, detects that data writing is requested, and notifies the burst length determination circuit 31n to that effect.
[0055]
By the way, as described above, a portion surrounded by a broken line is provided for each of the upper bit group and the lower bit group, and a circuit corresponding to the upper 8 bits (hereinafter referred to as “upper bit circuit”). A request for writing and VWU are supplied from the CMD decoder 31m, and a request for writing and VWL are supplied from the CMD decoder 31m to a circuit corresponding to the lower 8 bits (hereinafter referred to as “lower bit circuit”). Is done.
[0056]
In the following description, the upper bit circuit and the lower bit circuit will be described separately.
(1) Operation of upper bit circuit
The burst length determination circuit 31n of the upper bit circuit recognizes that data writing is requested by a request from the CMD decoder 31m, and also sets the burst length (to be set by the VWU acquired through the ADD input circuit 31h). = 1) and notifies the DS input activation determination circuit 31i and the DATA input circuit 31k.
[0057]
The DS input activation determination circuit 31i sets a DSE (Data Strobe Enable) signal to an “H” state when a predetermined time (time corresponding to the write latency) has elapsed since the writing was requested. As a result, the DS input circuit 31j receives an input of the DS signal from the DS input terminal 31d and supplies the input DS signal to the DATA input circuit 31k.
[0058]
When the DS signal is supplied, the DATA input circuit 31k starts to input the upper 8 bits of DATA from the DATA input terminal 31e as shown in FIG.
Since VWU = 1 is set now, the DATA input circuit 31k receives only the upper 8 bits of the data D11 out of the input data D11 to D14 via the internal data bus # U1. (See FIGS. 5E to 5H).
(2) Operation of lower bit circuit
On the other hand, the burst length determination circuit 31n of the lower bit circuit recognizes that data write is requested by a request from the CMD decoder 31m, and also sets a burst to be set by the VWL acquired via the ADD input circuit 31h. Recognize the length (= 1) and notify the DS input activation determination circuit 31i and the DATA input circuit 31k.
[0059]
The DS input activation determination circuit 31i sets the DSE signal to the “H” state when a predetermined time (time corresponding to the write latency) elapses after the write is requested. As a result, the DS input circuit 31j receives an input of the DS signal from the DS input terminal 31d and supplies the DS signal input to the DATA input circuit 31k.
[0060]
When the DS signal is supplied, the DATA input circuit 31k starts to input the lower 8 bits of DATA from the DATA input terminal 31e as shown in FIG.
Now, since VWL = 1 is set, the DATA input circuit 31k of the lower bit circuit receives only the lower 8 bits of the data D11 from the input data D11 to D14 via the internal data bus # L1. The data is transferred to the / O circuit 36 (see FIGS. 5J to 5M).
[0061]
The above is the operation of the upper bit circuit and the lower bit circuit corresponding to WR1.
Subsequently, when the WR2 command is input at the second rising edge of the CLK signal shown in FIG. 5A and VWU = 4 and VWL = 4 are input, the same operation as described above is executed. Data D21 to D24 are read at the rising edge of the third CLK signal.
[0062]
Since VWU = 4, the DATA input circuit 31k of the upper bit circuit transfers the upper 8 bits of the data D21 to D24 to the I / O circuit 36 via the internal data buses # U1 to # U4 (FIG. 5 (E) to (H)).
[0063]
Since VWL = 4, the DATA input circuit 31k of the lower bit circuit transfers the lower 8 bits of the data D21 to D24 to the I / O circuit 36 via the internal data buses # L1 to # L4 (FIG. 5). (See (J) to (M)).
[0064]
Subsequently, when the WR3 command is input at the third rising edge of the CLK signal shown in FIG. 5A and VWU = 2 and VWL = 0 are input, the same operation as described above is executed. Data D31 to D34 are read at the rising edge of the fifth CLK signal.
[0065]
Here, since VWU = 2, the DATA input circuit 31k of the upper bit circuit transfers the upper 8 bits of the data D31 and D32 to the I / O circuit 36 via the internal data buses # U1 and # U2 (FIG. 5 (E) to (H)).
[0066]
In the lower bit circuit, since VWL = 0, the DATA input circuit 31k does not transfer data to the I / O circuit 36 (see FIGS. 5J to 5M). As a result, the lower byte is not written to the cell 32.
[0067]
Thus, by setting VWU or VWL to “0”, it becomes possible to suspend writing of the upper byte or the lower byte.
In the above example, writing of data to the lower byte is suspended, but writing of data to the upper byte can be suspended. In that case, if WVU = 0 is input, writing to the upper byte is suspended by the same operation as described above.
[0068]
By the way, the address for designating VW is not provided exclusively for it, but it is normal to use a free address. For example, when the row address and the column address are fetched in two steps, the column address usually has a smaller number of bits, so some of the address terminals prepared for the row address fetch the column address. In time it is vacant. For example, VW can be allocated to the vacant address as shown in the following figure.
[0069]
FIG. 6 is a diagram illustrating an example of assignment of VWs to column addresses when the burst length is “2” (BL = 2). In the example of this figure, VWU and VWL for upper byte and lower byte are respectively assigned to A0 to A3. Specifically, when A0 and A1 are “0” and “0”, VWU = 0, and when A0 and A1 are “1” and “0”, VWU = 1, and A0 When A1 is “0” or “1”, VWU = 2 is assigned. The same assignment is made for the lower byte.
[0070]
FIG. 7 is a diagram illustrating an example of assignment of VWs to column addresses when the burst length is “4” (BL = 4). In the example of this figure, VWU and VWL for upper byte and lower byte are respectively assigned to A0 to A3. Specifically, when A0 and A1 are “0” and “0”, VWU = 0, and when A0 and A1 are “1” and “0”, VWU = 1, and A0 When A1 and A1 are “0” and “1”, VWU = 2, and when A0 and A1 are “1” and “1”, VWU = 4 is assigned. The same assignment is made for the lower byte.
[0071]
FIG. 8 is a diagram illustrating an example of assignment of VWs to column addresses when the burst length is “8” (BL = 8). In the example of this figure, VWU and VWL for upper bytes and lower bytes are assigned to A0 to A5, respectively. Specifically, when A0 to A2 are “0”, “0”, “0”, VWU = 0, and when A0 to A2 are “1”, “0”, “0”. VWU = 1, and when A0 to A2 are “0”, “1”, “0”, VWU = 2, and A0 to A2 are “1”, “1”, “0”. In this case, VWU = 4, and when A0 to A2 are “0”, “0”, “1”, VWU = 8 is assigned. The lower byte is assigned in the same way.
[0072]
FIG. 9 is a diagram illustrating an example of assignment of VWs to column addresses when the burst length is “16” (BL = 16). In the example of this figure, VWU and VWL for upper bytes and lower bytes are assigned to A0 to A5, respectively. Specifically, when A0 to A2 are “0”, “0”, “0”, VWU = 0, and when A0 to A2 are “1”, “0”, “0”. VWU = 1, and when A0 to A2 are “0”, “1”, “0”, VWU = 2, and A0 to A2 are “1”, “1”, “0”. In this case, VWU = 4, and when A0 to A2 are “0”, “0”, “1”, VWU = 8, and A0 to A2 are “1”, “0”, “1”. In this case, VWU = 16 is assigned. The lower byte is assigned in the same way.
[0073]
As described above, according to the present embodiment, the burst length can be set to “0” by the VW, so that the transfer of the upper byte or the lower byte can be suspended. Accordingly, either the upper byte or the lower byte can be written to the cell 32.
[0074]
In addition, according to the present embodiment, writing to both the upper byte and the lower byte can be suspended by the VW. Such a transfer mode is considered to be effective, for example, in an operation test of a semiconductor memory device having a write latency.
[0075]
That is, in the case of a semiconductor memory device having a write latency, when a write command for a certain address is given, only write data input delayed in that cycle is executed, and the actual write to the cell 32 is the next write. Runs when a command is entered.
[0076]
Therefore, when performing an operation test of such a semiconductor memory device, it is necessary to input a write command for a certain address and then input a dummy write command to complete the write operation for the previous data. In this case, it is assumed that dummy data affects the previous data. Therefore, if dummy writing is executed with VWU = VWL = 0, data transfer to the cell 32 is not performed. Such an inconvenience can be avoided without being executed.
[0077]
In the above embodiment, when VWU or VWL is “0”, the data transfer to the cell 32 is suspended. However, as in the principle diagram shown in FIG. 1, the data input from the DATA input terminal 31e is suspended. Even if the data import is prohibited, the same effect as described above can be obtained.
[0078]
Furthermore, in the above embodiment, the upper bit group and the lower bit group are divided and VW is provided for each bit group. However, for example, other division methods may be employed. Needless to say.
[0079]
Furthermore, the configuration examples shown in FIG. 2 and FIG. 3 are only examples, and it goes without saying that the present invention is not limited to such a case.
[0080]
【The invention's effect】
  According to the disclosed semiconductor memory device, interference between write data can be prevented. In addition, a part of data can be written.
[Brief description of the drawings]
FIG. 1 is a principle diagram illustrating an operation principle of the present invention.
FIG. 2 is a diagram illustrating a configuration example of an embodiment of the present invention.
FIG. 3 is a diagram illustrating a detailed configuration example of a control unit illustrated in FIG. 2;
FIG. 4 is a diagram illustrating a correspondence relationship between data input from a DATA input terminal and data stored in a cell according to the present invention.
FIG. 5 is a diagram for explaining the operation of the embodiment of the present invention.
FIG. 6 is a diagram illustrating an example of a method of assigning VWU and VWL to column addresses when the burst length is “2”.
FIG. 7 is a diagram illustrating an example of a method of assigning VWU and VWL to column addresses when the burst length is “4”.
FIG. 8 is a diagram illustrating an example of a method of assigning VWU and VWL to a column address when the burst length is “8”.
FIG. 9 is a diagram illustrating an example of a method for assigning VWU and VWL to column addresses when the burst length is “16”.
FIG. 10 is a diagram for explaining the operation of a conventional semiconductor memory device capable of setting a burst length when writing data.
[Explanation of symbols]
  1 Address input means
  2 Data input means
  3 Burst transfer means
  4 Burst transfer length designation means
  5 Data inputBanmeans
  6 cells
  31 Control unit
  31a CLK input terminal
  31b CMD input terminal
  31c ADD input terminal
  31d DS input terminal
  31e DATA input terminal
  31f CLK input circuit
  31g CMD input circuit
  31h ADD input circuit
  31i DS input activation determination circuit
  31j DS input circuit
  31k DATA input circuit
  31m CMD decoder
  31n burst length judgment circuit
  32 cells
  33 line decoder
  34 column decoder
  35 SA
  36 I / O circuit

Claims (4)

In a semiconductor memory device having a burst transfer mode in which a plurality of data is continuously input from the outside by one address designation from the outside and transferred to an internal cell area.
An address input means for receiving the input of the address from the outside;
Data input means for receiving the data input from the outside;
Burst transfer for burst-transferring the data input via the data input means to the area of the cell corresponding to a plurality of consecutive addresses starting from the address input via the address input means Means,
Burst transfer length designation means for receiving designation of burst transfer length of the burst transfer means from outside;
Data input prohibiting means for prohibiting external input of the data by the data input means when the burst transfer length specifying means specifies "0" as the burst transfer length from the outside. ,
The data input means inputs a plurality of bits of data that can be input at one time from the outside through a plurality of data input terminals divided into two in units of a predetermined bit group,
The burst transfer length designation means receives the designation of the two burst transfer lengths in the predetermined bit group unit from the outside, and sets the burst transfer length of the data in the predetermined bit group unit,
The data input prohibiting means prohibits input of the data in units of the predetermined bit group.   2. The data input unit according to claim 1, wherein the data input unit starts inputting the data after a predetermined time has elapsed since the burst transfer length was designated from the outside by the burst transfer length designating unit. Semiconductor memory device. In a semiconductor memory device having a burst transfer mode in which a plurality of data is continuously input from the outside by one address designation from the outside and transferred to an internal cell area.
  An address input means for receiving the input of the address from the outside;
  Data input means for receiving the data input from the outside;
  Burst that burst-transfers the data input via the data input means to the area of the cell specified by a plurality of consecutive addresses starting from the address input via the address input means Transfer means;
  Burst transfer length designation means for receiving designation of burst transfer length of the burst transfer means from outside;
  When the burst transfer length specifying means designates “0” as the burst transfer length from the outside, transfer holding means for holding transfer by the burst transfer means, and
  The data input means inputs a plurality of bits of data that can be input at one time from the outside through a plurality of data input terminals divided into two in units of a predetermined bit group,
  The burst transfer length designation means receives the designation of the two burst transfer lengths in the predetermined bit group unit from the outside, and sets the burst transfer length of the data in the predetermined bit group unit,
  The transfer holding means holds the transfer of the data in units of the predetermined bit group. 4. The data input unit according to claim 3, wherein the data input unit starts inputting the data after a predetermined time has elapsed since the burst transfer length was designated from the outside by the burst transfer length designating unit. Semiconductor memory device.

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