JP3563340B2 - Memory controller - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a memory controller, and more particularly to a memory controller that generates a memory access cycle with a minimum number of waits for a single address DMA transfer when an asynchronous memory and a synchronous memory are respectively connected to an external memory.
[0002]
[Prior art]
2. Description of the Related Art In recent years, with the advancement of the miniaturization technology of semiconductor devices, LSIs composed of the semiconductor devices have been increasing in scale, and this tendency is particularly remarkable in the field of semiconductor memories.
[0003]
For example, a dynamic random access memory (DRAM) and a synchronous dynamic random access memory (SDRAM) have been put into practical use as semiconductor memories having a capacity of 256 megabits per chip.
[0004]
The operating speed of a single-chip microcomputer connecting these semiconductor memories as an external memory has been remarkably improved, which is why the connected external memory is expected to increase in operating speed as well as in capacity.
[0005]
When an external memory is connected, direct memory access (hereinafter, referred to as DMA) for transferring data between the memory and the I / O device without going through a central processing unit (hereinafter, referred to as CPU) of a single-chip microcomputer. ) Has been done.
[0006]
In the single address DMA transfer, when data is transferred from an external memory to an I / O device, a read strobe signal is supplied to the memory, and a write strobe signal is supplied to the I / O device. Read data read from the memory is output. The data read on the data bus is written to the I / O device.
[0007]
On the other hand, when data is transferred from the I / O device to the external memory, a read strobe signal is supplied to the memory, and a write strobe signal is supplied to the I / O device. Write the read data to the external memory.
[0008]
An example of this type of conventional weight control is described in Japanese Patent Application Laid-Open No. Hei 4-251056. The weight signal control unit described in the publication includes a connection terminal 2A between the CPU and the DMA controller, a weight signal output terminal 2B, a weight setting register 21, a device decoder 22, and a weight signal generation unit 23.
[0009]
In the wait setting register 21, the number of waits corresponding to the access speed of the I / O device is set in advance by the CPU.
[0010]
The device decoder 22 detects an I / O device in the current DMA operation, and derives the number of waits corresponding to the device from the register 21.
[0011]
The derived weight number is input to weight signal generating section 23, and a weight signal corresponding to the weight number is generated.
[0012]
This weight control unit sets the number of waits to be inserted in the DMA of each device by a program in advance, so that an appropriate number of waits can be set for each device regardless of the access speed, and the DMA rate is not deteriorated. is there.
[0013]
As will be described later in the present invention, a memory controller that controls this kind of single address DMA transfer secures a data transfer rate by accessing with a minimum number of waits especially from a CPU that can access at high speed. Also, with respect to single address DMA transfer from a high-speed memory to a low-speed memory, a configuration in which the number of waits corresponding to the data access time of the low-speed memory is to be inserted into the operation cycle of the high-speed memory is disclosed.
[0014]
In general, access to the SDRAM takes advantage of the characteristics of the SDRAM, so that access from the CPU is usually performed with no-wait high-speed access.
[0015]
Therefore, normally, the memory controller does not have a data wait function. However, in the application field of a single-chip microcomputer, even in a single address DMA transfer from an SDRAM to a low-speed device, the memory controller does not transfer to a low-speed device as a transfer destination. It is required that high-speed transfer can be performed.
[0016]
[Problems to be solved by the invention]
As described above, in the memory controller mounted on the conventional general single-chip microcomputer, the wait control specialized for the DMA transfer is not performed. As an example of improving the drawback, there is an example of the above-mentioned Japanese Patent Application Laid-Open No. 4-251056, but in any case, data wait is not considered for SDRAM access. In other words, data that is normally output only for one clock period is extended to output two to several clock periods, so that a data wait for avoiding a malfunction in writing to the I / O device is reduced. I have not gone.
[0017]
Therefore, when one of the DMA transfer targets is the SDRAM, the specifications of the low-speed device at the transfer destination cannot be satisfied, and in many cases, the single address mode DMA transfer cannot be realized.
[0018]
That is, in a general microcomputer, the data wait is not considered at the time of accessing the SDRAM. Therefore, the access to the SDRAM is always performed at a 1CLK pitch. That is, during the data output period, only 1 CLK is output for both read / write.
[0019]
Therefore, for example, when the data output delay value of the SDRAM is 5 ns in a product having a bus operating frequency of 100 MHz, data cannot be prepared during the valid period of the write strobe signal to the I / O device, and the data cannot be transferred.
[0020]
That is, in the case of the 1 CLK pitch, the write strobe signal to the I / O device is toggled at a half clock.
[0021]
Further, even when a system in which writing to the I / O device is performed in synchronization with the rising edge of the clock supplied to the SDRAM, if the data output delay of the SDRAM is 5 ns, the data setup time for writing to the I / O device is reduced. Must be within 5 ns, and it is difficult to realize the setup time of 5 ns with a low-speed I / O device. As a result, a single address transfer between the SDRAM and the I / O cannot be performed.
[0022]
SUMMARY OF THE INVENTION An object of the present invention is to provide a single address mode DMA transfer adapted to the specifications of a low-speed memory to be transferred without reducing the transfer rate in CPU access. is there.
[0023]
[Means for Solving the Problems]
A feature of the memory controller of the present invention is that when performing data transfer between a CPU and a synchronous memory, a first operation cycle based on a wait when accessing the synchronous memory is generated, and the CPU and the asynchronous memory are generated. When performing a data transfer between the synchronous memory and the asynchronous memory, a second operation cycle is generated based on the wait when accessing the asynchronous memory. When performing a single address DMA transfer between the synchronous memory and the asynchronous memory, A memory access control signal generating circuit for generating a third operation cycle based on a wait at the time of the single address DMA transfer and supplying the same to the synchronous memory is provided.
[0024]
Another feature of the memory controller according to the present invention is that a memory controller corresponding to an I / O device to which a peripheral device is connected, including an asynchronous memory for low-speed operation, and a synchronous memory for high-speed operation, which are DMA transfer targets. Weight setting means for setting the number of waits when accessing the synchronous and asynchronous external memories from the CPU in advance; and A DMA transfer wait setting register in which the number of waits at the time of single address DMA transfer to a memory is set in advance by the CPU, and a wait address register and a DMA transfer wait setting register in response to a single address DMA transfer request and a memory access request. Have either one A weight selection means for selectively outputting the Eito number is to the memory access control signal generating means generates and outputs a memory access cycle of inserting the number of weights selected by the weight selection unit.
[0025]
Further, the memory access control signal generating means includes a predetermined control signal output means including an address signal for accessing the synchronous memory for high-speed operation and a clock enable signal, and the asynchronous memory for low-speed operation. In addition to predetermined control signal output means including an address signal to be accessed, a write strobe signal, and a read signal, the asynchronous memory control signal generation means, the I / O device, and the synchronous memory control It may further comprise a bidirectional data bus means for commonly connecting the signal generation means and the synchronous memory.
[0026]
Further, when the synchronous memory to be DMA-transferred is a synchronous dynamic random access memory (SDRAM), the clock enable signal for the SDRAM is set to an inactive level, and the transfer speed of the I / O device is changed. The SDRAM access can be executed in accordance with the above.
[0027]
Furthermore, the memory access control signal generating means, when accessing the synchronous memory and the I / O device and performing bidirectional DMA transfer, uses the number of waits selected from the plurality of wait setting register means. A DMA access control can be performed by generating a memory access cycle.
[0028]
Further, at the time of the single address DMA transfer, a single address DMA transfer cycle can be generated by selecting the number of waits in the DMA transfer wait setting register based on the DMA transfer request.
[0029]
Further, at the time of the single address DMA transfer, it is possible to execute a memory access according to a slower operation speed of the synchronous memory and the I / O device to be DMA-transferred.
[0030]
Furthermore, the asynchronous memory signal generating means may generate a write strobe signal for DMA single address transfer, and perform a single address DMA transfer during a read cycle of the synchronous memory by using the write strobe signal.
[0031]
Still another feature of the memory controller of the present invention is that a memory controller waits for an I / O device to which a peripheral device is connected, including an asynchronous memory for low-speed operation, and a synchronous memory for high-speed operation, which are DMA transfer targets. Weight setting register means for setting the number of waits for accessing the synchronous system and the I / O device from the CPU in advance; and number of waits for the weight setting register in response to a single address DMA transfer request and a memory access request. And a memory access control signal generating means for generating and outputting a memory access cycle in which the number of waits is inserted.
[0032]
The memory access control signal generating means comprises an asynchronous memory signal generating means and a synchronous memory signal generating means, wherein the asynchronous memory signal generating means accesses an address signal for accessing the I / O device. And a predetermined control signal supply unit including a write strobe signal. When the asynchronous memory is accessed, either an address access from the CPU or an access by the write strobe signal can be executed.
[0033]
Further, the synchronous memory can be directly accessed by the CPU without any wait without the intervention of the wait setting register.
[0034]
Furthermore, during DMA transfer between the synchronous memory and the I / O device including peripheral devices including the asynchronous memory, a single address DMA transfer cycle is generated based on the number of waits of the wait setting register means. You can also.
[0035]
Another feature of the memory controller of the present invention is that the memory controller wait control means for an I / O device including peripheral devices including a low-speed operation asynchronous memory and a high-speed operation synchronous memory to be DMA-transferred. Memory access control signal generating means for generating and outputting a memory access cycle into which a predetermined number of waits are inserted, wherein the memory access control signal generating means comprises a signal generating means for an asynchronous memory and a signal generating means for a synchronous memory. Wherein the asynchronous memory signal generation means includes a predetermined control signal supply means including an address signal for accessing the asynchronous memory and a write strobe signal, and the synchronous memory signal generation means. Means for receiving a wait signal from the I / O device And a predetermined control signal output means including an address signal for accessing the synchronous memory and a clock enable signal, and a wait based on the clock enable signal whose activation and deactivation is controlled according to the wait signal is inserted. In the memory cycle of the transferred single address DMA transfer.
[0038]
BEST MODE FOR CARRYING OUT THE INVENTION
First, an outline of the present invention will be described. As shown in FIG. 1, a memory controller according to the present invention accesses data from a CPU (not shown) capable of high-speed access by using a minimum number of waits. Secure transfer rate. In addition, in single address DMA transfer from a high-speed memory to a low-speed memory, a technique is disclosed in which the number of waits corresponding to the data access time of the low-speed memory is inserted into the operation cycle of the high-speed memory to secure the data transfer rate. Is what you do.
[0039]
Next, referring to FIG. 1 showing a block diagram of a first embodiment of the memory controller according to the present invention, the memory controller comprises a wait setting register 11, a DMA transfer wait setting register 12, a selector 13, a memory access control signal. Generator 14, signal generator 15 for asynchronous memory, signal generator 16 for SDRAM, I / O device (synchronous memory for low-speed operation, I / O) 17 and SDRAM (synchronous memory for high-speed operation) 18 Is provided.
[0040]
That is, an I / O device of an external memory is used as a memory controller wait control unit for the I / O device 17 to which a low-speed operation asynchronous memory or the like to be DMA-transferred is connected and the high-speed operation synchronous memory SDRAM 18. 17, a wait setting register 11 in which the number of waits for accessing the SDRAM 18 is set in advance by the CPU, and a single signal from the SDRAM 18 for high-speed operation to the I / O device 17 for low-speed operation among the I / O devices 17 and SDRAM 18. The number of waits at the time of the address DMA transfer has a DMA transfer wait setting register 12 which is set in advance by the CPU.
[0041]
Further, there is also provided a selector (weight selection means) 13 for selectively outputting the number of waits of one of the wait setting register 11 and the DMA transfer wait setting register 12 according to the single address DMA transfer request DMA_ERQ and the memory access request M_REQ.
[0042]
Further, it is provided with a memory access control signal generating circuit (memory access control signal generating means) 14 for generating and outputting a memory access cycle in which the number of waits selected by the selector 13 is inserted.
[0043]
The wait setting register 11 for CPU access and the wait setting register 12 for DMA transfer are programmable registers.
[0044]
The selector 13 selects which of the two wait setting registers 11 and 12 to use, based on the two input signals, that is, the memory access request signal M_REQ and the DMA transfer request DMA_REQ.
[0045]
The memory access control signal generation circuit 14 generates a memory access cycle in which the number of waits selected by the selector 13 is inserted.
[0046]
In this example, the memory access control signal generation circuit 14 includes an asynchronous memory signal generation circuit 15 for generating an access signal for an asynchronous memory (SRAM, I / O, etc.).
[0047]
The asynchronous memory signal generating circuit 15 also has an output unit for outputting a write strobe signal DMA_WE for DMA single transfer to an I / O device, and activates the write strobe signal DMA_WE during a read cycle of the SDRAM. By doing so, single address DMA transfer can be performed.
[0048]
As other signals, an address ADR, a chip select signal CS, a read signal RD, and a write signal WR are supplied to the I / O device side.
[0049]
Further, an SDRAM signal generation circuit 16 for generating an SDRAM access signal is provided inside the memory access control signal generation circuit 14.
[0050]
The SDRAM signal generation circuit 16 outputs ADR, CLK, RAS, CAS, WE, CKE, and DQM clocks and control signals to the SDRAM 18.
[0051]
Here, the signal CLK is an operation clock of the SDRAM 18, the address ADR is an address for the SDRAM 18, and the signal RAS is a row address strobe signal for the SDRAM 18.
[0052]
Signal CAS is a column address strobe signal for SDRAM 18, signal WE is a write enable signal for SDRAM 18, and signal CKE is a clock enable for SDRAM 18.
[0053]
Signal DQM is a data mask signal for SDRAM 18 and signal DMA_WE is a write strobe signal for I / O device 17.
[0054]
Further, a bidirectional data bus D for commonly connecting the asynchronous memory signal generation circuit 15 and the I / O device and the SDRAM signal generation circuit 16 and the I / O device is provided.
[0055]
Hereinafter, the operation of the present embodiment will be described with reference to FIG. 1 and a timing chart for explaining the operation, with reference to FIG. 2 showing the timing of a single address DMA transfer from the SDRAM to the I / O device.
[0056]
First, in FIG. 2, it is assumed that the access to the SDRAM 18 starts with the CAS latency being 2, the burst length being 4, and the bank / page being hit. It is also assumed that the wait number 1 is set in the DMA transfer weight setting register 12.
[0057]
The latency here indicates the time from when a data read instruction of a memory cell is issued to when data is read and output to the outside. Therefore, the latency from when the CAS signal is validated to when data is actually output is defined as CAS latency.
[0058]
For example, a row address is specified, the RAS signal is validated, and a word line corresponding to the given row address is activated. A desired memory cell is selected by designating a column address, enabling the CAS signal, and selecting a digit line corresponding to the given column address.
[0059]
The burst length is the number of words output or input in a read cycle or a write cycle.
[0060]
In the T1 state, to the SDRAM 18, the address ADR is supplied with ADm, the CAS signal is activated at a low level only during the T1 state, the RAS signal is supplied at a high level, the data mask signal DQM is at a low level, and the I / O device 17 Is a state in which the write strobe signal DMA_WE is given at a high level.
[0061]
First, upon receiving the DMA transfer request DMA_REQ, the memory controller issues a read command to the SDRAM 18 in the T1 state.
[0062]
Here, since the number of waits 1 is set in the DMA transfer wait setting register 12, the clock enable signal CKE is disabled in the T2 state in order to apply a wait to the data output from the SDRAM 18 according to the present invention.
[0063]
Due to this disabling, the data D normally output only in the T3 state is extended by 1 CLK, and the write time of the low-speed device is secured to the T4 state.
[0064]
In addition, the asynchronous memory signal generation circuit 15 makes DMA_WE low active from the T3 state to the T4 state in order to capture the data D output from the SDRAM 18, and captures the data.
[0065]
From the T5 state to the T10 state, the above operation is repeated.
[0066]
In the case of the conventional memory controller, when the transfer destination I / O device cannot realize single address transfer at a 1CLK pitch at a low speed, DMA transfer must be performed by dual address transfer.
[0067]
For example, when 2 CLK is required for writing to an I / O device, 15 CLK is required for transferring 4 words from the SDRAM. However, using the configuration of the present invention, 4-word transfer can be realized with 10 CLKs from the T1 state to the T10 state, and one transfer can be reduced to 2/3.
[0068]
Further, since the access to the SDRAM 18 from the CPU can be performed at a high speed as before, the transfer rate with respect to the CPU does not decrease.
[0069]
Next, a second embodiment will be described.
[0070]
In the second embodiment, the basic configuration is the same as that of the above-described first embodiment, but the configuration of the weight setting register 11 is further devised.
[0071]
Referring to FIG. 3 which shows a block diagram of the configuration, the difference from the first embodiment is that the wait setting register 12 for DMA transfer is deleted and only the wait setting register 11 for performing the wait setting from the CPU is provided. It is valid.
[0072]
An address ADR, a chip select signal CS, a read signal RD, a write signal WR, a write strobe signal DMA_WE, and a data bus D are provided from the asynchronous memory signal generation circuit 15 to the I / O device 17 in the same manner as in the first embodiment. ing.
[0073]
The signals between the SDRAM signal generation circuit 16 and the SDRAM 18 are the same as in the first embodiment.
[0074]
In other words, the I / O device 17 is configured to be capable of address access from the CPU, and is further characterized in that it can be accessed by the write strobe signal DMA_WE.
[0075]
When performing an address access to the I / O device from the CPU, the number of waits in the wait setting register 11 is employed, and the asynchronous memory signal generation circuit 15 generates a memory cycle according to the number of waits.
[0076]
In addition, since the CPU can access the SDRAM 18 at high speed with respect to the address cycle, the access is performed with no wait, and no wait setting register is provided.
[0077]
On the other hand, during single address DMA transfer between the SDRAM 18 and the I / O device, there is a wait setting register 11 in which the number of waits corresponding to the specifications of the I / O device 17 is set. Generate an address DMA transfer cycle.
[0078]
As described above, in the present embodiment, the DMA transfer satisfying the specifications of the I / O and the asynchronous low-speed memory connected as the I / O device is performed without providing the wait setting register 12 for the DMA transfer. Therefore, the circuit scale can be further reduced as compared with the first embodiment.
[0079]
Next, a third embodiment will be described.
[0080]
In the first and second embodiments described above, the wait insertion in the single address DMA transfer is performed in the wait setting register 11, the DMA transfer wait setting register 12, or the wait setting register 11.
[0081]
However, referring to the block diagram of the third embodiment shown in FIG. 4, the difference from the first embodiment is that any one of the wait setting registers 11 and 12 The difference is that neither is provided.
[0082]
On the other hand, the difference from the second embodiment is that the weight setting register 11 is also deleted. Further, a common difference from the first and second embodiments is that the memory controller is given a wait by giving a wait signal WAIT from the I / O device 17 to the SDRA signal generation circuit 16.
[0083]
First, a CLK signal and a CKE signal are input to the I / O device. The logic of the I / O device is such that the WAIT signal is always active while the CKE signal is active.
[0084]
The SDRAM signal generation circuit 6 sets the first CKE signal to the disable level by ANDing the DMA transfer request, the WAIT signal, and the inverted signal of the CAS signal.
[0085]
When the CKE signal goes to the disable level, the I / O device counts the number of clocks to be waited and sets the WAIT signal to the disable level.
[0086]
Since the WAIT signal is at the disable level, the SDRAM signal generation circuit 6 activates the CKE signal.
[0087]
In response to the activation of the CKE signal, the I / O device activates the WAIT signal again.
[0088]
The SDRAM signal generation circuit 6 disables CKE by ANDing the DMA transfer request and the WAIT signal.
[0089]
The above is repeated while the DMA transfer request continues to be issued.
[0090]
Referring to FIG. 5 showing a timing chart of the single address DMA transfer in the case of using this embodiment, also in this embodiment, in the T1 state, the address ADR is supplied to the SDRAM 18 with ADm, and the CAS signal becomes T1. It is activated to low level only during the state period.
[0091]
The RAS signal is given a high level, the write enable signal WE is given a high level, the clock enable signal CKE is given a high level, and the data mask signal DQM is given a low level.
[0092]
The write strobe signal DMA_WE is supplied to the I / O device 17 at a high level, and the wait signal WAIT is supplied from the I / O device 17 to the SDRAM signal generation circuit 16 at a high level.
[0093]
First, upon receiving the DMA transfer request DMA_REQ, the memory controller issues a read command to the SDRAM 18 in the T1 state. Since the wait signal WAIT is active at the high level for one clock period between the T1 state and the T2 state, the SDRAM signal generation circuit 16 changes the clock enable signal CKE to the low level in the T2 state in response to the activation of the WAIT signal. Disable
[0094]
Therefore, data output from SDRAM 18 can be weighted.
[0095]
As described above, by disabling the clock enable signal CKE, the data D which is normally output only in the T3 state is extended by 1 CLK, and the write time of the low-speed device is secured up to the T4 state.
[0096]
In addition, the asynchronous memory signal generation circuit 15 can make DMA_WE low active from the T3 state to the T4 state to take in the data D output from the SDRAM 18, and can take in the data. The above operation is repeated from the T5 state to the T10 state.
[0097]
As described above, also in this embodiment, by weighting the memory controller with the wait signal WAIT, the same effect as in the first and second embodiments, that is, the transfer of four words from the T1 state to the T10 state is achieved. And one transfer can be reduced to 2/3.
[0098]
Further, since the access to the SDRAM 18 from the CPU can be performed at a high speed as before, the transfer rate with respect to the CPU does not decrease. Further, since neither the wait setting register 11 nor the DMA transfer wait setting register 12 is provided, the number of registers can be reduced and the circuit scale can be reduced.
[0099]
Next, a fourth embodiment will be described.
[0100]
Referring to FIG. 6 showing a block diagram of the configuration of the fourth embodiment of the present invention, the difference from the first embodiment is that the SDRAM signal generation circuit 16 is deleted from the memory access control signal generation circuit 14. In the above-described embodiment, the SDRAM 18 is connected as the synchronous external memory, but the asynchronous SRAM 19 is provided here.
[0101]
Since the SDRAM signal generation circuit 16 has been deleted, the signals supplied from the asynchronous memory signal generation circuit 15 to the SRAM 19 also include the synchronous clock CLK, the address signal ADR, the chip select signal CS, and the read signal except for the data D. Only the RD and the write strobe signal DMA_WE are provided.
[0102]
The fourth embodiment is an example of transfer timing from the SRAM 19 to the I / O, and shows that it is effective to provide a DMA transfer wait setting register even if the transfer target is not the SDRAM.
[0103]
Referring to FIG. 7, which is a timing chart for explaining the operation of the fourth embodiment and showing the timing of the single address DMA transfer, it shows the transfer between the SRAM and the I / O. This is a case where, for example, 1 is set as the number of data weights in the setting register.
[0104]
In the SRAM 19, during the T1 state and the T3 state, the address ADR is supplied with ADm, and the chip select signal CS is supplied at low level during the period from the T1 state to the T12 state.
[0105]
The read signal RD is at a low level during the T1 period, and is at a high level in the T4 state.
[0106]
The write strobe signal DMA_WE is supplied to the I / O device 17 at a low level between the T1 and T3 states and at a high level between the T3 and T4 states.
[0107]
In this embodiment, the number of transfer clocks is 12 clocks. If the number of data waits is set to 0, transfer can be performed in eight clocks.
[0108]
First, upon receiving the DMA transfer request DMA_REQ, the memory controller issues a read command to the SRAM 19 in the T1 state. Here, since the number of waits 1 is set in the DMA transfer wait setting register 12, the data D normally output only from the T1 state to the T2 state is extended by one CLK by this wait, and the speed of the low-speed device is reduced. The write time is secured up to the T3 state. The other signals ADR, CS, and RD are each extended by 1 CLK.
[0109]
The asynchronous memory signal generation circuit 15 makes DMA_WE low active from the T1 state to the T3 state in order to take in the data D output from the SRAM 19, and takes in the data.
[0110]
Therefore, the data output from the SRAM 19 can be weighted.
[0111]
As described above, by setting the number of waits in the DMA transfer wait setting register 12, the data D normally output between the T1 and T2 states is extended by 1 CLK, and the write time of the low-speed device is reduced to the T3 state period. Until the end of From the T3 state to the T12 state, the above operation is repeated.
[0112]
In this embodiment, the transfer target is the I / O device 17 and the SRAM 19, but in terms of a high-speed memory and a low-speed I / O device, the SRAM 19 and the I / O device 17 as in the embodiment shown in FIG. According to the present invention, the CPU access can be performed at high speed, and the single address DMA transfer can be performed according to the specifications of the I / O device 17.
[0113]
Further, any of the weight insertion methods of the first, second and third embodiments described above may be used.
[0114]
As described above, in this embodiment, by setting the number of waits in the DMA transfer wait setting register 12, the same effect as in the first, second, and third embodiments, that is, the number of waits is 1 In this case, the transfer of four words can be realized by 12 CLKs from the T1 state to the T12 state, and one transfer can be reduced to 4/5.
[0115]
In addition, since the access to the SRAM 19 from the CPU can be performed at a high speed as before, the transfer rate of the CPU 19 is not reduced. Further, since the signal generator for the synchronous memory is not provided, the circuit scale can be reduced accordingly.
[0116]
【The invention's effect】
As described above, the memory controller according to the present invention provides a high-speed data access that secures a data transfer rate by accessing the external memory from a CPU capable of high-speed access with a minimum number of waits corresponding to the operation speed of the CPU. In a single address DMA transfer in which data is transferred from a high-speed external memory to a low-speed external memory without using a transfer unit and a CPU, the number of waits according to the data access time of the low-speed external memory is determined by: A low-speed data transfer means for securing a data transfer rate by being inserted into an operation cycle of an external memory having a high operation speed is also provided. Therefore, in the case of the conventional example, the transfer destination I / O device has a low speed at 1 CLK pitch. If single address transfer cannot be realized, the only option is to perform dual address transfer. If vice were light required 2CLK of was necessary 15CLK to 4 word transfers from SDRAM.
[0117]
However, according to the present invention, four-word transfer can be realized with 10 CLK, and one transfer can be reduced to 2/3. Further, since the SDRAM access from the CPU can be performed at a high speed as before, the transfer rate of the CPU is not reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram of a first embodiment of the present invention.
FIG. 2 is a timing chart for explaining the operation of the first embodiment of the present invention.
FIG. 3 is a block diagram of a second embodiment of the present invention.
FIG. 4 is a block diagram of a third embodiment of the present invention.
FIG. 5 is a timing chart for explaining the operation of the third embodiment of the present invention.
FIG. 6 is a block diagram of a fourth embodiment of the present invention.
FIG. 7 is a timing chart for explaining the operation of the fourth embodiment of the present invention.
FIG. 8 is a block diagram illustrating an example of a conventional weight control circuit.
[Explanation of symbols]
11 Wait setting register
12 DMA transfer wait setting register
13 Selector
14 Memory access control signal generation circuit
15 Signal generation circuit for asynchronous memory
16 SDRAM signal generation circuit
17 I / O devices
18 SDRAM
19 SRAM
ADR address
CAS column address strobe signal
CKE clock enable signal
CLK Operation clock
D Data bus
DMA_REQ Single address DMA transfer request
DMA_WE write strobe signal
DQM data mask signal
M_REQ Memory access request
RAS row address strobe signal
WE write enable signal

Claims (9)

When performing data transfer between the CPU and the synchronous memory, a first operation cycle is generated based on a wait when accessing the synchronous memory, and when performing data transfer between the CPU and the asynchronous memory, A second operation cycle based on a wait when accessing the asynchronous memory is generated, and when a single address DMA transfer is performed between the synchronous memory and the asynchronous memory, the wait during the single address DMA transfer is performed. A memory access control signal generation circuit for generating a third operation cycle based on the control signal and supplying the generated signal to the synchronous memory. 2. The single address DMA transfer, wherein a wait based on a clock enable signal generated by a wait at the time of the single address DMA transfer is inserted into the third operation cycle of the synchronous memory. A memory controller according to claim 1. 3. The memory controller according to claim 1, wherein the synchronous memory is a synchronous dynamic random access memory (SDRAM). The memory access control signal generation circuit writes data read from the synchronous memory to the asynchronous memory during a read cycle of the synchronous memory, and the single address DMA from the synchronous memory to the asynchronous memory. The memory controller according to claim 1, wherein the transfer is performed. The memory access control signal generation circuit includes a synchronous memory signal generation circuit that outputs the first or third operation cycle for the synchronous memory, and a second or third operation cycle for the asynchronous memory. An asynchronous memory signal generating circuit to output; a synchronous memory signal generating circuit; a bidirectional data bus means for commonly connecting the synchronous memory and the asynchronous memory; The memory controller according to any one of claims 1 to 4, further comprising: A CPU weight setting register in which the CPU sets at least one of a wait when accessing the synchronous memory and a wait when accessing the asynchronous memory, and the CPU sets a wait during the single address DMA transfer DMA wait setting register, and wait selecting means for selectively outputting a value of one of the CPU and DMA wait setting registers to the memory access control signal generation circuit in response to a data transfer request. The memory controller according to claim 1, wherein: 7. The memory controller according to claim 6, wherein there are a plurality of said DMA wait setting registers, and said plurality of DMA wait setting registers can be selected from said plurality of DMA wait setting registers by said data transfer request. The CPU sets the wait when accessing the asynchronous memory or the wait during the single address DMA transfer, and the wait set in the shared wait setting register to the memory access control signal generation circuit. Wait selection means for selectively outputting the data, wherein in the data transfer between the CPU and the synchronous memory, the first operation cycle has no wait in response to a data transfer request; Wherein the data transfer request or the single address DMA transfer is controlled by the data transfer request in a second or third operation cycle in which the wait of the shared wait setting register is inserted. 6. The memory controller according to any one of 1 to 5. 6. The wait according to claim 2, wherein the wait at the time of the single address DMA transfer is given by a wait signal from the asynchronous memory, and the clock enable signal is generated in response to the wait signal. Memory controller.

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