JP3957421B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a control technique for a semiconductor memory device, and more particularly to a technique effective when applied to a semiconductor memory device suitable for improving system operation efficiency using a clock synchronous memory such as a synchronous DRAM (SDRAM).
[0002]
[Prior art]
For example, as a technique studied by the present inventor, in SDRAM and the like, for example, the read latency is set to 1 to 3 cycles with CAS latency, and the memory access efficiency is set so as not to decrease according to the frequency of the system clock. On the other hand, a technique for performing the operation with the write latency fixed to 0 or 1 can be considered.
[0003]
As a technique related to such a semiconductor memory device such as an SDRAM, for example, a technique described in “Advanced Electronics I-9 Super LSI Memory” issued on November 5, 1994, published by Baifukan Co., Ltd. can be cited.
[0004]
[Problems to be solved by the invention]
By the way, according to the semiconductor memory device such as the SDRAM as described above, since the write latency is fixed, for example, in a system in which operations such as continuous write operation-read operation-write operation are performed, the bus idle time. It is considered that the dead cycle increases.
[0005]
Here, an example of FIG. 5 illustrating a data transition during an operation in which a continuous write operation-read operation-write operation is performed will be described. Here, the operation is performed when CAS latency CL = 2 and burst length BL = 4. In this example, since write latency = 0 and read latency = 2, as shown in the figure, there is a free time on the input / output data I / Oi bus during the write operation-read operation. In a read operation / write operation, high impedance control is performed before a predetermined data length (BL = 4) is read in order to avoid data collision on the bus of the input / output data I / Oi.
[0006]
That is, since the write latency is fixed at the time of continuous write operation-read operation-write operation, an empty time is generated on the bus during write operation-read operation, and read data is read during read operation-write operation. Cancellation (masking) may occur, and the efficiency of the system bus may be reduced.
[0007]
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor memory device capable of improving the efficiency of a system bus by changing a write latency setting in accordance with a read latency in a clock synchronous memory such as an SDRAM. It is.
[0008]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0009]
[Means for Solving the Problems]
Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
[0010]
That is, a semiconductor memory device according to the present invention includes a write register that enables setting of a plurality of types of write latencies and a read register that enables setting of a plurality of types of read latencies. The write latency setting is made variable in accordance with the CAS latency (read latency) of the clock synchronous memory.
[0011]
This write register selects one from a plurality of types of delayed state signals generated based on the write state signal by a preset control signal in accordance with the CAS latency, and is delayed by a predetermined amount. A multiplexer circuit that outputs as a state signal, and a register that controls the clock signal for internal data capture by the delayed state signal from the multiplexer circuit and outputs it as internal data of a predetermined latency based on external data for writing Circuit.
[0012]
The read register selects one of a plurality of types of delayed data generated based on the read internal data according to the CAS latency according to a preset control signal, and has a predetermined latency. It consists of a multiplexer circuit that outputs as external data.
[0013]
In this arrangement, or equal to the values of the read latency and the write latency, if a plurality of semiconductor memory devices are connected to the system bus, individually among the semiconductor memory device and a read latency and the write latency It is something that is set.
[0014]
Therefore, according to the semiconductor memory device, the efficiency of the system bus can be improved. As a result, the performance of the system can be improved. That is, by combining the read latency and write latency of the memory, it is possible to eliminate system bus idle time and dead cycles in continuous interrupt operations and the like. As a result, the bus efficiency can be maximized, so that the performance of the entire system can be improved.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0016]
1 is a schematic functional block diagram showing a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing an input register in the semiconductor memory device of this embodiment, and FIG. 3 shows an operation of a write operation. FIG. 4 is a timing chart showing operations of continuous write operation-read operation-write operation.
[0017]
First, a schematic functional configuration of an example of the semiconductor memory device according to the present embodiment will be described with reference to FIG.
[0018]
The semiconductor memory device of the present embodiment is, for example, a 256 Mb SDRAM having a two-bank configuration, two memory array banks MAB0 and MAB1, and a row decoder RD, a column decoder CD and a sense amplifier corresponding to each memory array bank MAB0 and MAB1. & I / O bus SA & IOB, common row address buffer RAB, column address buffer CAB, column address counter CAC, refresh counter RC, input buffer IB, output buffer OB, input register IR, output register OR, control logic & timing generator It consists of CL & TG and the like and is formed on one semiconductor chip by a known semiconductor manufacturing technique.
[0019]
In this SDRAM, in addition to the clock signal CLK, control signals include a clock enable signal CKE, a chip select signal / CS, a row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal / WE, and a data mask signal. / DQM and the like are input from the outside, and an internal control signal is generated by the control logic & timing generator CL & TG based on these control signals, and operations of internal circuits such as a read operation and a write operation are controlled by this internal control signal. It has become so.
[0020]
In the read operation and write operation of the SDRAM, the row address signal and the column address signal are respectively input to the row address buffer RAB and the column address buffer CAB based on the address signal Aa input from the outside, and the row decoder RD, Arbitrary memory cells in the memory array banks MAB0 and MAB1 are selected via the column decoder CD. Then, at the time of reading, the memory cell data is output from the output buffer OB as input / output data I / Oi via the sense amplifier & input / output bus SA & IOB and the output register OR, and at the time of writing, the output data Qi for reading is written. Input data Di is input from the input buffer IB via the input register IR.
[0021]
Next, the input register IR that makes the write latency setting variable according to the read latency, which is a feature of the present embodiment, will be described. This input register IR selects one of a plurality of types of delayed state signals generated based on the write state signal WD-EN by a preset control signal CL-Control according to the CAS latency. , A multiplexer circuit that outputs a predetermined delayed state signal, and a clock signal for taking in internal data is controlled by the delayed state signal from the multiplexer circuit, and a predetermined latency based on the external data Dini for writing is controlled. It consists of a register circuit that outputs as internal data Int-Dini, and a circuit example will be described with reference to FIG. 2 and a timing example with reference to FIG.
[0022]
In FIG. 2, an input register IR includes a multiplexer circuit that outputs a write state signal WD-EN123, which is input with the write state signal WD-EN from the control logic & timing generator CL & TG, and external data from the input buffer IB. A register circuit which receives Dini as input and outputs internal data Int-Dini. The write state signal WD-EN is a write state signal asserted by a write command.
[0023]
The multiplexer circuit receives the write state signal WD-EN, operates in synchronization with the clock signal CLK, and a plurality of flip-flops FF1 cascaded in three stages to generate different types of delayed state signals. To FF3 and a selector SL that outputs one of the state signals generated from the flip-flops FF1 to FF3 as a write state signal WD-EN123 that is delayed by selecting one by the control signal CL-control is provided. Yes.
[0024]
The register circuit receives external data Dini and inputs a flip-flop FF4 that operates in synchronization with the clock signal CLK, a gate AND that performs an AND operation on the clock signal CLK and the delayed write state signal WD-EN123, and a gate A flip-flop FF5 that operates in synchronization with the internal data capturing clock signal WD-CLK123 from the AND and outputs the internal data Int-Dini corresponding to the write latency is provided.
[0025]
3A shows the timing when the control signal CL-control = 1, and FIG. 3B shows the timing when the control signal CL-control = 3. At this time, when the control signal CL-control = 1, the multiplexer circuit selects the write state signal WD-EN123 delayed only by the one-stage flip-flop circuit FF1 by the selector SL, and the control signal CL-control. When = 3, the write state signal WD-EN123 delayed through the three-stage flip-flop circuits FF1 to FF3 is selected.
[0026]
For example, as shown in FIG. 3A, in the case of the control signal CL-control = 1, the write operation command COM is issued in the first cycle in synchronization with the clock signal CLK. Write data D1 to D4 are input as input / output data I / Oi in order from the second cycle. The write data D1 to D4 are obtained from the write state signal WD-EN123 further delayed within the range of one cycle based on the write state signal WD-EN delayed from the rising edge of the clock signal CLK in the first cycle. Is generated and is taken in as internal data Int-Dini in synchronization with the internal data fetching clock signal WD-CLK123 by the logical product operation of this and the clock signal CLK.
[0027]
Similarly, in the case of the control signal CL-control = 3 as shown in FIG. 3 (b), the write operation command COM is issued in the first cycle in synchronization with the clock signal CLK. Write data D1 to D4 are input in order from the fourth cycle. The write data D1 to D4 are written based on the write state signal WD-EN delayed from the rising edge of the clock signal CLK in the first cycle, and are further delayed within a range of 2 to 3 cycles. EN123 is generated, and is taken in as internal data Int-Dini in synchronization with the internal data take-in clock signal WD-CLK123 by the logical product operation of this and the clock signal CLK.
[0028]
The output register OR has the same configuration as the multiplexer circuit of the input register IR, and includes a plurality of flip-flops and selectors (not shown) that receive the internal data Int-Douti and output the external data Douti. Accordingly, one of a plurality of types of delayed data generated based on the read internal data Int-Douti is selected by a preset control signal CL-control, and the external data Douti having a predetermined latency is selected. It has a multiplexer circuit configuration for output.
[0029]
Next, an example of transition of input / output data I / Oi at the time of continuous write operation-read operation-write operation will be described with reference to FIG.
[0030]
Here, as shown in FIG. 4, in the operation when CAS latency CL = 2 = read latency = write latency and burst length BL = 4, the command COM is written in the first cycle in synchronization with the clock signal CLK. A command Write (a) shows a case where a read command Read (b) is issued in the second cycle and a write command Write (c) is issued in the sixth cycle.
[0031]
First, when the write command Write (a) is issued in the first cycle, the write data D (a1) is input in the third cycle two cycles later (write latency = 2). On the other hand, since the read command Read (b) is issued in the second cycle, the read data Q (b1), Q (b2) is obtained from the fourth cycle to the seventh cycle after the second cycle (read latency = 2). ), Q (b3), and Q (b4) are sequentially output for the burst length.
[0032]
Furthermore, for the write command Write (c) issued in the sixth cycle, the write data D (c1), D (c2), D (c2),・ ・ Is entered. As described above, when a write command and a read command are issued, data is input and output after two cycles. When inputting / outputting the input / output data I / Oi, priority is given to issuing a new command by an interrupt operation.
[0033]
In the operation of the above continuous write operation-read operation-write operation, since write latency = read latency = 2, there is a free time on the I / O data I / Oi bus even during the write operation-read operation. do not do. In the read operation-write operation, it is not necessary to interrupt the burst read and perform high impedance control.
[0034]
Therefore, according to the semiconductor memory device of the present embodiment, the output register OR for changing the read latency setting and the input register IR for changing the write latency setting are provided to match the read latency and the write latency. As a result, the system bus idle time and dead cycle can be eliminated in continuous interrupt operations, etc., so that the bus efficiency can be maximized and the overall system performance can be improved. .
[0035]
For example, in the operation of the present embodiment, an improvement in bus efficiency of about 22% is seen with respect to the operation shown in FIG. Further, it is clear that the bus efficiency is further improved (about 20 to 30%) in the continuous write operation-read operation-write operation operation and interrupt operation.
[0036]
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.
[0037]
For example, when a plurality of SDRAM are connected to the system bus, by setting individually among La site latency, the read latency plurality of SDRAM, also more, be controlled to increase the efficiency of the bus It is.
[0038]
In addition, although the example of 256 Mb SDRAM having a two-bank configuration has been described, there is a tendency to increase the number of banks such as 4 banks and 8 banks, and the present invention can be widely applied to SDRAMs having a capacity of 1 Gbit or the like. The effect of the present invention is further increased by adopting a large capacity configuration.
[0039]
Furthermore, the present invention is effective not only for SDRAM but also for DDR SDRAM and the like, and can be widely applied to all other clock synchronous memories in general.
[0040]
【The invention's effect】
Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.
[0041]
(1). Has a write register that allows multiple types of write latency settings and a read register that allows multiple types of read latencies to be set, and sets the write latency according to the read latency. By making the variable variable, it is possible to eliminate a system bus idle time and a dead cycle in continuous interrupt operations and the like, so that the bus efficiency can be maximized.
[0042]
(2) According to the above (1), the efficiency of the system bus can be improved in a clock synchronous memory such as an SDRAM, so that the performance of the system can be improved.
[Brief description of the drawings]
FIG. 1 is a schematic functional block diagram showing a semiconductor memory device according to an embodiment of the present invention.
FIG. 2 is a circuit diagram showing an input register in the semiconductor memory device of one embodiment of the present invention.
FIGS. 3A and 3B are timing charts showing the write operation in the semiconductor memory device according to the embodiment of the present invention. FIGS.
FIG. 4 is a timing chart showing operations of continuous write operation-read operation-write operation in the semiconductor memory device of one embodiment of the present invention;
FIG. 5 is a timing chart showing operations of continuous write operation-read operation-write operation in the semiconductor memory device as a premise of the present invention.
[Explanation of symbols]
MAB0, MAB1 Memory array bank RD Row decoder CD Column decoder SA & IOB Sense amplifier & I / O bus RAB Row address buffer CAB Column address buffer CAC Column address counter RC Refresh counter IB Input buffer OB Output buffer IR Input register OR Output register CL & TG Control logic & Timing generator FF1 to FF4 flip-flop SL selector

Claims (4)

It has a write register that enables setting of multiple types of write latencies and a read register that allows setting of multiple types of read latencies, and sets read latencies and write latencies based on CAS latencies. Is,
The write register selects one of a plurality of delayed state signals generated based on the write state signal by a control signal set in advance based on the CAS latency, and has a predetermined delay The multiplexer circuit that outputs as the state signal that has been output and the delayed state signal from the multiplexer circuit control the clock signal for taking in the internal data and output the internal data with a predetermined latency based on the external data for writing Ri Do from a register circuit,
The semiconductor memory device characterized by equal to the value of the write latency value of the read latency. The semiconductor memory device according to claim 1,
The read register selects one of a plurality of types of delayed data generated based on the read internal data according to a control signal set in advance based on the CAS latency, and has a predetermined latency. A semiconductor memory device comprising a multiplexer circuit that outputs external data. The semiconductor memory device according to claim 1, wherein
A semiconductor memory device, wherein when the plurality of semiconductor memory devices are connected on a system bus, the read latency and the write latency are individually set between the semiconductor memory devices. A semiconductor memory device according to claim 1, wherein,
The semiconductor memory device is a synchronous DRAM.

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