JPH10134576A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a data transmission factor while the number of pins of a chip is not increased and the compatibility between memory chips is satisfied and improve the system performance without remodeling hardware by a method wherein a data bus is enhanced to have the capacity double the capacity of a data I/O pad and a datum is outputted in the rising and falling of a row address signal. SOLUTION: When the data of a cell selected by a column address and a row address are read, a 1st data bus 2 which has a process capacity double the capacity of a data I/O pad 7 carries 2n data and transmits the (n) data which are taken out of a memory array first to a 1st buffer 4 and transmits the (n) data which are taken out next to a 2nd buffer 5 through 2nd data buses 3. If a column address strobe signal is activated at a low level, the data in the 1st and 2nd buffers 4 and 5 are outputted from the I/O pad 7 whose data capacity is (n) through I/O buses 6. The two sets of data can be processed by one row address.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of increasing a data transmission rate.

[0002]

2. Description of the Related Art In general, semiconductor memories have been used as a central technology in the information age, which is being mass-produced and speeded up, in 1970.
1Kbit DRAM (DRAM; Dynamic Random A)
Since the development of ccessMemory), with the improvement of circuit design technology and manufacturing technology, high integration and large capacity have been dramatically advanced. Gigabit capacity semiconductor memories are being developed.

In order to achieve high integration and large capacity of such a semiconductor memory device, low power consumption, high-speed data processing, a wide operating margin and low cost are the most important points to be considered. In particular, recent technological trends for high-speed data processing will be schematically described below. A fast page mode (Fast Page Mode) is one of the most widely used methods for increasing the speed. In the high-speed page mode, a column circuit performs a static operation and a column address strobe (CAS; Column Address Strobe) for a column address.
robe), the access is performed, the CAS precharge time is reduced, and the transmission speed can be improved.

[0004] An EDO (Extended Data Out) mode is an improved technique over the high-speed page mode. In the EDO mode, as shown in FIG.
Row address strobe (RAS; Ro) for row address of
X when Address Strobe is enabled
An address (row address) is read, and thereafter, when the CAS of (B) is enabled low, a Y address (column address) is read, and the data output of (D) is
Will continue to validate data even if is disabled high.

That is, since the data is maintained even in the section in which the CAS is disabled, the period THPC (Hyper Page Mode Cycle TPC) is shorter than in the high-speed page mode.
ime) can be reduced. In FIG. 3,
TDOH is an abbreviation of Time Data Output Holding, and C
When the AS changes from a low level to a high level or from a high level to a low level, it means outputting data relating to the Y address.

As another method of processing data at high speed, there is generally a method of increasing the number of pins (Pins) of a DRAM, and this method can improve the data transmission rate. For example, comparing 16 I / O and 32 I / O from the following equations (1) and (2), it can be seen that the data transmission rate is significantly improved when the number of data pins is increased. (1) 16 I / O: 57.2 Mbyte / sec = 2 bytes x (1/35 n
sec) = 2 x 28.6 M (2) 32 I / O: 114.4 Mbyte / sec = 4 byte x (1/35 n
sec) = 4 × 28.6 M Note that 35 nsec in the above equation is TRAC (Access Time from
/ RAS) = 50nsec and TCAC (Access Time from
/ CAS) = 35nsec.

[0007]

However, among the conventional high-speed data processing methods, when the EDO mode is used,
Although the processing speed is improved as compared with the DRAM having the high-speed page mode, it does not reach the processing speed of the CPU (Central Process Unit), and the SDRAM (Sy
There is a problem that the nchronous DRAM) and the DRAM are almost incompatible.

In the method of increasing the number of pins of data, the number of pins of data of equation (1) is doubled as determined from equations (1) and (2) (2). In equation (2), the data transmission rate doubles, but there is a problem that the chip size increases as the number of pins increases. As described above, in the conventional high-speed processing method, it is difficult to improve the data transmission rate while maintaining compatibility between the memory elements, and in order to solve such a problem,
Increasing the number of data pins increases the sap size.

In view of the above, the present invention provides a semiconductor memory device which can output two data for one Y address (column address) and improve the data transmission rate. It is an object of the present invention to be able to realize the present invention without lowering the performance and increasing the chip size.

[0010]

In order to achieve the above object, a semiconductor memory device according to the first aspect of the present invention comprises a memory array (1) for storing data, and a memory array (1) and an external memory. And a data input / output pad (7) for inputting / outputting data by n units between the memory array (1) and the data input / output pad (7).
A data bus (2,3,2) which exchanges at least 2n data with the memory array (1) and simultaneously exchanges at least 2n data with the data input / output pad (7) by n in a time interleaved manner. 6).

According to a second aspect of the present invention, there is provided a semiconductor memory device for storing and storing data, and for inputting and outputting n pieces of data between the memory array and the outside. A data input / output pad (7), a first data bus (2) for transmitting 2n input / output data to / from the memory array (1), and 2n data buses for transmission on the first data bus (2). A second data bus for transmitting n data each, and first and second buffers for temporarily storing n data to be transmitted on the second data bus, respectively.
(4,5) and a data input / output bus (6) for transmitting n data each between the first and second buffers (4,5) and the data input / output pad (7). Is done.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. In the semiconductor memory device according to the present invention, as shown in FIG. 1, the first data bus 2 is extended twice as large as the data input / output pad 7 to improve the data transmission rate. Pat 7 and the first
The first data bus 2 and the memory array 1 via first and second buffers 4 and 5 connecting the data bus 2 to the first data bus 2
Exchanges at least 2n data, and at the same time, in accordance with the column address strobe signal CAS, the first data bus 2 and the data input / output pad 7 are at least 2n data n by time interleave. Exchange data.

More specifically, a memory array 1 having a plurality of memory cells and data are written to the memory array 1 by an external control signal, or data stored in the memory array 1 is output to the outside. Therefore, 2
A first data bus 2 for processing n data, and 2n data transmitted from the first data bus 2 are transmitted to the first and second buffers 4 and 5, respectively, in a time interleaved manner by n data. A second data bus 3 and the second data bus 3
First and second buffers 4 and 5 for temporarily storing data moving between the memory array 1 and the data input / output pad 7 for each n data as an output of the data bus 3; 5 is output n times, or n is output to the first and second buffers 4 and 5, respectively.
And a data input / output pad 7 for inputting data.

The operation of the semiconductor memory device according to the present invention will now be described. As shown in FIG. 2A, the row address strobe signal (/ RAS) is activated low, the X address (row address) is read, and a word line is selected. As shown in FIG. Detecting the point when the X address changes to a low or high state, the internal Y cell is enabled, and the cell data at the portion crossing the word line is placed on the data line. Since the data input / output pad 7 is at least twice as large as the data input / output pad 7, the cell data can be at least twice as large as the data input / output pad 7.

The first data bus 2 is divided into two data buses (second data buses 3), and the first and second data buses 2
For example, the data output from the memory array 1 is connected to the first buffer 4.
Is transmitted to the second buffer 5
Is to be transmitted. When the column address strobe signal (/ CAS) is activated low as shown in FIG. 2B, the data input from the first and second buffers via the data input / output bus 6 becomes the data The data is sequentially input or output via the input / output pad 7, and two data of Y and Y 'are processed for one Y address (column address) as shown in (D).

[0016]

As described above, according to the semiconductor memory device of the present invention, the data bus is extended twice as large as the data input / output pad, and the rise and rise of the Y address selection signal (column address signal CAS). Since the data is output at the falling edge, it is possible to improve the data transmission rate without increasing the number of pins of the chip while satisfying the compatibility between the memory elements. There is an effect that the system performance can be further improved without modifying the hardware.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor memory device according to the present invention.

FIG. 2 is an operation timing chart of the semiconductor memory device according to the present invention;

FIG. 3 is an operation timing diagram of a conventional semiconductor memory device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1; Memory array 2; 1st data bus 3; 2nd data bus 4; 1st buffer 5; 2nd buffer 6; Data input / output bus 7;

Claims (2)

[Claims] A memory array for storing data; and a data input / output pad for inputting / outputting n data between the memory array and an external device.
Between the memory array (1) and the data input / output pad (7), at least 2n data is exchanged with the memory array (1), and at the same time, the data input / output pad (7) is time-interleaved. A semiconductor memory device comprising: a data bus (2, 3, 6) for exchanging at least 2n data by n data according to a system. A memory array for storing data; a data input / output pad for inputting / outputting n data between the memory array and the outside; (1) a first data bus (2) for transmitting 2n input / output data, and a second data bus (2) for transmitting n data of 2n data transmitted on the first data bus (2). 3) and first and second buffers for temporarily storing n data to be transmitted on the second data bus (3) at a time.
(4,5) and a data input / output bus (6) for transmitting n data each between the first and second buffers (4,5) and the data input / output pad (7). A semiconductor memory device.