JP2002260385A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory which can burst-transfer one part of data. SOLUTION: An address input means 1 receives an input of an address. A data input means 2 receives an input of data. A burst transfer means 3 burst- transfers data inputted through the data input means 2 for a region of a cell 6 corresponding to an address through the address input means 1. A burst transfer length specifying means 4 receives specification. A data input restricting means 5 restricts input of data from the data input means 2 when burst transfer length '0' is specified by the burst transfer length specifying means 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a burst transfer mode for continuously transferring a plurality of data by one address designation.

[0002]

2. Description of the Related Art When reading / writing data from / to a semiconductor memory device, it is necessary to specify an address to be accessed.

In a semiconductor memory device having a burst transfer mode, when accessing consecutive addresses, it is possible to access all addresses only by designating a head address.

In a semiconductor memory device having such a burst transfer mode, there is a device capable of setting a burst length when writing data. FIG.
FIG. 2 is a diagram for explaining an operation of such a semiconductor memory device. It is assumed that the physical maximum burst length of the target semiconductor storage device is “4”.

[0005] In synchronization with the 0th rising edge of the CLK (Clock) signal shown in FIG. 10A, a WR1 command (see FIG. 10B) requesting a write is input and the burst length is set. It is assumed that VW = 1 (burst length = 1) (FIG. 10D) is input from the address input terminal as a VW (Variable Write) signal for designating.

Then, the latency (see FIG. 10C)
After the lapse of the time corresponding to the data D11 to D14, the data D11 to D14 are read from the DATA input terminal. In the present example, since the burst length is set to “1”, the data D11 is stored only in the internal data bus # 1 among the internal data buses # 1 to # 4 (FIGS. 10E to 10H). Will be sent.

Data D sent to internal data bus # 1
11 is stored for a predetermined bit of a predetermined address. When the time corresponding to the bank access interval (see FIG. 10B) has elapsed after the input of the WR1 command, the WR2 command is input in synchronization with the second rising edge, and after the time corresponding to the latency has elapsed, Data D
21 to D24 are input, and VW = 4 is input. As a result, the internal data buses # 1 to # 4
D21 to D24 are respectively transmitted. Then, the data D21 to D24 transmitted to the internal data buses # 1 to # 4
Are stored for predetermined bits of consecutive addresses, respectively.

When the time corresponding to the bank access interval has elapsed since the input of the WR2 command, the WR3 command and
VW = 2 is input. As a result, the internal data bus #
Data D31 and data D32 are sent to 1 and # 2, respectively.

The data D21 and D22 transmitted to the internal data buses # 1 and # 2 are stored for predetermined bits of a continuous address, respectively.

[0010]

By the way, a plurality of DAs are required.
In the case of a semiconductor memory device having a TA input terminal, DATA
In many cases, the input terminal group is divided into an upper bit group and a lower bit group, and the burst length is set independently for each.

In such a semiconductor memory device, it may be required to write only to the upper or lower bit group. In such a case, the conventional semiconductor memory device has a problem that unnecessary data is written because there is no means for prohibiting data writing to any of these bit groups.

In the case of a semiconductor memory device having a latency for a write operation, when a write command is first input, data is not written to the cell and held, and then the write command is input. At this point, many devices have a function of writing data corresponding to the first write command to the cell.

When an operation test is performed to determine whether or not the write operation of such a semiconductor memory device is normal,
To write data into a cell, it is necessary to issue a write command twice. In that case, in the case of the conventional semiconductor memory device, since there is no means for inhibiting data writing as described above, writing by the first writing command may interfere with writing by the next writing command. In addition, there is a problem that an operation test becomes complicated to eliminate such interference.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor memory device capable of writing data to a cell in a unit of a bit group.

[0015]

According to the present invention, there is provided a semiconductor memory device having a burst transfer mode shown in FIG. 1 and having a burst transfer mode for continuously transferring a plurality of data by one address designation. Address input means 1 for receiving the address input, data input means 2 for receiving the data input, and data input to the area of the cell 6 corresponding to the address input through the address input means 1 A burst transfer means for burst-transferring data input through the means, a burst transfer length designating means for receiving a designation of a transfer length of the burst transfer means, and a burst transfer length by the burst transfer length designating means; When "0" is designated, there is provided a data input restricting means 5 for restricting data input from the data input means 2. The semiconductor memory device is provided, characterized in that.

Here, the address input means 1 receives an input of an address. The data input means 2 receives data input. The burst transfer unit 3 performs burst transfer of data input via the data input unit 2 to an area of the cell 6 corresponding to the address input via the address input unit 1. The burst transfer length designation means 4 receives designation of the transfer length of the burst transfer means 3. When the burst transfer length “0” is designated by the burst transfer length designating unit 4, the data input limiting unit 5 sets the data input unit 2.
Restrict entry of data from.

In a semiconductor memory device having a burst transfer mode for continuously transferring a plurality of data by specifying one address, address input means for receiving the address, and data input means for receiving the data Burst transfer means for burst-transferring data input via the data input means to an area of a cell designated by an address input via the address input means, and transfer of the burst transfer means A burst transfer length designating means for receiving a length designation, and a transfer limiting means for limiting the transfer by the burst transfer means when the burst transfer length "0" is designated by the burst transfer length designating means. A semiconductor memory device characterized by the above is provided.

Here, the address input means receives an address. The data input means receives data input. The burst transfer means burst-transfers data input through the data input means to a cell area specified by the address input through the address input means. The burst transfer length designation means receives designation of the transfer length of the burst transfer means. The transfer restricting means restricts the transfer by the burst transfer means when the burst transfer length "0" is designated by the burst transfer length designating means.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a principle diagram for explaining the operation principle of the present invention. As shown in FIG. 1, the semiconductor memory device of the present invention comprises an address input unit 1, a data input unit 2,
It is composed of a burst transfer means 3, a burst transfer length designation means 4, a data input restriction means 5, and a cell 6.

Here, the address input means 1 receives an input of a destination address. The data input means 2 receives input of data to be transferred. In this example, data # 1 corresponding to the upper bit group and data # 2 corresponding to the lower bit group are input.

The burst transfer means 3 burst-transfers the data # 1 and # 2 input via the data input means 2 to the area of the cell 6 corresponding to the address input via the address input means 1. I do.

The burst transfer length designation means 4 receives designation of the transfer length of the burst transfer means 3. In this example, a burst transfer length # 1 corresponding to data # 1 and a burst transfer length # 2 corresponding to data # 2 are input, respectively.

The data input restricting means 5 restricts data input from the data input means 2 when the burst transfer length specifying means 4 designates the burst transfer length “0”.

Next, the operation of the above principle diagram will be described. The address indicating the transfer destination of the burst transfer is input to the address input means 1, and "4" bits are set as the burst transfer length # 1 and "0" bits are set as the burst transfer length # 2. Is entered.

The burst transfer means 3 includes a transfer destination address input via the address input means 1 and a burst transfer length # input via the burst transfer length specifying means 4.
1 and # 2 are obtained, and the internal circuit is set.

The data input limiting means 5 refers to the burst transfer lengths # 1 and # 2 supplied from the burst transfer length designating means 4, and since the burst transfer length # 2 is set to "0", It requests the means 2 to restrict the input of the data # 2.

The data input means 2 inputs only data # 1 and supplies it to the burst transfer means 3 when a predetermined time (time corresponding to latency) has elapsed since the input of the address or the like.

The burst transfer means 3 includes the data input means 2
Only the data # 1 supplied from the address input unit 1
The burst transfer is performed to a predetermined area of the cell 6 corresponding to the address supplied from.

As a result, only the upper bit group of the data is transferred to the cell 6. In the present example, the case where only the upper bit group is transferred has been described as an example.
Only the lower bit group can be transferred.

As described above, according to the semiconductor memory device of the present invention, only the upper bit group or the lower bit group of data can be transferred to the cell. In the above example, the division is made into the upper bit group and the lower bit group, but it goes without saying that other division methods can be adopted.

In the above example, the input of data is restricted according to the burst transfer length. However, the burst transfer may be restricted according to the burst transfer length. Next, an embodiment of the present invention will be described.

FIG. 2 is a diagram showing a configuration example of the semiconductor memory device of the present invention. As shown in this figure, the semiconductor memory device of the present invention comprises a control unit 31, a cell 32, a row decoder 33,
It comprises a column decoder 34, an SA (Sense Amplifier) 35, and an I / O circuit 36.

Here, the control unit 31 outputs a clock signal CLK (Clock).
A signal, a CMD (Command) signal, an ADD (Address) signal, a DS (Data Strobe) signal, and a DATA signal are input and supplied to each unit of the device, and at the time of writing, DATA is read at a predetermined timing. Also,
At the time of reading, DATA is read from a predetermined address and output.

The cell 32 is composed of a group of storage elements arranged in a matrix and stores input data. The row decoder 33 controls the cell 3 based on the row address.
Designate 2 predetermined lines.

The column decoder 34 designates a predetermined column of the cells 32 based on a column address. SA35 is the cell 32
Is amplified with a predetermined gain and converted to a digital level.

The I / O circuit 36 controls data input / output. FIG. 3 is a diagram showing a detailed configuration example of the control unit 31 shown in FIG. As shown in FIG.
1 is a CLK input terminal 31a, a CMD input terminal 31b,
ADD input terminal 31c, DS input terminal 31d, DATA
Input terminal 31e, CLK input circuit 31f, CMD input circuit 31g, ADD input circuit 31h, DS input activation determination circuit 31i, DS input circuit 31j, DATA input circuit 3
1k, a CMD decoder 31m, and a burst length determination circuit 31n. Note that one portion surrounded by a broken line is provided for each of the upper bit group and the lower bit group.

Here, the CLK input terminal 31a is connected to the CLK input terminal 31a.
Receive signal input. CMD input terminal 31b
Receive signal input. The ADD input terminal 31c is
Receive signal input. The DS input terminal 31d receives a DS signal. DATA input terminal 31e
Receive signal input.

The CLK input circuit 31f is constituted by a buffer or the like, and supplies the CLK signal input from the CLK input terminal 31a to the CMD input circuit 31g, the ADD input circuit 31h, and the DS input activation determination circuit 31i. .

The CMD input circuit 31g acquires the CMD signal input from the CMD input terminal 31b in synchronization with the CLK signal, and supplies the CMD signal to the CMD decoder 31m. ADD
The input circuit 31h acquires the ADD signal input from the ADD input terminal 31c in synchronization with the CLK signal and supplies the ADD signal to the burst length determination circuit 31n.

The DS input activation determining circuit 31i outputs the burst length (V) determined by the burst length determining circuit 31n.
In response to W), a DSE (Data Strobe Enable) signal is activated.

When the DSE signal supplied from the DS input activation judging circuit 31i becomes active, the DS input circuit 31j inputs the DS signal from the DS input terminal 31d and supplies it to the DATA input circuit 31k.

When the DS signal is supplied from the DS input circuit 31j, the DATA input circuit 31k inputs data from the DATA input terminal 31e and supplies the data to the I / O circuit 36 shown in FIG.

The CMD decoder 31m decodes the CMD signal input from the CMD input circuit 31g, and supplies the CMD signal to a burst length determination circuit 31n when the command is a burst length setting command (hereinafter, referred to as a burst length setting command). I do.

When the burst length setting command is supplied from the CMD decoder 31m, the burst length determining circuit 31n refers to the data supplied from the ADD input circuit 31h to determine the burst length, and a DS input activation determining circuit 3
1i.

Next, the operation of the above embodiment will be described. In the following, first, the basic operation of the present embodiment will be briefly described with reference to FIG. 4, and then the detailed operation will be described with reference to FIG.

FIG. 4 shows a data input terminal (D shown in FIG. 3).
FIG. 3 is a diagram showing how data is transferred from an ATA input terminal 31e) to a cell (corresponding to a cell 32 shown in FIG. 2). As shown in the figure, the 8-bit data input to the DATA input terminals T1 to T8 is divided into an upper bit group and a lower bit group, and successive addresses ADD1 and ADD.
It is stored as two upper bit groups and two lower bit groups.

Here, the maximum burst length is a physical maximum length and is determined by the configuration of the semiconductor memory device. The burst length (MRS: Mode Register Set) is a burst length set by an MRS command for initialization supplied at the time of starting the apparatus. The burst length (VW) is a burst length specified by a VW command when writing data, and has a length equal to or less than the burst length set by the above-described MRS command.

Although FIG. 4 shows an example in which 8-bit data is input to simplify the drawing, in the present embodiment, 16-bit data is input.
It is divided into upper 8 bits and lower 8 bits.

Next, a detailed operation of this embodiment will be described. When the semiconductor memory device shown in FIG. 2 is started,
The control device (not shown) supplies a command for setting the burst length to “4” to the CMD input terminal 31b.

The CMD decoder 31m acquires a burst length setting command via the CMD input circuit 31g, and detects that the setting of the burst length is requested. Subsequently, the control device supplies data indicating “4”, which is the burst length to be set, to the ADD input terminal 31c.

The burst length determining circuit 31n obtains this data via the ADD input circuit 31h, determines that the burst length is "4", and determines that BL = 4.
Input activation determination circuit 31i and DATA input circuit 31
Notify k. The CMD decoder 31m sets the I / O circuit 36 so that the burst length becomes "4".

With the above operation, the setting of the burst length (burst length (MRS) shown in FIG. 4) is completed. Next, a data write operation when the burst length is set to "4" by MRS will be described with reference to FIG.

The WR1 command (FIG. 5B) at the 0th rising edge of the CLK signal shown in FIG.
Is input to the CMD input terminal 31b, and VWU = 1 (see FIG. 5D) and VWU are input to the ADD input terminal 31c.
It is assumed that L = 1 (see FIG. 5 (I)) is input. Here, VWU (Variable Write Upper) is a command for setting the burst length of the upper 8 bits.
WL (Variable Write Lower) is a command for setting the burst length of the lower 8 bits.

The CMD input circuit 31g supplies the CMD input from the CMD input terminal 31b to the CMD decoder 31m. The CMD decoder 31m decodes the CMD, detects that data writing has been requested,
This is notified to the burst length determination circuit 31n.

By the way, as described above, a portion surrounded by a broken line is provided for each of the upper bit group and the lower bit group, and a circuit corresponding to the upper 8 bits (hereinafter referred to as “upper bit”). Circuit) is supplied with a write request and VWU from the CMD decoder 31m, and a circuit corresponding to the lower 8 bits (hereinafter, referred to as a circuit).
CMD decoder 31m
Supplies a write request and VWL.

Hereinafter, the upper bit circuit and the lower bit circuit will be described separately. (1) Operation of Upper Bit Circuit The burst length determination circuit 31n of the upper bit circuit uses the CMD
It recognizes that the data writing is requested by the request from the decoder 31m, and the ADD input circuit 31
By notifying the burst length (= 1) to be set by the VWU obtained via the h, the notification is sent to the DS input activation determination circuit 31i and the DATA input circuit 31k.

When a predetermined time (a time corresponding to the write latency) elapses after the writing is requested, the DS input activation judging circuit 31i outputs a DSE (Data Strobe Enab).
le) Set the signal to "H" state. As a result, the DS input circuit 31j receives the input of the DS signal from the DS input terminal 31d, and converts the input DS signal into the DATA input circuit 31d.
k.

When the DS signal is supplied, the DATA input circuit 31k starts inputting the upper 8 bits of DATA from the DATA input terminal 31e as shown in FIG. 5C. Now, since VWU = 1 is set, DATA
The input circuit 31k transfers only the upper 8 bits of the data D11 among the input data D11 to D14 to the I / O circuit 36 via the internal data bus # U1 (FIGS. 5E to 5E). H)). (2) Operation of Lower Bit Circuit On the other hand, the burst length determination circuit 31n of the lower bit circuit
It recognizes that the data writing is requested by the request from the CMD decoder 31m, recognizes the burst length to be set (= 1) by the VWL obtained via the ADD input circuit 31h, and activates the DS input. Conversion determination circuit 31
i and the data input circuit 31k.

The DS input activation determination circuit 31i sets the DSE signal to "H" when a predetermined time (time corresponding to the write latency) has elapsed since the writing was requested. As a result, the DS input circuit 31j receives the input of the DS signal from the DS input terminal 31d, and supplies the input DS signal to the DATA input circuit 31k.

When the DS signal is supplied, the DATA input circuit 31k starts inputting the lower 8 bits of DATA from the DATA input terminal 31e as shown in FIG. 5C. Now, since VWL = 1 is set, the data input circuit 31k of the lower bit circuit outputs only the lower 8 bits of the data D11 among the input data D11 to D14 via the internal data bus # L1. Transfer to the / O circuit 36 (see FIGS. 5 (J) to 5 (M)).

The above is the operation of the upper bit circuit and the lower bit circuit corresponding to WR1. Subsequently, at the second rising edge of the CLK signal shown in FIG. 5A, a WR2 command is input, and VWU = 4 and VWL =
When 4 is input, the same operation as that described above is performed, and data D21 to D24 are read at the third rising edge of the CLK signal.

Here, since VWU = 4, the data input circuit 31k of the upper bit circuit is connected to the internal data bus #
The upper 8 bits of the data D21 to D24 are transferred to the I / O circuit 36 via U1 to U4 (FIGS. 5E to 5H).
reference).

Since VWL = 4, the data input circuit 31k of the lower bit circuit is connected to the internal data bus #L.
The lower 8 bits of the data D21 to D24 are transferred to the I / O circuit 36 via 1 to # L4 (see FIGS. 5J to 5M).

Subsequently, when a WR3 command is input at the third rising edge of the CLK signal shown in FIG. 5A and VWU = 2 and VWL = 0 are input,
The same operation as that described above is performed, and the fifth CLK
Data D31 to D34 at the rising edge of the signal
Is read.

Here, since VWU = 2, the data input circuit 31k of the upper bit circuit is connected to the internal data bus #
The upper 8 bits of data D31 and D32 are transferred to I / O circuit 36 via U1 and # U2 (FIG. 5E).
To (H)).

In the lower bit circuit, since VWL = 0, the DATA input circuit 31k is connected to the I / O circuit 36.
Is not executed (FIG. 5J).
(M)). As a result, the lower byte will not be written to cell 32.

As described above, VWU or VWL is set to "0".
, The writing of the upper byte or the lower byte can be suspended. In the above example, the writing of data to the lower byte is suspended, but the writing of data to the upper byte can be suspended. In that case, WVU = 0
Is input, the writing to the upper byte is suspended by the same operation as in the case described above.

By the way, the address for designating the VW is not provided exclusively, but a vacant address is usually used. For example, when a row address and a column address are fetched twice, the column address usually has a smaller number of bits, and therefore some of the address terminals prepared for the row address take in the column address. It is vacant at times. For example, VW can be allocated to the vacant address as shown in the following figure.

FIG. 6 shows a case where the burst length is "2" (BL
FIG. 11 is a diagram showing an example of VW assignment to column addresses in the case of = 2). In the example of this figure, VWU and VWL for the upper byte and the lower byte are respectively assigned to A0 to A3. Specifically, VWU = 0 when A0 and A1 are “0” and “0”, and VWU = 0 when A0 and A1 are “1” and “0”.
If WU = 1 and A0 and A1 are “0” and “1”, VWU = 2 is assigned. A similar assignment is made for the lower byte.

FIG. 7 shows a case where the burst length is "4" (BL
FIG. 11 is a diagram showing an example of VW assignment to column addresses in the case of = 4). In the example of this figure, VWU and VWL for the upper byte and the lower byte are respectively assigned to A0 to A3. Specifically, VWU = 0 when A0 and A1 are “0” and “0”, and VWU when A0 and A1 are “1” and “0”.
WW = 1, VWU = 2 when A0 and A1 are “0” and “1”, and VWU = 4 when A0 and A1 are “1” and “1”. ing. A similar assignment is made for the lower byte.

FIG. 8 shows a case where the burst length is "8" (BL
FIG. 11 is a diagram showing an example of VW assignment to column addresses in the case of = 8). In the example of this figure, VWU and VWL for the upper byte and the lower byte are assigned to A0 to A5, respectively. Specifically, A0 to A2
Is "0", "0", "0", VWU = 0, and if A0-A2 are "1", "0", "0", VWU = 1, A0 A2 are “0”, “1”,
When it is “0”, VWU = 2, when A0 to A2 are “1”, “1”, and “0”, VWU = 4, and A0 to A2 are “0”, “0”. If "1" or "1", VWU = 8 is assigned. Note that the lower byte is similarly allocated.

FIG. 9 shows a case where the burst length is "16" (B
FIG. 14 is a diagram illustrating an example of assignment of VWs to column addresses when L = 16). In the example of this figure, VWU and VWU for upper byte and lower byte for A0 to A5
L are respectively assigned. Specifically, A0
When A2 is “0”, “0”, “0”, VWU =
VWU = 1 when A0 to A2 are “1”, “0”, “0”, and A0 to A2 are “0”,
If “1” or “0”, VWU = 2 and A0
When A2 is "1", "1", "0", VWU
= 4, and when A0 to A2 are “0”, “0”, “1”, VWU = 8, and A0 to A2 are “1”,
If it is “0” or “1”, VWU = 16 is assigned. Note that the lower byte is similarly allocated.

As described above, according to the present embodiment, since the burst length can be set to "0" by VW, the transfer of the upper byte or the lower byte can be suspended. Therefore, either the upper byte or the lower byte can be written to the cell 32.

Further, according to the present embodiment, it is possible to suspend writing to both the upper byte and the lower byte by VW. Such transfer forms are:
For example, it is considered to be effective in an operation test of a semiconductor memory device having a write latency.

That is, in the case of a semiconductor memory device having a write latency, when a write command for a certain address is given, only fetching of write data input with a delay in that cycle is executed, and actual writing to the cell 32 is not performed. Executed when the next write command is input.

Therefore, when performing an operation test of such a semiconductor memory device, it is necessary to complete a write operation for the preceding data by inputting a dummy write command after inputting a write command for a certain address. In this case, it is assumed that the dummy data affects the previous data. Therefore, if VWU = VWL = 0 is set and the dummy write is executed, the cell 32
, No data transfer is executed, and such inconvenience can be avoided.

In the above embodiment, when VWU or VWL is "0", the transfer of data to cell 32 is suspended. However, as in the principle diagram shown in FIG. The same effect as in the above-described case can be obtained even when the capture of data from 31e is prohibited.

Further, in the above embodiment, the upper bit group and the lower bit group are divided and the VW is provided for each bit group. For example, other division methods may be adopted. It goes without saying that it is possible.

Further, the configuration examples shown in FIGS. 2 and 3 are only examples, and it is needless to say that the present invention is not limited to only such a case.

[0080]

As described above, according to the present invention, in a semiconductor memory device having a burst transfer mode for continuously transferring a plurality of data by one address designation,
Address input means for receiving an address, data input means for receiving data input, and data input via the data input means for a cell area corresponding to the address input via the address input means A burst transfer means for performing burst transfer of data, a burst transfer length designating means for receiving a designation of a transfer length of the burst transfer means, and a data transfer means when the burst transfer length "0" is designated by the burst transfer length designating means. And data input restricting means for restricting the input of the data described above, it is possible to prevent the write data from interfering with each other when an operation test of the semiconductor memory device is performed.

In a semiconductor memory device having a burst transfer mode for continuously transferring a plurality of data by one address designation, an address input means for receiving an address, a data input means for receiving a data input, Burst transfer means for burst-transferring data input via the data input means to a cell area specified by the address input via the address input means, and receiving a transfer length designation of the burst transfer means Since the burst transfer length designating means and the transfer limit means for restricting the transfer by the burst transfer means when the burst transfer length "0" is designated by the burst transfer length designating means are provided, one of the data Part can be written.

[Brief description of the drawings]

FIG. 1 is a principle diagram for explaining the operation principle of the present invention.

FIG. 2 is a diagram illustrating a configuration example of an embodiment of the present invention.

FIG. 3 is a diagram illustrating a detailed configuration example of a control unit illustrated in FIG. 2;

FIG. 4 is a diagram showing a correspondence relationship between data input from a DATA input terminal and data stored in a cell according to the present invention.

FIG. 5 is a diagram for explaining the operation of the exemplary embodiment of the present invention.

FIG. 6 is a diagram illustrating an example of a method of assigning VWUs and VWLs to column addresses when the burst length is “2”.

FIG. 7 is a diagram illustrating an example of a method of assigning VWUs and VWLs to column addresses when the burst length is “4”.

FIG. 8 is a diagram showing an example of a method of assigning VWUs and VWLs to column addresses when the burst length is “8”.

FIG. 9 is a diagram illustrating an example of a method of assigning VWUs and VWLs to column addresses when the burst length is “16”.

FIG. 10 is a diagram for explaining an operation of a conventional semiconductor memory device capable of setting a burst length when writing data.

[Description of Signs] 1 Address input means 2 Data input means 3 Burst transfer means 4 Burst transfer length specifying means 5 Data input limiting means 6 Cell 31 Control unit 31a CLK input terminal 31b CMD input terminal 31c ADD input terminal 31d DS input terminal 31e DATA input terminal 31f CLK input circuit 31g CMD input circuit 31h ADD input circuit 31i DS input activation determination circuit 31j DS input circuit 31k DATA input circuit 31m CMD decoder 31n burst length determination circuit 32 cell 33 row decoder 34 column decoder 35 SA 36 I / O circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B015 HH03 JJ18 KB36 KB52 KB84 KB92 MM04 NN03 5L106 DD00 FF04 GG07 5M024 AA40 AA90 BB20 BB27 BB30 BB34 BB36 DD83 DD90 JJ02 JJ54 MM10 PP01 PP07 PP10

Claims (6)

[Claims] 1. A semiconductor memory device having a burst transfer mode for continuously transferring a plurality of data by specifying one address, wherein: an address input unit receiving the address input; and a data input unit receiving the data input. Burst transfer means for burst-transferring data input via the data input means to an area of a cell corresponding to an address input via the address input means; transfer length of the burst transfer means A burst transfer length designating means for receiving the designation of: a data transfer limiting means for limiting data input from the data input means when the burst transfer length “0” is designated by the burst transfer length designating means; A semiconductor memory device comprising: 2. The burst transfer length designating means is capable of setting a burst transfer length of data in a predetermined bit group unit, and the data input limiting means is configured to restrict data input in the predetermined bit group unit. The semiconductor memory device according to claim 1, wherein: 3. The semiconductor device according to claim 1, wherein said data input means starts data input after a predetermined time has elapsed since the burst length was specified by said burst transfer length specifying means. Storage device. 4. A semiconductor memory device having a burst transfer mode for continuously transferring a plurality of data by one address designation, wherein: an address input means for receiving the address input; and a data input means for receiving the data input. Burst transfer means for burst-transferring data input via the data input means to an area of a cell specified by an address input via the address input means; and transfer of the burst transfer means. Burst transfer length designating means for receiving a length designation, and transfer limiting means for limiting the transfer by the burst transfer means when the burst transfer length “0” is designated by the burst transfer length designating means. A semiconductor memory device characterized by the above-mentioned. 5. The burst transfer length designating means can set a burst transfer length of data in a unit of a predetermined bit group, and the transfer restricting unit limits data transfer in a unit of the predetermined bit group. The semiconductor memory device according to claim 4, wherein: 6. The semiconductor memory according to claim 4, wherein said data input means starts data input after a predetermined time has passed since the burst length is specified by said burst length specifying means. apparatus.