JP2003151273A - Storage device, internal control method for storage device, system, and control method for storage means in system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a storage device to which efficient access can be performed and in which current consumption can be reduced without changing a package, an internal control method for a storage device, a system, and a control method for a storage means in a system. SOLUTION: A memory device changes a shape of a logic address map of a DRAM core in accordance with a page length specifying signal outputted from a mode register. And when page length is set shorter than full page by the page length specifying signal, a row address Row increased by the above is taken in simultaneously with a column address Co1 at the time of the first red-command RD1. At the time, the address Row being increased is taken in from an external address terminal being not used at the time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device, a storage device internal control method, a system, and a storage means control method in the system.

In recent years, a semiconductor memory (dynamic RAM: Dynamic RAM), which requires a data holding operation at any time, has an increased storage capacity required by a customer (system side), an increased access speed (increased operating frequency), and an I / O The current consumption tends to increase due to the expansion of the O bus width (increasing the width of the number of bits handling data in one access). With this,
The current consumption of the entire system equipment equipped with the memory device is also increasing, and customers are demanding to reduce the power consumption of the memory device.

Further, the increase in the above-mentioned current consumption may cause a rise in the chip temperature of the memory device. Generally, D
RAM cell data retention characteristics (≈ Refresh characteristics: TREF)
Is deteriorated at high temperature (holding time is shortened), and for this reason also, reduction of current consumption is required.

Therefore, semiconductor memories are required to have improved performance such as increased storage capacity, increased access speed, and expanded I / O bus width, as well as reduced power consumption.

[0005]

2. Description of the Related Art A memory device has a memory cell array in which a plurality of memory cells are arranged in an array and a sense amplifier. Each memory cell is connected to a word line and a bit line, and the sense amplifier is connected to the bit line. The sense amplifier is paired with the bit line and amplifies and holds information (read data) of one cell.

The memory cell array is array-developed in the X-expansion direction in which the word line is expanded by the row address and in the Y-expansion direction in which the bit line and the sense amplifier are expanded by the column address. If the memory capacity is 1 Mbit, the logical address of the memory device is 10 bits (2
¹⁰ = 1024 word lines: WL) X address (Row
Address) can be configured from a Y address (Column Address) of 10 bits (2 ¹⁰ = 1024 bit lines: BL (1024 sense amplifiers)) (Note: bit line definition = pair of complementary bit lines) ). At this time, if the wiring pitches of the word lines and the bit lines are the same, the logical memory array is imaged as a square.

The internal operation of the memory device is an SDRAM (Synchr) which is synchronous with the system clock CLK.
Onous DRAM) will be described as an example. SDRAM is
Active / synchronous with the system clock CLK to activate / deactivate the memory device as a control command.
It operates by a precharge command (falling and rising of a chip enable signal / CE (“/” indicates a bar) in an asynchronous memory device) and a read / write command for inputting / outputting data to / from the memory device.

When an active command is externally applied at the rising edge of the system clock CLK, the X address is fetched and decoded by the X decoder to select one word line and activate it. Each memory cell connected to the selected word line outputs data to each bit line, and each sense amplifier amplifies and holds the data (latches the data).

After that, when a read command is externally applied at the rising edge of the system clock CLK (with a delay of several CLKs from the active command), the Y address is fetched and decoded by the Y decoder to be held in one sense amplifier. Output data to the outside of the memory device.
Further, when a write command is externally applied, the Y address is fetched and decoded by the Y decoder to write the write data (input when the write command is applied) to the memory cell via one sense amplifier. After that, if necessary, read / write commands are issued at any time, and the desired Y
The memory cell is accessed according to the address and the outside.

After the read / write command is completed,
At the rising edge of the system clock CLK (with a few CLK delay from the read / write command), a precharge command is applied to reset (equalize) the activated word line, sense amplifier and bit line, and the memory array becomes Return to the initial state (preparing for the next active command).

It takes an internal time until the reset operation, and it is necessary to wait (wait) for several CLKs in order to apply the next active command from the precharge command. Similarly, it is necessary to delay (wait) several CLK from the active command to the read / write command.

Although the number of input / output bits of the memory array is 1 for simplicity of explanation, the number of input / output bits is n (nI / O) (ex.4I / O). )
In this case, n sense amplifiers are simultaneously selected by the Y address. Each sense amplifier is connected to n I / O ports via n I / O buses.

The depth of the Y address is called the page length. In response to one active command, the memory device operates at least I / O bus width × page length sense amplifiers. For example, in the case of an SDRAM in which the Y address is set to 8 bits (YA <0: 7>), the page length is 256. This SDRAM is a 32-bit I / O
With the O bus width, at least 8,192 (= 256 × 32) sense amplifiers operate in response to the active command.

The SDRAM latches information of a plurality of memory cells connected to a word line selected by an active command in a plurality of sense amplifiers by a read command input at any time. Therefore, by activating one word line, the information of the memory cells for the page length can be appropriately read out. More specifically, for each read / write command that is input at any time, the Y decoder is used to select a sense amplifier at any time according to the Y address that is input at the same time as the command, so that information is read from the memory cell at an arbitrary Y address. That is, the X address can be randomly accessed while the X address is fixed. Such an operation is called a Y address priority operation. Information can be similarly written to the memory cell of an arbitrary Y address in response to a write command.

In this Y address priority operation, in addition to the advantage of random access, it is possible to efficiently use a plurality of data latched in each sense amplifier of the sense amplifier group which operates by one active command. . In other words, one word line charge / discharge current and one (plural) sense amplifier (plural) bit line charge / discharge currents enable random access to the memory cells included in page 256.

Therefore, the current consumption required for one access is a value obtained by dividing the current consumption due to the charge / discharge of the word line and the charge / discharge of the bit line by the number of accesses to the page activated at the same time. Therefore, as the number of accesses in a page activated at the same time increases, the current consumption of the SDRAM per access decreases.

Further, in the Y address priority operation, the number of clocks required from application of the active command to the read / write command and the number of clocks required from application of the precharge command to the next active command are The share of the Therefore, the ratio of data occupying the input / output bus (data occupancy) is high, and the efficiency of the I / O bus in the system is good. For these, the higher the system clock frequency (higher frequency), the greater the latency that must be taken.
In M, the data occupation rate of the input / output bus can be increased.

[0018]

By the way, the SDRAM
Depending on the customer's system that uses, the bit length to be accessed is small (for example, continuous 4 bits or 8 bits). SDRAM by such a system
Access from a single active command to the precharge command, the number of reads / reads that is less than the page length.
The write operation cannot be performed and X is generated by the next active command.
The address is changed. For convenience, such an operation is performed as X.
This is called address priority operation. In this operation, the sense amplifier activated by one active command is not used efficiently.

For example, the Y address is changed (the X address is constant) and four memory cells are accessed. In this case, the charge / discharge current of one word line selected by the X address and the number of activated sense amplifiers (8192).
Current) (including the charge / discharge current of the bit line by the sense amplifier). The current consumption at this time is P (y). Therefore, the consumption current for accessing one memory cell is P (y) / 4.

On the other hand, when the X address is changed (the Y address is arbitrary) to access four memory cells, an active command and a precharge command are required every time the X address is changed. Therefore, in the case of this access method, four times (4
× P (y)), and the current consumption for accessing one memory cell is P (y).

Therefore, in the case of a system or application which frequently uses the X address priority operation, a memory device having a shallow Y address (a small number of pages) and a deep X address is effective.

However, the X address priority operation and the Y address priority operation may be mixed depending on the access method of the system using the memory device and the step of the application. In such a case, if a memory device having a shallow Y address is used, the access speed may be extremely slow depending on the access order, which hinders the speed improvement. On the other hand, using a memory device with a shallow X address hinders reduction of current consumption.

Further, such memory devices having different depths of the X address and the Y address have different pin arrangements and package sizes from the standard products, so that the memory devices cannot be simply replaced. For this reason, it has been necessary to re-create a board or the like on which the memory device is mounted, which causes an increase in cost and a longer development period.

Further, when a large current consumption operation such as an X address priority operation is repeated, the chip temperature (junction temperature) of the memory device may be increased. In this case, the data retention characteristic deteriorates due to the temperature rise, and the refresh operation, which is a data retention operation, must be frequently performed. Then, the chip temperature is the sum of the temperature rise due to the access to the memory device and the self-heating due to the refresh operation of the memory device, which leads to the deterioration of the data retention characteristic and the further increase of the current consumption due to the frequent refresh operation. Further, when the data holding operation is performed asynchronously regardless of the control of the customer system side (self-refresh operation), the busy state in which the refresh operation does not respond to the access from the outside increases, and the system performance increases. Decrease (the data occupancy of the I / O bus decreases).

The present invention has been made to solve the above problems, and an object of the present invention is to provide a storage device and a storage device which can achieve efficient access and reduction of current consumption without changing the package. Internal control method, system,
Another object of the present invention is to provide a method of controlling storage means in the system.

[0026]

According to the invention described in claims 1 and 3, an M-bit first address and an N-bit second address are provided.
A memory device that accesses a memory cell array in which memory cells are arranged in an array by an address has a first address and a second address.
Either an address terminal for taking in an address at the same time is provided, or an address terminal having a larger number of the first address and the second address is provided. Then, the storage device replaces a part of the external address with the first address or the second address based on the access form information that changes the shape of the logical address map of the memory cell array.

According to the second and fourth aspects of the invention, the storage device invalidates the external address or a part thereof based on the access form information for changing the logical address map shape of the memory cell array.

According to the fifth and seventh aspects of the present invention, either an address terminal for simultaneously taking in the M-bit first address and the N-bit second address is provided, or the M-bit first address and the N-bit first address. A memory means for accessing a memory cell array in which memory cells are arrayed at the first address and the second address, and a control means for accessing and controlling the memory cell array are provided. In the above system, the control means supplies the access form information to the storage means at any time.
Then, the storage means generates an i-bit increased address that increases according to the logical address map shape of the memory cell array changed based on the access form information in a time division after generating the first address.

According to the invention of claim 6, claim 5
In addition to the operation of the invention described in (1), the control means performs the access form information by any one of the address, the decoder and the code information by the control signal.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) A first embodiment of the present invention will be described below.

FIG. 1 shows a memory device (SDRAM) 1.
It is a block diagram for explaining the outline of 0. The memory device 10 is connected to a CPU (not shown), and the CPU
Gives the access form information to the memory device 10 once or before access is started. The memory device 10
It has a function of changing the logical address map shape according to the access form information. More specifically, the memory device 10
Changes the logical address map shape in response to access form information applied from the outside (CPU). Therefore,
The CPU functions as a memory controller that controls the logical address map shape of the memory device 10.

The logical address map shape is determined by the depth of the X address and the Y address. The capacity of the memory cell array is constant. Therefore, the memory device 10
The depth of the X address and the depth of the Y address are changed complementarily.

The memory device 10 inputs an address signal of the number of bits required for designating the maximum value of the X address and the maximum value of the Y address from the external address terminal by using a plurality of logical address map shapes. And
The memory device 10 has the same outer shape as a standardized memory device having substantially the same memory capacity.

For example, a memory device having a capacity of 64 Mbits (32 I / O, 4-bank structure) generally (standard) has 0.5 MB memory cells for each I / O in each bank. Each bank is selected by a 2-bit bank address. The memory cells in each bank are plural (2048 lines) selected by an 11-bit row address (X address) and plural (256 lines) selected by an 8-bit column address (Y address).
Are arrayed by bit lines. And SD
A memory device such as a RAM is configured to take in an X address and a Y address by an address multiplexing method. Therefore, a typical memory device is
It has 3 address pins from which a 13-bit X
An address (of which, a 2-bit bank address) and a Y address are fetched in a time division manner.

Next, the functional configuration of the memory device 10 will be described. The memory device 10 includes the clock buffer 1
1, a command decoder 12, an address buffer 13, an input / output buffer 14, a control signal latch 15, a mode register 16, an address generation circuit 17, a write / read (I / O) control circuit 18, and a DRAM core 19.

The clock buffer 11 inputs the clock enable signal CKE and the external clock signal CLK from an external device and outputs the internal clock signal CLK1 generated based on them to each circuit.

The command decoder 12 responds to the internal clock signal CLK1 from the clock buffer 11, that is, the clock signal CLK, in response to an external command C from an external device.
Enter the OM. In the present embodiment, the external command COM is composed of a chip select signal / CS, a column address strobe signal / CAS, a write enable signal / WE and a row address strobe signal / RAS. Then, the command decoder 12 responds to the internal clock signal CLK1 at that time by the external command COM,
That is, various commands such as a write command, a read command, and a refresh command are decoded from the state (H level or L level) of each signal / CAS, / WE, / CS, / RAS. Then, the command decoder 12 uses the various commands decoded from the external command COM as an internal command and an enable signal and the like, the address buffer 13, the input / output buffer 14, the control signal latch 15,
It outputs to the mode register 16 and the I / O control circuit 18.

The address buffer 13 has a buffer function and a latch function, and based on an internal command from the command decoder 12, an address signal A0-A from an external device is sent.
10 and bank address signals BA0 and BA1 are input.
The address buffer 13 receives the input address signals A0 to A0.
A10 and bank address signals BA0 and BA1 are amplified, address data based on them are latched, and are output to the control signal latch 15, the mode register 16 and the address generation circuit 17.

The input / output buffer 14 is activated based on the enable signal from the command decoder 12, and receives write data DQ0 to DQ31 and a mask control signal DQM from an external device. The input / output buffer 14 is responsive to the internal clock signal CLK1 to write data DQ0 to DQ.
31 is output to the I / O control circuit 18. Further, the input / output buffer 14 responds to the internal clock signal CLK1 with the I
Read data DQ0 to DQ31 from the / O control circuit 18
To an external device. Further, the input / output buffer 14 is
Write data DQ0 to DQ0 in response to the mask control signal DQM
Mask DQ31.

The control signal latch 15 inputs the internal command from the command decoder 12 and the address data from the address buffer 13. Then, the control signal latch 15 outputs control signals for various processing operations such as write data write, read data read, refresh, and self refresh to the DRAM core 19 based on these internal commands and address data. To do.

The mode register 16 inputs the internal command (mode register set command) from the command decoder 12 and the address data from the address buffer 13. Then, the mode register 16 determines the DRAM core 1 based on these internal commands and address data.
9 holds the mode of various processing operations to be carried out for 9. Then, the mode register 16 outputs a control signal based on the held mode information.

The mode information held by the mode register 16 includes access form information. The access form information is information indicating the logical address map shape of the DRAM core 19. The mode register 16 outputs an address configuration selection signal generated based on the access form information to the address generation circuit 17.

The address generating circuit 17 inputs address data based on the address signals A0 to A10 from the address buffer 13. Then, the address generation circuit 17
Based on the mode of the mode register 16 and the address configuration selection signal, the row address data and the column address data generated corresponding to the logical address map shape of the DRAM core 19 at that time are output to the DRAM core 19. The address generation circuit 17 has a function of automatically generating a column address incremented from an input address based on the burst length set in the mode register 16.

The I / O control circuit 18 controls input or output based on the internal command from the command decoder 12. The I / O control circuit 18 outputs the write data (32 bits) from the input / output buffer 14 to the DRAM core 19 and the read data (32 bits) from the DRAM core 19 to the input / output buffer 14.

The DRAM core 19 is composed of a plurality of (four in this embodiment) banks, and each bank has a control signal from the control signal latch 15 and row address data and column address data from the address generation circuit 17. Respectively. That is, the DRA in the address buffer 13
Bank address signal BA corresponding to the number of banks of the M core
0, BA1 are input, and the control signal latch 15 and the address generation circuit 17 are provided for each bank.

The DRAM core 19 executes various processing operations such as write data write, read data read, refresh, and self-refresh on the built-in memory cell array based on the control signal and the address data. Therefore, the DRAM core 19 writes the write data DQ0 to DQ31 input from the input / output buffer 14 into the memory cell at the predetermined address based on the control signal and the address data.

FIG. 2 is a schematic block diagram of the DRAM core 19. For simplification of description, one bank that constitutes the DRAM core 19 will be described here. DRA
Each bank of the M core 19 includes a memory cell array 21,
The memory cell array 21 is configured by arranging a plurality of memory cells in an array. Each memory cell has a word line W
It is connected to L and a bit line (not shown), and the bit line is connected to the sense amplifier S / A. A column selection line CL is connected to the sense amplifier S / A. That is, in the memory cell array 21, the X expansion direction in which the word line WL is expanded by the X address (row address) and the column selection line CL and the sense amplifier S / A (S / A column) by the Y address (column address). The array is expanded in the Y expansion direction.

The memory cell array 21 has a plurality of row blocks divided in the X development direction and a plurality of column blocks divided in the Y development direction.
k). Here, the row block is a sense amplifier S / A (S) in the X expansion direction of the memory cell array 21.
/ A column). Further, the column block is a region divided in units of sub word lines SWL connected to the word lines WL in the Y expansion direction of the memory cell array 21.

The memory cell array 21 has a function of changing the logical address map shape according to the access form information held by the mode register 16, and this logical address map shape is an address configuration selection signal output from the mode register 16. (In this embodiment, the page
It is changed by the long designation signal).

More specifically, the memory cell array 21 changes the X address and the Y address according to the page length designation signal to change the logical address map shape. When the page length (the depth of the Y address) is changed by the page length designation signal, the sense amplifier S activated in response to the change.
The number of / A is changed. That is, the number of data that can be continuously accessed is changed.

The DRAM core 19 thus constructed
Are address signals A0 to A10 and bank address signals B input from a predetermined number of external address terminals.
Various processing operations such as data writing and reading are executed with respect to the memory cells at predetermined X and Y addresses based on A0 to BA1.

It should be noted that the number of external address terminals is set to the larger one of the number of terminals required for fetching the X address and the number of terminals required for fetching the Y address. Specifically, in the memory device 10 in which the X address is set to M bits and the Y address is set to N bits, for example, when M> N, the number of external address terminals is set to M. That is, the memory device (SDRAM) 10 of the present embodiment is provided with 13 external address terminals for taking in a maximum of 13-bit X address (including row address and bank address).

FIG. 3 is a block diagram illustrating a method of controlling the memory device 10. In the following description, the number of external address terminals is M, and the X address when the page length is set to the maximum value (hereinafter, full page) by the page length designation signal is M bits (XA <0: m>, (m = M-1)) and the Y address is N bits (YA <0: n>, (n = N-1)) (where M> N). Although the address buffer 13 (see FIG. 1) is functionally divided into the first to third address buffers 13a to 13c in FIG. 1 for convenience of description, the address buffer 13 may be configured without division.

Now, it is assumed that a page length shorter than the full page is set based on the page length designation signal from the mode register 16 and the X address increased by the page length designation signal is i bits. At this time, the Y address is reduced by i bits. This is because the substantial capacity (2 ^{M + N} ) × I / O count of the memory cell array 21 does not change. Then, the increased i-bit X address is fetched from i of the (M−N + i) external address terminals which are not needed at the time of fetching the Y address.

More specifically, the first address buffer 13a
Is an internal command from the command decoder 12 (in the figure,
Address signal A based on the row address capture signal)
Enter 0-Am. The first address buffer 13a is
The input address signals A0-Am are amplified, and X address data based on them are latched and output to the address generation circuit 17.

The second address buffer 13b has an internal command (Column Addre in the figure) from the command decoder 12.
address signals A0-A (n
-Enter i). The second address buffer 13b amplifies the input address signals A0 to A (n-i), latches Y address data based on them, and outputs them to the address generation circuit 17.

The third address buffer 13c has an internal command (Column Addre in the figure) from the command decoder 12.
address signal A (n-i +)
1) -An is input. Third address buffer 13b
Amplifies the input address signals A (n-i + 1) to An, latches X address data or Y address data based on them, and outputs them to the address generation circuit 17.

The address generation circuit 17 includes first to third decoders (selection circuits in the figure) 17a to 17c, a clamp circuit 17d, and a switch circuit 17e. First to third
The decoders 17a to 17c, based on the address data from the first to third address buffers 13a to 13c, bank (BANK), row block (Row Block), word line W
L, column block (column block), column select line CL
Is appropriately selected according to the function of each decoder. The clamp circuit 17d invalidates any input address data and changes the decoding compression rate. For the sake of convenience of description, in the present embodiment, the address generation circuit 17 is functionally divided into the first to third decoders 17a to 17c, but may be configured not to be divided.

The first decoder 17a will be described in detail below.
Selects a bank, a row block, and a word line WL based on the X address data output from the first address buffer 13a, and DRs the X address corresponding to them.
Output to the AM core 19.

The second decoder 17b selects the column selection line CL based on the Y address data output from the second address buffer 13b, and outputs the corresponding Y address to the DRAM core 19.

Here, when the page length designating signal designates a page length shorter than the full page, the page length designating signal switches the switch circuit 17e to a predetermined connection position, and the third address buffer 13c becomes the third page. It is connected to the decoder 17c.

As a result, the third decoder 17c operates as the third decoder 17c.
Based on the X address data output from the address buffer 13c, the column block (specifically, the word line W
L) is selected and the corresponding X address is output to the DRAM core 19. That is, the i-bit X address increased by the page length designation signal is taken in from i of the (M−N + i) external address terminals which are not needed at the time of taking in the Y address. At this time, the switch circuit 17e connects the second decoder 17b to the clamp circuit 17d. As a result, the clamp circuit 17d
Invalidates unnecessary Y addresses when fetching Y addresses.

When the full page is designated by the page length designation signal, the third address buffer 13c is connected to the second decoder 17b. As a result, the second decoder 17b selects the column selection line CL based on the Y address data output from the third address buffer 13c, and outputs the corresponding Y address to the DRAM core 19.
Output to. At this time, the clamp circuit 17d
It is connected to the third decoder 17c and invalidates an unnecessary X address when the Y address is fetched.

For comparison, FIG. 33 shows a block diagram for explaining a conventional method of controlling a memory device. Conventionally, the address buffer 51 for fetching the X address
And an address buffer 52 for fetching the Y address
Are provided respectively. When using a short page length, the number (M or N) of external address terminals is increased according to the increased number of bits of the X address or Y address at that time.

FIG. 7 shows the memory device 10 of this embodiment.
5 is a waveform diagram showing the internal operation of FIG. Here, as an example, an operation waveform diagram of a 64 Mbit (megabit) SDRAM (32 I / O) is shown.

Now, in the initial state, the memory device 1
0 is a 13-bit X address (row address RA <0:10
>, Bank address BA <0: 1>), 8-bit Y address (column address CA <0: 7>), and the page length is set to 256 (full page). .

The memory device 10 responds to the mode register set command MRS with address signals A0-A.
10 is taken in as the address code Code (CodeA <0:10>), and the bank address Bank (BA <0: 1>) is taken in. Then, the memory device 10 determines the page length Pa based on the address code Code (CodeA <0:10>).
various settings such as ge, cast latency tCL, and burst length BL.

Now, the cast latency tCL = 3, the burst length BL = 2, and the page length Page = 32.
At this time, the memory device 10 uses the 16-bit X address (row address RA <0:13>, bank address BA <0: 1>
) 5-bit Y address (column address CA <0: 4>
) Of the logical address map shape. That is, the row address is increased by 3 bits as the page length is changed.

The memory device 10 takes in the address signals A0 to A10 as the row address Row (RA <0:10>) and takes in the bank address Bank (BA <0: 1>) in response to the active command ACT. Note that the fetching of the bank address is the same hereafter, and is therefore omitted.

The mode register set command MRS
The page length (= 32) set at the time of input may be set at the time of input of this active command ACT.
In this case, the number of row addresses to be fetched is reduced by the number of bits required to set the page length. For example, if 2 bits are required to set the page length, the memory device 10
The address signals A0 to A8 are set to the row address Row (RA <0: 8>
) And the address signals A9 and A10 as setting information. Alternatively, it may be fetched from another pin (DQ mask pin or the like) that is not used when the active command ACT is input.

Then, the memory device 10 responds to the read command RD1 input after a predetermined clock (for example, two clocks) after the input of the active command ACT, and outputs the address signals A0 to A5 to the column address Col (Col (C
The address signals A6 to A8 are taken in as the row address Row (RA <11:13>) as A <0: 4>).

That is, the 3-bit row address Row which increases with the page length variable is fetched from the external address terminal which is not required when the column address Col (CA <0: 4>) is fetched when the read command RD1 is inputted. Be done. Then, the memory device 10 selects the column block and the word line WL based on the row address Row (RA <11:13>), and activates the selected word line WL and the sense amplifier S / A corresponding thereto. Let

In response to the active command ACT, the address signals A0 to A10 are transferred to the row address Row (RA <3:
13>) and address signals A6 to A8 in response to the read command RD1 to the row address Row (RA <0: 2>
). Further, the address signals A6 to A8 may be taken in at arbitrary bit positions of the row address Row in response to the read command RD1.

The memory device 10 sends the read command R
When D1 is issued, the set cast latency tC
Based on L (= 3) and burst length BL (= 2), read data D11 and D12 are sequentially output 3 clocks after the read command RD1 is input.

After that, the memory device 10 sequentially responds to the read commands RD2 and RD3 and outputs the column address Col (CA <0: 4>) and the bank address Bank (BA <0: 1.
>). At this time, in the second and subsequent read commands RD2 and RD3, the increased row address Row is not captured, and only the column address Col (CA <0: 4>) and the bank address Bank (BA <0: 1>) are captured.

In this embodiment, the read command RD
1 to RD3 have been described, the same applies to the case of a write command. That is, the active command AC
The increased row address Row (RA <11:13>) is taken in by the first write command after T input. And 2
In the write command after the first time, the column address Col
Only (CA <0: 4>) and bank address Bank (BA <0: 1>) are fetched.

For comparison, waveform diagrams showing the internal operation of the conventional memory device are shown in FIGS. 34 and 35. Figure 3
FIG. 4 is an operation waveform diagram of the 64 Mbit (megabit) SDRAM when the page length Page is set to 256 (full page). As shown in the figure, after the mode register set command MRS is input, the memory device
Row address R in response to active command ACT
ow (RA <0:10>) is taken in. Then, the memory device sequentially responds to the read commands RD1 to RD3 and fetches the column address Col (CA <0: 7>).

FIG. 35 is an operation waveform diagram of a 64 Mbit (Megabit) SDRAM in which the page length Page is set to 32. As shown in the figure, when a short page length (= 32) is used, the row address Row increases by 3 bits. That is, the memory device uses the active command A
Address signals A0 to A10 are fetched as row address Row (RA <0:10>) in response to CT, and address signal A1
Row address Row (RA <11:13>) with 3 to A15 increased
Take in as. Therefore, conventionally, a short page length (=
In the memory device set to 32), the number of external address terminals for taking in the increased 3-bit row address Row increases compared to the standard product.

FIG. 8 is a block diagram for explaining access control after issuing the active command ACT in FIG. In the figure, the same components as those in FIG. 3 are designated by the same reference numerals, and detailed description thereof will be partially omitted.

The command decoder 12 (see FIG. 1) includes a command judging circuit (Command judging circuit in the drawing) 12a,
First page command detection circuit (Pa in the figure) for detecting the first activation signal output from the command determination circuit 12a.
ge Command first detection circuit) (hereinafter, command detection circuit) 12b is included. In this embodiment, the activation signal is a signal that activates the word line WL and the sense amplifier S / A.

The command determination circuit 12a determines a read command and a write command among various commands decoded in response to the internal clock signal CLK1 and outputs a read activation signal or a write activation signal according to the determination.

Now, when the read command RD1 shown in FIG. 7 is input, the command determination circuit 12a outputs a read activation signal. The second address buffer 13b (Address Latch in the figure) includes an OR circuit 31 and a delay circuit 3.
The address signals A0 to A4 are input based on the read activation signal (read command RD1) input via 2. Then, the second address buffer 13b converts the column address data based on the address signals A0 to A4 into the second decoder 17b (Column Address Decoder in the figure).
Output to.

Third address buffer 13c (in the figure, Addr
ess Latch) receives the command detection circuit 12 by the first read activation signal (read command RD1) input to the command detection circuit 12b via the OR circuit 31.
Address signal A5 based on the detection signal output from b
-Enter A7. Then, the third address buffer 13
c is a third decoder 17c (in the figure, Column Block) that outputs the row address data based on the address signals A5 to A7.
Output to the selection Address Decoder).

The second decoder 17b selects the column selection line CL based on the column address data output from the second address buffer 13b. Third decoder 17c
Are column blocks and word lines WL based on the row address data output from the third address buffer 13c.
Select. As a result, the word line WL and the sense amplifier S / A are activated.

In this way, the command detection circuit 12b
Detects only the first read activation signal (read command RD1) output from the command determination circuit 12a, and based on the detection signal from the command detection circuit 12b, the expanded row address Row (RA <11 : 13>) is held in the third decoder 17c.

Then, the second read activation signal (see FIG.
The read command RD2) shown in FIG.
No detection signal is output from 2b. That is, in the read commands RD2 and RD3 issued after the second time, the address signals A5 to A7 are not taken into the third address buffer 13c.

13 and 14 are circuit diagrams showing an example of the specific circuit configuration of FIG. 8 described above. Moreover, FIG.
FIG. 5 is a waveform diagram showing an example of the internal operation of the circuits shown in FIGS. 13 and 14.

For comparison, a block diagram for explaining conventional access control is shown in FIG. Since this figure explains the principle of conventional access control, the same reference numerals are given to the components having the same functions. As shown in FIG. 36, since the page length is 256 in the related art,
The column address Col (CA <0: 4>) and the column address Col (CA <5: 7>) are fetched each time a read or write activation signal (that is, a read or write command) is output.

FIG. 9 is a block diagram for explaining a case where the access control described in FIG. 8 is performed according to the page length. In this configuration, the connection position of each of the switch circuits 33a and 33b is switched based on the page length designation signal, so that the address signals latched by the second and third address buffers 13b and 13c are appropriately changed according to the page length. be able to. Accordingly, the second and third decoders 1
7b and 17c are DRAMs according to the page length.
The row address and the column address generated corresponding to the logical address map shape of the core 19 are output to the DRAM core 19.

FIG. 10 is a schematic block diagram illustrating activation control of word line WL and sense amplifier S / A.
As shown in the figure, the word line activation circuit 41 and the sense amplifier activation circuit 42 respond to the output signal of either the command determination circuit 12a or the command detection circuit 12b input according to the page length designation signal. Word line WL,
Each sense amplifier S / A is activated.

More specifically, when the page length Page is set to the full page by the page length designation signal, each activation circuit 41, 42 responds to the active signal (active command) from the command determination circuit 12a. W
L and the sense amplifier S / A are activated respectively. This is because all the bits of the row address necessary for selecting the word line WL and the sense amplifier S / A are aligned when the active command is received.

On the other hand, the page length P is given by the page length designation signal.
When the page length is set to be shorter than the full page, each activation circuit 41, 42 responds to the detection signal from the detection circuit 12a, that is, the read or write activation signal (read or write command), to write the word. The line WL and the sense amplifier S / A are activated respectively. This is because a row address accepted by the active command and a row address accepted by the page command are required to select the word line WL and the sense amplifier S / A to be activated.

For comparison, FIG. 37 shows a block diagram for explaining a conventional control method of the activation circuit. Since this figure illustrates the principle of conventional activation control, the same reference numerals are given to components having the same function. As shown in FIG. 37, conventionally, each activation circuit 41, 42 is
Activates the word line WL and the sense amplifier S / A only by the active signal from the command determination circuit 12a.

As described above, according to this embodiment, the following effects can be obtained. (1) The memory device 10 responds to the page length designation signal output from the mode register 16 in accordance with the DRAM core 1
9 changes the logical address map shape. When the page length is set shorter than that of the full page, the row address Row thus increased is fetched when the first read command RD1 is input. In this way, the increasing row address Row is fetched in a time division manner by using the external address terminals which are not used at that time,
The page length can be changed without changing the number and arrangement of external address terminals, and a general-purpose package can be used. Therefore, it is possible to prevent the development period from increasing and the cost from increasing.

(2) Since the page length can be changed without changing the package, an efficient access method according to the system of the customer who uses the memory device can be realized.

(3) Since the page length can be shortened without changing the package, the activation number of the sense amplifier S / A can be reduced to the necessary minimum, and the current consumption can be reduced. Can be realized.

(Second Embodiment) A second embodiment of the present invention will be described below. In the present embodiment, when the page length is similarly changed from 256 to 32 using the memory device 10 of the first embodiment, another control method of the row address fetching method that increases with the page length change. To explain. Therefore, the same name is assigned to the same component, and the detailed description thereof is partially omitted.

FIG. 18 is a waveform diagram showing the internal operation of the second embodiment. In the present embodiment, as shown in FIG.
The read command RD1 is input one clock after the active command ACT. That is, the first read command RD1 after the active command ACT is input.
Is set to tRCD = 1, and the read command RD1 is input one clock earlier than in the first embodiment. (By the way, in the first embodiment, tRCD = 2 (see FIG. 7).) Therefore, the row address Row (RA <11:13>) that increases with the page length change (change from 256 to 32) is executed in the first embodiment. It is taken in by one clock earlier than the form, and thereby the word line WL and the sense amplifier S / A corresponding thereto are activated almost one clock earlier.

By the way, generally, in order to completely complete the activation operation of the word line WL, it is necessary to delay (wait) from the input of the active command ACT to the start of the access operation by the input of the read command RD1. This grace period varies depending on the frequency of the clock signal, but normally 2 clocks are required at the general clock frequency of the device currently used. Therefore, it is necessary to delay the start timing of the access operation based on the read command RD1 by substantially one clock from the time when the read command RD1 is input.

On the other hand, the CAS latency tCL defines the period (clock number) from the input of the read command to the output of the read data. Therefore, as shown in FIG. 18, the CAS latency tCL corresponding to the first read command RD1 is a preset value of the CAS latency tCL from tCL = 3 (set value) to tCL = 4.
Is changed to. Therefore, the memory device reads the read data D1 4 clocks after the read command RD1 is issued.
1, D12 are sequentially output.

Thereafter, the memory device responds to the read commands RD2 and RD3 and outputs the column address Col (CA <0:
4>) and the bank address Bank (BA <0: 1>) are sequentially taken in, and the preset latency tCL (tCL = tCL =
3: Read data is sequentially output according to the set value).

At this time, similarly to the above, in the second and subsequent read commands RD2 and RD3, the increased row address Row is not taken in and the column address Col (CA <0: 4
>) And bank address Bank (BA <0: 1>) are taken in. In the present embodiment, the read commands RD1 to R
Although D3 has been described, the same applies to the case of a write command.

FIG. 19 is a block diagram for explaining the control method of the cast latency tCL. In this embodiment, the command decoder 12 (see FIG. 1) includes the command determination circuit 12a, a page command first detection circuit 12b, and a Cas Latency control circuit 12c.

Similarly to the above, the command determination circuit 12a
Determines whether it is a read command or a write command, and outputs a read activation signal or a write activation signal. The command detection circuit 12b is the command determination circuit 12
The first read activation signal or write activation signal output from a is detected, and the detection signal is output to the CAS latency control circuit 12c.

The CAS latency control circuit 12c outputs an output control signal at a predetermined clock number in response to the internal clock signal CLK1 and issues an internal command (read commands RD1 to RD3 in FIG. 18). The time from when the output data is determined to when the output data is determined, that is, the CAS latency tCL is controlled.

Then, the CAS latency control circuit 12c
When the detection signal is output from the command detection circuit 12b, changes the value of the CAS latency tCL at that time in response to the detection signal. In addition, specifically, the CAS latency control circuit 12c of the present embodiment responds to the detection signal from the command detection circuit 12b in response to the CAS latency t.
The value of CL is increased by 1 from a predetermined value (setting value).

That is, in FIG. 18, the cast latency tCL is set to tCL = 3 (set value) by the mode register set command MRS. Next, after issuing the active command ACT, the first read command R
When D1 is input, the CAS latency control circuit 12c
A detection signal output from the command detection circuit 12b is input to the. In response to this detection signal, the CAS latency control circuit 12c causes the value of the CAS latency tCL (t
CL = 3: set value) is changed to tCL = 4. That is, the CAS latency control circuit 12c changes tCL = 4 only when the first read command RD1 is input, and sets tCL = 3 for the second and subsequent read commands RD2 and RD3.

As described above, this embodiment has the following effects. (1) In the present embodiment, the first read command RD1 after the active command ACT is input is input one clock earlier than that in the first embodiment, so that the row address Row that increases as the page length is changed is first input. 1 rather than form
It is captured earlier by the clock. Therefore, the word line WL and the sense amplifier S / A can be activated earlier by almost one clock. At that time, the CAS latency tCL corresponding to the read command RD1 is changed to tCL = 4 by the CAS latency control circuit 12c, thereby activating the word line WL and the sense amplifier S / A and then outputting the read data. The period is sufficiently secured.
This prevents the start timing of the access operation based on the read command RD1 from being delayed when the page length is variable.

(Third Embodiment) The third embodiment of the present invention will be described below. In the present embodiment, when the page length is similarly changed from 256 to 32 using the memory device 10 of the first embodiment, another control method of the row address fetching method that increases with the page length change. To explain. Therefore, the same name is assigned to the same component, and the detailed description thereof is partially omitted.

FIG. 20 is a block diagram for explaining the access control of the third embodiment. In the present embodiment, the command decoder 12 (see FIG. 1) includes the command determination circuit 12a and a predetermined time detection circuit (hereinafter, time detection circuit) 12d.

The detection circuit 12d has an internal clock signal C
LK1, the active signal and the read or write activation signal output from the command determination circuit 12a are input.

That is, the command determination circuit 12a outputs an active signal when the internal command is the active command ACT. In response to the active signal, the time detection circuit 12d outputs an address fetch signal for fetching the increased row address after a predetermined time (hereinafter referred to as address latency tAL) has elapsed.

In the present embodiment, the address latency tAL is set based on the internal clock signal CLK1, and the time detection circuit 12d uses the internal clock signal CLK.
After counting a predetermined number of clocks based on 1, an address fetch signal is output. At this time, the time detection circuit 1
2d outputs the address take-in signal until the command read circuit 12a outputs the first read activation signal or write activation signal.

Now, when the page length is set to 32, the switch circuit 33 is switched to the connection position shown in FIG. 20 by the page length designating signal. Third address buffer 1
3c amplifies the input address signals A0-An based on the address take-in signal from the time detection circuit 12d, latches the row address data based on them, and outputs the row address data to the third decoder 17c. Then, the third decoder 17c
Is a row address (RA <0: n>) for specifying the column block (word line WL) corresponding to the row address data.
To the DRAM core 19 (FIG. 1).

Incidentally, as shown in FIG. 20, the row address (increased row address) fetched based on the detection signal from the time detection circuit 12d is changed to the second and third buffers 13b, 13b based on the page length designation signal. It is taken in by any of 13c. Note that FIG. 22 is a circuit diagram showing an example of a specific circuit configuration of the time detection circuit 12d of FIG.

FIG. 21 is a waveform diagram showing the internal operation of this embodiment. In the same figure, a case where the address latency tAL of the time detection circuit 12d is set to, for example, tAL = 1 will be described.

As shown in FIG. 21, the page length is variable (25
Row address Row increased with the change from 6 to 32)
(RA <0: 4>) is captured by the address capture signal from the time detection circuit 12d one clock after the active command ACT is input. As a result, the column block and the word line WL are selected, and the selected word line WL
And the corresponding sense amplifier S / A is activated.

Thereafter, the memory device 10 sequentially responds to the read commands RD1 to RD3 and outputs the column address C.
ol (CA <0: 4>) and bank address Bank (BA <0: 1>)
Of the preset cast latency (tCL
= 3), the read data is sequentially output according to the burst length (BL = 2). At this time, similarly to the above, in the read commands RD1 to RD3, the increased row address Ro is increased.
The w is not fetched, but only the column address Col (CA <0: 4>) and the bank address Bank (BA <0: 1>) are fetched. In the present embodiment, read commands RD1 to RD
3 has been described, the same applies to the case of a write command.

As described above, this embodiment has the following effects. (1) The command decoder 12 includes the command determination circuit 12
A time detection circuit 12d that outputs an address fetch signal after a predetermined time (address latency tAL) has elapsed in response to the active signal from a is provided. As a result, the row address Row that has increased as the page length is changed is fetched one clock after the active command ACT (tAL = 1). Therefore, similarly to the second embodiment, the word line WL and the sense amplifier S / A can be activated quickly. Further, in the present embodiment, the increased row address Ro
Since w is fetched at a timing earlier than the input of the read command RD1, the fetch is not affected by the arrangement of external address terminals.

(2) The timing of the active command ACT and the read command RD, and the address signal designated at the time of output thereof do not depend on the page length (logical address map shape). That is, the memory controller (CP
U) It only outputs the address signal corresponding to the row address extended between the active command ACT and the read command RD. Therefore, the change is easy, and a new function (function of changing the logical address map shape) can be used without trouble.

(Fourth Embodiment) A fourth embodiment of the present invention will be described below. In this embodiment, the address latency t of the time detection circuit 12d in the third embodiment is used.
The case where AL is set to, for example, tAL = 0.5 will be described.

FIG. 23 is a waveform diagram showing the internal operation of the fourth embodiment. In this embodiment, as shown in FIG.
The row address Row that increases as the page length is changed (changed from 256 to 32) is taken in by an address take-in signal from the time detection circuit 12d 0.5 clocks after the input of the active command.

That is, the memory device 10 takes in the row address Row (RA <0:10>) at the rising edge of the clock signal CLK based on the input of the active command ACT, and clock signal CL after 0.5 clocks.
The row address Row (RA <that increased at the falling edge of K
0: 4>).

As described above, in this embodiment, by setting the address latency tAL = 0.5, the increased row address Row is fetched by 0.5 clock earlier than in the third embodiment, whereby the word line is read. The WL and the corresponding sense amplifier S / A are activated for about 0.5 clocks.

Thereafter, the memory device 10 sequentially responds to the read commands RD1 to RD3 and outputs the column address C.
ol (CA <0: 4>) and bank address Bank (BA <0: 1>)
Of the preset cast latency (tCL
= 3), the read data is sequentially output based on the burst length (BL = 2). At this time, similarly to the above, in the read commands RD1 to RD3, the increased row address R
ow is not taken in, column address Col (CA <0: 4>)
And only the bank address Bank (BA <0: 1>) is fetched. In the present embodiment, read commands RD1 to RD
3 has been described, the same applies to the case of a write command.

As described above, according to this embodiment, the following effects can be obtained. (1) In this embodiment, the address latency tAL is
Since tAL = 0.5 is set, the row address Row increased as the page length is changed is changed to the active command A
Captured 0.5 clocks after CT. Therefore, the word line WL and the sense amplifier S / A can be activated by about 0.5 clock earlier than in the third embodiment.
This prevents the start timing of the access operation based on the read command RD1 from being delayed when the page length is variable.

The above embodiments may be implemented in the following modes. In each of the above embodiments, the number of bits of the memory cell, the address configuration, the switching type of the address configuration, etc. are not limited to this example.

In FIG. 3, the clamp circuit 17d is
Although it is provided in the address generation circuit 17, it may be provided separately. The configuration of FIG. 3 may be modified as shown in FIG. That is, dedicated address buffers 13f and 13g for fetching the Y address and the X address based on the address signals A (n-i + 1) to An may be provided, respectively.

The configuration of FIG. 3 may be modified as shown in FIG. That is, each of the address buffers 13h to 13j
Are configured to share an address buffer for fetching the X address or the Y address, respectively. Then, those output signals (X address data or Y address data) may be appropriately selected by the XY switching signal.

The configuration of FIG. 3 may be modified as shown in FIG. That is, as in FIG. 5, each address buffer 1
3k, 13l, and 13n are configured to share an address buffer for fetching an X address or a Y address, respectively, and an address (X
Address buffer 13 for fetching only (address)
You may make it provide m separately.

The command determination circuit 12a and the command detection circuit 12b shown in FIG. 8 may be replaced with another configuration which does not depend on the clock signal CLK1 when the memory device is an asynchronous type.

In FIG. 10, the sense amplifier (S /
A) Only the activation circuit 42 may be controlled. The configuration of FIG. 8 may be modified as shown in FIG.
That is, the third address buffer 13c fetches the address signals A5 to A7 every time for each read / write activation signal (that is, read / write command) from the command determination circuit 12a. Then, based on the detection signal from the command detection circuit 12b, the third decoder 17c causes the third address buffer 1 to perform the read / write command after the second time.
The row address data from 3c may not be re-latched. 16 and 17 are circuit diagrams showing an example of the specific circuit configuration of FIG.

Further, FIG. 12 shows a case where the address control performed by the configuration of FIG. 11 is performed according to the page length. In this configuration, the connection positions of the switch circuits 33a and 33b are switched by the page length designation signal, so that the row address and the column address generated corresponding to the logical address map shape of the DRAM core 19 at each time according to the page length. Is the second and third decoders 17b, 1
7c respectively outputs.

In the first and second embodiments, the address increased as the page length is changed is changed to the active command ACT.
The Y address is fetched at the same time as the Y address fetched by the first read / write command after input, but the present invention is not limited to this example. That is, the increased address is read / read first
After being fetched by the write command, the Y address may be fetched after a predetermined clock (for example, one clock) of the command.

In the third and fourth embodiments, the time detection circuit 12d outputs the detection signal after a predetermined clock in response to the active signal, but when embodying it in an asynchronous memory device, , Internal clock signal CL
The detection signal may be output after a predetermined time (tAL) has elapsed regardless of K1.

A double data rate (DDR) method is used as another means for realizing the method of fetching the row address Row increased at the address latency tAL = 0.5 as in the fourth embodiment. You may embody it. That is, the clock signals CLK, / CL
Using two clock signals represented by K (/ is a bar), a row address is fetched at the rising edge of the clock signal CLK, and a clock signal / C having a 180 ° phase difference immediately after that is fetched.
The row address increased at the rising edge of LK may be fetched.

In each of the above embodiments, the page length is specified when the mode register set command MRS is input or when one type of active command ACT is input. However, two types of active commands ACT are used to specify the page length. The page length may be designated based on the input of ACT.

In each of the above-mentioned embodiments, the synchronous memory device is embodied, but an asynchronous memory may be configured so that the logical address map shape can be changed. Since the schematic configuration of the asynchronous memory is already known, the drawing and description thereof are omitted.

This memory device determines the address signal ADD as the X address (row address) at the fall of the chip enable signal (/ CE) or the row address strobe signal (/ RAS). Next, the memory device determines the address signal as a Y address (column address) by a read or write control signal,
The cell specified by those addresses is accessed.

The change of the logical address map shape is performed by the following illegal entry method (a control method from the outside which is not normally used in the access from the outside). In the illegal entry method, the address configuration select signal inside the memory device is generated earlier than the word line activation signal from the chip enable signal / CE, as in the case of using the mode register set command in the synchronous method (MRS method). To do. As a result, access delay can be prevented without delaying the switching operation of the address generation circuit or its output.

The illegal entry method will be described in detail. FIG. 24 is a waveform diagram illustrating a mode setting cycle for address configuration. The memory device has a dedicated terminal for mode setting for address configuration, and by fetching the necessary information from the dedicated terminal to the information for determining each type of address configuration, it is possible to prevent external access delay and prevent malfunction. The safe operation of normal operation can be guaranteed.

That is, the memory device does not operate normally when the chip enable signal / CE1 is at the H level. During this period, the address code Code based on the address signal ADD is fetched in response to the program mode signal / PE (= address configuration setting terminal) input from the dedicated terminal. Specifically, the memory device activates the input of the address code at the falling edge of the program mode signal / PE, and latches the address code information at the rising edge of the signal / PE.

On the other hand, when the chip enable signal / CE1 is at the L level, the memory device enters the operation state corresponding to the external access and fetches the address signal ADD corresponding to the external access.

In the figure, t1 to t5 are external specification timing conditions. At the timing shown in the figure, the input circuit of the external dedicated terminal is activated at the fall of the program mode signal / PE to start the decoding operation for the address signal. Then, the decoding result is determined at the rising edge of the program mode signal / PE, and the input circuit is deactivated. By this operation, power consumption can be reduced.

In the mode setting cycle for the above address configuration, the logic of the program mode signal / PE may be inverted. The address code may be input from a data terminal (called a DQ or I / O pin).

Further, as will be described later, the mode may be determined after the program cycle by the code method is repeated several times. FIG. 25 is an explanatory diagram of commands.

When using this command, a memory device of a specification system which recognizes a command with respect to a reference clock (system clock CLK or chip enable signal / CE1) and performs an external access operation is targeted.

Therefore, in the memory device of the specification system which does not operate by the command with respect to the chip enable signal / CE1, the address is simply used as information for determining each kind of address configuration based on FIG. It can be used as the number of times

Commands (1) to (6), (8) to (1
0) is a command used in normal operation, and commands (7) and (11) are commands that have no meaning in normal operation. The command (7) is a write (WR) operation but does not input data (masked) because the signals / LB and / UB are at the H level. Command (11)
Is a read (RD) operation, but similarly the signal / LB,
No data is output because it is masked by / IB.

As described above, by fetching a command (illegal command) not used for normal operation as information for determining each type of address configuration, it is possible to set information without providing a dedicated terminal.

FIG. 26 is a waveform diagram for explaining the mode setting cycle for address configuration. By continuously inputting a plurality of commands (11) shown in FIG. 25, information necessary for mode setting for address configuration is shown. Shows the case where is taken in as an address code.

The memory device takes in the address signal ADD as the address code Code in response to the command (11). This operation is repeated N times. N from the first time
When all the N address codes Code fetched corresponding to the command (11) up to the first match, the address code Code is validated and the mode setting for the address configuration is performed.

The command (11) is N? When they match once, mode setting for address configuration may be performed based on the address code Code fetched corresponding to the Nth command (11). Further, the fetching of the address code Code is performed in an arbitrary cycle (for example, 1
It may be changed to the first time). Various other applications can be developed.

As the address code for setting the mode, the number of address Bits may be determined corresponding to the number of types of address configuration. In the case of N mode setting cycles as shown in FIG. 26, a counter circuit is used inside the device. When the upper bits of the counter circuit change for N number of mode setting cycle entries, the circuit configuration is such that the mode is determined.

FIG. 27 is an operation waveform diagram of an entry control circuit which is a mode setting circuit for program address configuration. As shown in FIG. 27A, the first entry circuit outputs the H-level first address enable signal proaddz in the third cycle, and outputs the first entry signal proentz in the fourth cycle. Then, the first entry circuit uses the first address enable signal proa.
Reset ddz and the first entry signal proentz at the same time. As a result, the memory device sends the previously determined address configuration information to the 4th by the first entry signal proentz.
The information of the latest address configuration is changed according to the address code information fetched in the second cycle.

As shown in FIG. 27 (b), the first entry circuit causes the other commands (device activation active command and read / write command) during counting.
When is accepted, the count is reset. As a result, the first address enable signal proaddz and the enable signal proaddz are held at the L level.

That is, in the mode setting for determining each type of address configuration, if the same command for that purpose does not continue for the specified number of times, it is canceled. (The memory device maintains the previously determined address configuration information) FIG. 28 is an operation waveform diagram of the entry control circuit (second entry circuit) which is the mode setting circuit for the program address configuration corresponding to FIG. is there.

The second entry circuit outputs the H-level address enable signal peaddz in response to the L-level program mode signal / PE, and then responds to the H-level program mode signal / PE in the H-level enable signal.
Output peaddz. As a result, the memory device transmits the information of the previously determined address configuration to the second entry signal proe.
It is changed to the latest address configuration information according to the address code information imported by ntz.

FIG. 29 is an operation waveform diagram of the entry signal generating circuit. As shown in FIG. 29A, the signal generation circuit responds to the first entry signal proentz by generating the combined signal en.
Output tz. Further, as shown in FIG. 29 (b), the signal generation circuit responds to the entry signal peentz by combining signal en
Output tz.

FIG. 30 is an operation waveform diagram of the mode setting address buffer for address configuration. The address buffer activates the input circuit in response to the H-level address enable signal peaddz and outputs the address signal az <0: 3>. The same operation is performed in response to the first address enable signal proaddz.

FIG. 31 is an operation waveform diagram of the mode setting address latch for address configuration. The address latch uses the address setting az <0: 3> output in response to the H level address enable signal peaddz and latches the code Code latched in response to the combined signal entz for setting the mode. Output as <0: 3>.
The same operation is performed in response to the first address enable signal proaddz.

The mode setting decoder for address configuration uses the mode setting address signal paz <for address configuration.
0: 3> is decoded and an address configuration select signal for several types of address maps is output.

FIG. 32 is an operation waveform diagram of the mode setting decoder. The decoder uses the mode setting address signal pa
Decode z <0: 3> to select one of the address configuration select signals for several types of address maps and bring it to H level.

When the depth of the X address is smaller than the depth of the Y address, the address configuration setting terminal can be shared by the address terminals which are not used when active.
The command for setting the address configuration can be a precharge command or another new command in addition to the active command.

The function of changing the address map is independently realized for each bank. System performance is further improved by setting (changing) the logical address map for each bank.

The position of the address bit to be clamped may be changed appropriately. -The position of the address bit to be invalidated may be changed appropriately. In each of the above embodiments, the logical address map shape can be changed from outside at any time, but a ROM such as bonding or Fuse is provided, and the logical address map shape is changed to a desired shape at the time of shipment or user use,
You may make it maintain the shape. Also, a ROM that can be rewritten from the outside may be provided, and the logical address map shape may be changed as necessary. In these cases, the logical address map shape is fixed for a short period or a long period. Therefore, the existing program and CPU can be used. Further, it is possible to save the trouble of changing the logical address map shape for each row access cycle.

The features of this embodiment are summarized as follows. (Supplementary note 1) M-bit first address and N-bit second
An address terminal for taking in an address at the same time is provided, or an address terminal having a larger number of M-bit first address and N-bit second address is provided, and memory cells are arrayed at the first address and the second address. In a storage device accessing an arrayed memory cell array, a part of an external address input from the address terminal is set to a first address or a second address based on access form information for changing a logical address map shape of the memory cell array. A storage device comprising address replacement means for replacement. (Supplementary Note 2) M-bit first address and N-bit second
An address terminal for taking in an address at the same time is provided, or an address terminal having a larger number of M-bit first address and N-bit second address is provided, and memory cells are arrayed at the first address and the second address. In a storage device that accesses arranged memory cell arrays, an address invalidating unit that invalidates an external address or a part thereof input from the address terminal based on access form information that changes a logical address map shape of the memory cell array. A storage device comprising: (Supplementary Note 3) A predetermined time detecting means is provided for outputting a control signal for fetching an i-bit increasing address that increases in accordance with the change of the logical address map shape, after a lapse of a predetermined time after the first address fetch. 3. The storage device according to appendix 1 or 2, characterized in that. (Supplementary note 4) The storage device according to supplementary note 3, wherein the predetermined time detection unit outputs the control signal after a predetermined clock of a clock signal in response to an active command for fetching the first address. (Supplementary Note 5) A control signal for fetching an i-bit increasing address that increases according to the change of the logical address map shape is generated based on a command issued at the time of the (N-i) -bit second address fetch control. 3. The storage device according to appendix 1 or 2, further comprising a command detection unit for outputting. (Additional remark 6) The command detection unit detects the first read or write command after the active command for fetching the first address, and outputs the control signal based on the read or write command. 5. The storage device according to item 5. (Supplementary Note 7) The storage device according to Supplementary Note 6, further comprising a cast latency control unit that delays the cast latency corresponding to the first read or write command based on a control signal from the command detection circuit. (Supplementary note 8) The storage device according to any one of supplementary notes 3 to 6, further comprising a word line activation unit that activates a word line based on a control signal for fetching the increased address of i bits. (Supplementary note 9) The supplementary note 3 is characterized in that it further comprises a sense amplifier activating means for activating the sense amplifier based on a control signal for fetching the i-bit increased address.
7. The storage device according to any one of items 6 to 6. (Supplementary note 10) The storage device according to supplementary note 2, wherein the address invalidating unit includes a unit that clamps an arbitrary address in order to vary a compression rate of decoding. (Supplementary Note 11) A control signal to which the access form information is applied, or a combination of a plurality of control signals, is provided, which is provided with a unit for generating an address configuration selection signal according to the setting of the logical address map shape, and the address control unit or the Note 1 that the address invalidating means executes the replacement or the invalidation based on the address configuration selection signal.
Alternatively, the storage device according to item 2. (Supplementary Note 12) An external address is input, and based on the address configuration selection signal, an output signal thereof is converted into a first signal generation circuit for generating a selection signal in the first address direction and a selection signal in the second address direction. 12. The storage device according to appendix 11, further comprising an address generation circuit having a switching circuit for switching to a second signal generation circuit for generation. (Supplementary note 13) The storage device according to Supplementary note 1 or 2, wherein the address control unit or the address invalidation unit includes a ROM such as a bonding or a Fuse that stores the access form information. (Supplementary Note 14) The storage device according to Supplementary Note 1 or 2, wherein the address control unit or the address invalidation unit includes an externally rewritable ROM that stores the access form information. (Supplementary Note 15) Is there an address terminal for simultaneously capturing an M-bit first address and an N-bit second address?
Alternatively, a memory device having an address terminal having a larger number of M-bit first address and N-bit second address, and accessing a memory cell array in which memory cells are arrayed at the first address and the second address In the internal control method, wherein a part of the external address input from the address terminal is replaced with a first address or a second address based on access form information for changing a logical address map shape of the memory cell array. Internal control method for storage device. (Supplementary Note 16) Is there an address terminal for simultaneously taking in an M-bit first address and an N-bit second address?
Alternatively, a memory device having an address terminal having a larger number of M-bit first address and N-bit second address, and accessing a memory cell array in which memory cells are arrayed at the first address and the second address The internal control method according to claim 1, wherein the external address input from the address terminal or a part thereof is invalidated based on access form information for changing the logical address map shape of the memory cell array. Internal control method. (Supplementary Note 17) The internal control method for a storage device according to Supplementary Note 15 or 16, wherein the access mode information is set to be set during a standby period or at the same time as an active operation. (Supplementary note 18) The internal control method in the storage device according to any one of supplementary notes 15 to 17, wherein the number of activated sense amplifiers is controlled according to the shape of the logical address map. (Supplementary Note 19) Supplementary note 15 characterized in that the compression rate of decoding is varied according to the shape of the logical address map.
19. An internal control method in the storage device according to any one of 18 to 18. (Supplementary Note 20) An address configuration selection signal according to the setting of the logical address map shape is generated by a control signal to which the access form information is applied, or a combination of a plurality of control signals, and the address configuration selection signal is generated based on the address configuration selection signal. 19. The internal control method for a storage device according to any one of appendices 15 to 18, characterized in that the replacement or the invalidation is executed. (Supplementary note 21) The internal of the storage device according to supplementary note 20, wherein the first and second addresses are generated by a common address generating means, and an output destination of the common address generating means is switched by the address configuration selection signal. Control method. (Additional remark 22) The first and second address generating means for generating the first and second addresses according to an external address are provided, and the input destination of the external address is switched by the address configuration selection signal. An internal control method in the storage device described. (Supplementary note 23) The internal of the storage device according to supplementary note 15 or 16, characterized in that an i-bit increasing address that increases according to a change in the shape of the logical address map is fetched in time division after the first address is fetched. Control method. (Supplementary Note 24) The address latency control is such that after the first address is fetched in synchronization with a clock signal, the i-bit increased address is fetched in synchronization with a predetermined clock of the clock signal. 24. An internal control method in the storage device according to attachment 23. (Supplementary Note 25) The address latency control is based on the i
25. The storage device according to claim 24, further comprising: a step of previously capturing a predetermined number of clocks of the clock signal after capturing the first address so as to generate a control signal for capturing an increased address of bits. Internal control method. (Supplementary note 26) The internal control method in the storage device according to supplementary note 25, wherein the step is performed before or at the time of fetching the first address. (Supplementary Note 27) The supplementary note 25, wherein the step is performed by a command and is set in a mode register.
Or an internal control method in the storage device according to item 26. (Supplementary note 28) The above step is performed with a command including an address code before fetching the first address,
Note 25 or 26, characterized in that the first address is fetched by two types of active commands
An internal control method in the storage device described. (Supplementary note 29) The supplementary note 15 or 16, wherein an i-bit increasing address that increases in accordance with the change of the logical address map shape is performed simultaneously with the fetch control of the (N−i) -bit second address. Internal control method in storage device. (Supplementary note 30) An increased address of i bits that increases according to the change of the logical address map shape is output from an address terminal that is not used when the second address of (Ni) bits is taken out of the N address terminals. The internal control method in the storage device according to appendix 15 or 16, wherein the internal control method is incorporated. (Supplementary note 31) The supplementary note 15 or 16 is characterized in that an i-bit incremented address that increases in accordance with the change of the logical address map shape is performed at the next command after the active command for fetching the first address. Internal control method in storage device. (Supplementary note 32) The internal control method in the storage device according to supplementary note 31, wherein the increased address of i bits is fetched at the same time as the read or write command after the active command. (Supplementary Note 33) A command detecting unit for detecting a first read or write command after the active command is provided, and delaying the CAS latency corresponding to the first read or write command based on an output signal of the command detecting unit is provided. 33. An internal control method in a storage device according to Supplementary Note 32. (Supplementary Note 34) A predetermined time detecting means for outputting a signal for taking in the increased address of the i-bit after a lapse of a predetermined time after taking in the first address is provided, and an output signal of the command detecting means or the predetermined time detecting means is provided. 34. An internal control method in a memory device as set forth in appendix 33, wherein the word line is activated based on the above. (Supplementary note 35) The internal control method in the storage device according to supplementary note 33 or 34, wherein the sense amplifier is activated based on an output signal of the command detecting unit or the predetermined time detecting unit. (Supplementary Note 36) Is there an address terminal for simultaneously taking in an M-bit first address and an N-bit second address?
Alternatively, a storage means is provided which has an address terminal having a larger number of a M-bit first address and an N-bit second address, and which accesses a memory cell array in which memory cells are arrayed at the first address and the second address. And a control means for accessing and controlling the access means, the control means supplies the access form information to the storage means from time to time, and the storage means changes based on the access form information. The system, wherein the increased address of i bits, which increases according to the shape of the logical address map of the memory cell array, is generated in a time division after the generation of the first address. (Supplementary note 37) The system according to supplementary note 36, wherein the control means performs the access form information by using one of an address, a decoder, and code information based on a control signal. (Supplementary note 38) The system according to supplementary note 36 or 37, wherein the control means supplies the access form information at the same time as or before the start of access. (Supplementary note 39) Is there an address terminal for simultaneously taking in an M-bit first address and an N-bit second address?
Alternatively, a storage means is provided which has an address terminal having a larger number of a M-bit first address and an N-bit second address, and which accesses a memory cell array in which memory cells are arrayed at the first address and the second address. And a control method of a storage means in a system including a control means for accessing and controlling the storage means, wherein the control means comprises a logical address of a memory cell array included in the storage means in accordance with access form information at each time. A control method of a storage unit in a system, wherein a map shape is changed, and an i-bit increasing address that increases according to the logical address map shape is controlled to be generated in a time division after generating the first address.

[0168]

As described in detail above, according to the present invention,
It is possible to provide a storage device, an internal control method of the storage device, a system, and a control method of a storage means in the system, which can efficiently access and reduce current consumption without changing the package.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating an outline of an SDRAM.

FIG. 2 is a schematic configuration diagram of a DRAM core.

FIG. 3 is a block diagram illustrating a method of controlling the memory device according to the first embodiment.

FIG. 4 is a block diagram illustrating another control method.

FIG. 5 is a block diagram illustrating another control method.

FIG. 6 is a block diagram illustrating another control method.

FIG. 7 is a waveform diagram showing an internal operation of the memory device of the first embodiment.

FIG. 8 is a block diagram illustrating access control.

FIG. 9 is a block diagram illustrating access control according to page length.

FIG. 10 is a block diagram illustrating a method of controlling the activation circuit.

11 is a block diagram showing another configuration of FIG. 8. FIG.

FIG. 12 is a block diagram illustrating access control according to page length.

FIG. 13 is a circuit diagram showing a specific configuration example of FIG.

FIG. 14 is a circuit diagram showing a specific configuration example of FIG.

FIG. 15 is a waveform diagram showing the internal operation of FIGS. 13 and 14.

16 is a circuit diagram showing a specific configuration example of FIG.

FIG. 17 is a circuit diagram showing a specific configuration example of FIG.

FIG. 18 is a waveform diagram showing the internal operation of the second embodiment.

FIG. 19 is a block diagram illustrating a method of controlling the cast latency.

FIG. 20 is a block diagram illustrating access control according to the third embodiment.

FIG. 21 is a waveform chart showing the internal operation of the third embodiment.

FIG. 22 is a circuit diagram showing a specific configuration example of a predetermined time detection circuit.

FIG. 23 is a waveform chart showing the internal operation of the fourth embodiment.

FIG. 24 is a waveform diagram illustrating a mode setting cycle.

FIG. 25 is an explanatory diagram of commands.

FIG. 26 is a waveform diagram illustrating a mode setting cycle.

FIG. 27 is an operation waveform diagram of the program mode setting circuit.

FIG. 28 is an operation waveform diagram of the program mode setting circuit.

FIG. 29 is an operation waveform diagram of the combined entry signal generation circuit.

FIG. 30 is an operation waveform diagram of a mode setting address buffer.

FIG. 31 is an operation waveform diagram of a mode setting address latch.

FIG. 32 is an operation waveform diagram of the mode setting decoder.

FIG. 33 is a block diagram illustrating a conventional method of controlling a memory device.

FIG. 34 is a waveform diagram showing a conventional internal operation.

FIG. 35 is a waveform chart showing an internal operation when the conventional page length is changed.

FIG. 36 is a block diagram illustrating conventional access control.

FIG. 37 is a block diagram illustrating a control method for a conventional activation circuit.

[Explanation of symbols]

Row X address (row address) as first address Col Y address (column address) as second address 10 Memory device 21 as memory device 21 Memory cell array

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5B060 AB13 AB19                 5M024 AA07 BB07 BB27 BB34 BB35                       BB36 CC99 DD62 DD63 DD80                       DD99 JJ02 JJ32 JJ52 JJ55                       PP01 PP02 PP03 PP07 PP10

Claims (7)

[Claims] 1. An address terminal for simultaneously taking in an M-bit first address and an N-bit second address, or
Alternatively, a memory device having an address terminal having a larger number of M-bit first address and N-bit second address, and accessing a memory cell array in which memory cells are arrayed at the first address and the second address In the first address or the second address, based on access form information for changing the logical address map shape of the memory cell array, part of the external address input from the address terminal is used.
A storage device comprising address control means for substituting an address. 2. An address terminal for simultaneously receiving an M-bit first address and an N-bit second address, or
Alternatively, a memory device having an address terminal having a larger number of M-bit first address and N-bit second address, and accessing a memory cell array in which memory cells are arrayed at the first address and the second address The memory device according to claim 1, further comprising address invalidation means for invalidating an external address input from the address terminal or a part thereof based on access form information for changing a logical address map shape of the memory cell array. . 3. An address terminal for simultaneously receiving an M-bit first address and an N-bit second address, or
Alternatively, a memory device having an address terminal having a larger number of M-bit first address and N-bit second address, and accessing a memory cell array in which memory cells are arrayed at the first address and the second address In the internal control method, wherein a part of the external address input from the address terminal is converted into a first address or a second address based on access form information for changing a logical address map shape of the memory cell array.
An internal control method in a storage device characterized by replacing with an address. 4. An address terminal for simultaneously taking in an M-bit first address and an N-bit second address, or
Alternatively, a memory device having an address terminal having a larger number of M-bit first address and N-bit second address, and accessing a memory cell array in which memory cells are arrayed at the first address and the second address The internal control method according to claim 1, wherein an external address or a part thereof inputted from the address terminal is invalidated based on access form information for changing a logical address map shape of the memory cell array. Internal control method. 5. An address terminal for simultaneously taking in an M-bit first address and an N-bit second address, or
Alternatively, a storage means is provided which has an address terminal having a larger number of a M-bit first address and an N-bit second address, and which accesses a memory cell array in which memory cells are arrayed at the first address and the second address. And a system including control means for accessing and controlling the access means, the control means supplies the access form information at any time to the storage means, and the storage means changes based on the access form information. The system, wherein the increased address of i bits, which increases according to the shape of the logical address map of the memory cell array, is generated in a time division after the generation of the first address. 6. The system according to claim 5, wherein the control means performs the access form information by using one of an address, a decoder, and code information based on a control signal. 7. An address terminal for simultaneously receiving an M-bit first address and an N-bit second address,
Alternatively, a storage means is provided which has an address terminal having a larger number of a M-bit first address and an N-bit second address, and which accesses a memory cell array in which memory cells are arrayed at the first address and the second address. And a control method of a storage unit in a system including a control unit for accessing and controlling the storage unit, wherein the control unit is a logical address of a memory cell array included in the storage unit according to access form information at each time. A control method of a storage unit in a system, wherein a map shape is changed, and an i-bit increasing address that increases according to the logical address map shape is controlled to be generated in a time division after generating the first address.