JP2007200359A - Storage device, address control method and system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a storage device achieving efficient access and reduction in current consumption. <P>SOLUTION: In a memory device 12, a logical address map shape is configured to be changeable. A CPU 11 controls the logical address map shape of the memory device 12 in accordance with an access mode. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  In recent years, semiconductor RAM (Dynamic RAM), which requires data holding operations as needed, has increased storage capacity required by customers (system side), increased access speed (higher operating frequency), I / O bus width The current consumption tends to increase due to the expansion of (the increase in the number of bits for handling data in one access). Along with this, the current consumption of the entire system device equipped with the memory device tends to increase, and the customer is demanded to reduce the power consumption of the memory device.

  In addition, the increase in current consumption described above may lead to an increase in the chip temperature of the memory device. In general, the data retention characteristic (≈ Refresh characteristic: TREF) of a DRAM cell deteriorates at a high temperature (the retention time is shortened). Therefore, reduction of current consumption is also required for this reason.

  Therefore, the semiconductor memory is required to improve performance such as increase in storage capacity, speed up access, and expansion of I / O bus width, and to reduce power consumption.

  The memory device has a memory cell array in which a plurality of memory cells are arranged and a sense amplifier. Each memory cell is connected to a word line and a bit line, and the sense amplifier is connected to the bit line. The sense amplifier is paired with a bit line and amplifies and holds information (read data) of one cell.

The memory cell array is array-developed in the X expansion direction in which word lines are expanded by row addresses and in the Y expansion direction in which bit lines and sense amplifiers are expanded by column addresses. If the memory capacity is 1 Mbit, for example, the logical address of the memory device is 10 bits (2 ¹⁰ = 1024 word lines: WL) X address (Row Address) and 10 bits (2 ¹⁰ = 1024). It can be configured from a Y address (Column Address) of a bit line: BL (1024 sense amplifiers) (note: bit line definition = a pair of complementary bit lines). At this time, if the wiring pitch of the word lines and the bit lines is the same, the logical memory array is imaged as a square.

The internal operation of the memory device will be described using an SDRAM (Synchronous DRAM) that is synchronous with the system clock CLK as an example.
The SDRAM establishes an active / precharge command (chip enable signal / CE (“/” indicates a bar) in an asynchronous memory device) in synchronization with the system clock CLK for activating / deactivating the memory device as a control command. And the read / write command for inputting / outputting data to / from the memory device.

  When an active command is externally applied at the rising edge of the system clock CLK, the X address is taken in and decoded by the X decoder to select one word line and activate it. Each memory cell connected to the selected word line outputs data to each bit line, and each sense amplifier amplifies and holds the data (data latch).

  After that, when a read command is externally applied at the rising edge of the system clock CLK (with a delay of several CLK from the active command), the Y address is fetched and decoded by the Y decoder to store the data held in one sense amplifier. Output outside the device. When a write command is externally applied, the Y address is fetched and decoded by the Y decoder (write data inputted at the time of applying the write command) is written into the memory cell via one sense amplifier. Thereafter, a read / write command is performed as necessary to access the memory cell corresponding to the desired Y address and the outside.

  After the read / write command is completed, the precharge command is applied at the rising edge of the system clock CLK (several CLK delay from the read / write command) to activate the activated word line, sense amplifier, and bit line. Is reset (equalized) to return the memory array to the initial state (in preparation for the next active command).

  The internal operation takes time until the reset operation, and a delay of several CLK is required to apply the next active command from the precharge command. Similarly, a delay of several CLK is required from the active command to the read / write command.

  Here, for simplification of explanation, the case where the number of input / output bits of the memory array is 1 has been described. However, the number of input / output bits is n (denoted as nI / O (ex.4I / O)). In this case, n sense amplifiers are simultaneously activated by the Y address. Each sense amplifier is connected to n I / O ports via n I / O buses.

  The depth of the Y address is called the page length. In response to one active command, the memory device operates at least the number of sense amplifiers of I / O bus width × page length. For example, in the case of an SDRAM in which the Y address is set to 8 bits (YA <0: 7>), the page length is 256. When this SDRAM has a 32-bit I / O bus width, at least 8,192 (= 256 × 32) sense amplifiers operate in response to an active command.

  The SDRAM latches information of a plurality of memory cells connected to a word line selected by an active command in response to a read command that is input as needed in a plurality of sense amplifiers. Therefore, if one word line is activated, the memory cell information for the page length can be appropriately read out. More specifically, information is read from a memory cell at an arbitrary Y address by selecting a sense amplifier at any time by a Y decoder according to a Y address input simultaneously with the command for each read / write command input at any time. That is, the Y address can be accessed randomly while the X address is fixed. Such an operation is called a Y address priority operation. Note that information can be written to a memory cell at an arbitrary Y address in the same way for a write command.

  In this Y address priority operation, in addition to the advantage of random access, a plurality of data latched in each sense amplifier of the sense amplifier group operated by a single active command can be efficiently used. That is, random access to the memory cells included in 256 pages is possible by one charge / discharge current of the word line and one (plural) bit line charge / discharge current by the sense amplifier.

  Therefore, the current consumption required for one access is a value obtained by dividing the current consumption due to charging / discharging of the word line and charging / discharging of the bit line by the number of accesses to the page activated at the same time. Therefore, the greater the number of accesses in the simultaneously activated page, the smaller the current consumption per SDRAM access.

  Further, in the Y address priority operation, the number of clocks required from the active command to the application of the read / write command and the number of clocks required from the precharge command to the application of the next active command are the ratio of the entire operation. Less is. Therefore, the ratio of data to the input / output bus (data occupation ratio) is high, and the efficiency of the I / O bus is good in the system. These have the effect that the higher the system clock frequency (higher frequency), the higher the data occupancy rate of the input / output bus in the SDRAM that must have a higher latency.

  By the way, depending on the customer's system using the SDRAM, there is a system having a small bit length to access (for example, continuous 4 bits, 8 bits, etc.). In the SDRAM access by such a system, the number of read / write operations smaller than the page length is not allowed between one active command and a precharge command, and the X address is changed by the next active command. Such an operation is called an X address priority operation for convenience. In this operation, a sense amplifier activated by a single active command is not efficiently used.

  For example, the Y address is changed (X address is constant) to access four memory cells. In this case, the current corresponding to the charge / discharge current of one word line selected by the X address and the number of sense amplifiers to be activated (8192) (including the charge / discharge current of the bit line by the sense amplifier) are consumed. To do. The current consumption at this time is P (y). Therefore, the current consumption for access to one memory cell is P (y) / 4.

  On the other hand, when four memory cells are accessed by changing the X address (the Y address is arbitrary), an active command and a precharge command are required every time the X address is changed. Therefore, in the case of this access method, the current consumption is four times (4 × P (y)) when accessing with the X address fixed, and the current consumption for accessing one memory cell is P (y).

Therefore, in the case of a system or application that frequently uses the X address priority operation, a memory device having a shallow Y address (small number of pages) and a deep X address is effective.
However, the X address priority operation and the Y address priority operation may be mixed depending on the access method of the system using the memory device and the application step. In such a case, if a memory device with a shallow Y address is used, the access speed may become extremely slow depending on the order of access, which hinders speed improvement. On the other hand, if a memory device with a shallow X address is used, current consumption will be hindered.

  Furthermore, if an operation with a large current consumption such as the X address priority operation is repeated, the temperature (junction temperature) of the chip of the memory device may be increased. In this case, the data retention characteristic deteriorates due to the temperature rise, and the refresh operation as the data retention operation must be frequently performed. Then, the chip temperature is obtained by adding the self-heating due to the refresh operation of the memory device to the temperature rise due to the access to the memory device, resulting in deterioration of data retention characteristics and further increase in current consumption due to frequent refresh operations. In addition, when the data holding operation is performed asynchronously regardless of the control on the customer system side (self-refresh operation), the number of busy states not responding to external accesses in these refresh operations increases, and the system performance is reduced. Decrease (I / O bus data occupation rate decreases).

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a storage device, an address control method, and a system capable of efficiently accessing and reducing current consumption.

  In order to achieve the above object, the invention described in claim 1 is a storage device for accessing a memory array in which memory cells are arrayed at a first address and a second address, and controls a logical address of the memory array. Map changing means for changing the logical address map shape of the memory array, and the logical address map shape is set during the standby period or at the time of switching from standby to active by external access.

  According to a second aspect of the present invention, in a storage device for accessing a memory array in which memory cells are arrayed at a first address and a second address, the logical address of the memory array is controlled by controlling the logical address of the memory array. Map change means for changing the map shape is provided, and the address map is changed at least during a period from activation to deactivation of the circuit based on the first or second address.

  According to a third aspect of the present invention, in a storage device that accesses a memory array in which memory cells are arrayed at a first address and a second address, the logical address of the memory array is controlled by controlling the logical address of the memory array. Map change means for changing the map shape is provided, and the logical address map shape is changed by changing the depth of at least one of the first and second addresses.

  According to a fourth aspect of the present invention, in a storage device for accessing a memory array in which memory cells are arrayed at a first address and a second address, the logical address of the memory array is controlled by controlling the logical address of the memory array. Map change means for changing the map shape and a control terminal for controlling the logical address are provided.

  According to a fifth aspect of the present invention, in a storage device for accessing a memory array in which memory cells are arrayed at a first address and a second address, the logical address of the memory array is controlled by controlling the logical address of the memory array. Map changing means for changing the map shape is provided, the memory array is composed of a plurality of banks, and the logical address map shape can be set for each bank.

  According to a sixth aspect of the present invention, in the storage device according to any one of the first to fifth aspects, the map changing unit changes the logical address map shape every time the memory array is activated.

  According to a seventh aspect of the present invention, in a storage device that accesses a memory array in which memory cells are arrayed at a first address and a second address, based on access mode information that changes a logical address map shape of the memory array. The address control means for replacing a part of the external address with the first address or the second address for each cycle in which the external address for access in the first address direction is input, and the access mode information An address configuration selection circuit that generates an address configuration selection signal according to the setting of the logical address map shape by a combination of a control signal to be applied or a plurality of control signals, and the address control means includes the address configuration selection The replacement is performed based on the signal.

  According to an eighth aspect of the present invention, in a storage device that accesses a memory array in which memory cells are arrayed at a first address and a second address, the memory device is based on access mode information that changes a logical address map shape of the memory array. In each cycle in which an external address for access in the first address direction is input, an address control means for replacing a part of the external address with the first address or the second address and an external address are input. Based on the address configuration selection signal, the output signal is switched between the first signal generation circuit that generates the selection signal in the first address direction and the second signal generation circuit that generates the selection signal in the second address direction. And an address generation circuit having a switching unit.

  According to a ninth aspect of the present invention, in a storage device that accesses a memory array in which memory cells are arrayed at a first address and a second address, based on access mode information that changes a logical address map shape of the memory array. In each cycle in which an external address for access in the first address direction is input, an address control means for replacing a part of the external address with the first address or the second address and an external address are input. A first signal generation circuit for generating a selection signal in the first address direction based on an address configuration selection signal and an external address are input, and a selection signal in the second address direction is generated based on the address configuration selection signal And a second signal generation circuit.

  According to a tenth aspect of the present invention, in a storage device that accesses a memory array in which memory cells are arrayed at a first address and a second address, based on access mode information that changes a logical address map shape of the memory array. The address control means for replacing a part of the external address with the first address or the second address for each cycle in which the external address for access in the first address direction is input, and And a bonding or fuse ROM for storing the access mode information.

  According to an eleventh aspect of the present invention, in a storage device that accesses a memory array in which memory cells are arrayed at a first address and a second address, based on access mode information that changes a logical address map shape of the memory array. The address control means for replacing a part of the external address with the first address or the second address for each cycle in which the external address for access in the first address direction is input, and And an externally rewritable ROM for storing the access mode information.

  According to a twelfth aspect of the present invention, in a storage device that accesses a memory array in which memory cells are arrayed at a first address and a second address, the access mode information changes the logical address map shape of the memory array. The address invalidating means invalidates the external address or a part thereof for each cycle in which the external address for accessing in the first address direction is input, and the address invalidating means includes decoding compression. Means are provided for clamping any address to vary the rate.

  According to a thirteenth aspect of the present invention, in a storage device that accesses a memory array in which memory cells are arrayed at a first address and a second address, based on access mode information that changes a logical address map shape of the memory array. Each time an external address for access in the first address direction is input, an address invalidating means for invalidating the external address or a part thereof, and a control signal to which the access mode information is applied, Or an address configuration selection circuit that generates an address configuration selection signal in accordance with the setting of the logical address map shape by a combination of a plurality of control signals, and the address invalidating means is configured to invalidate the address based on the address configuration selection signal. Execute the conversion.

  According to a fourteenth aspect of the present invention, in a storage device that accesses a memory array in which memory cells are arrayed at a first address and a second address, based on access mode information that changes a logical address map shape of the memory array. The address invalidation means for invalidating the external address or a part thereof, and the external address are inputted every cycle in which the external address for accessing in the first address direction is inputted. And an address generator having a switching unit that switches the output signal between a first signal generation circuit that generates a selection signal in the first address direction and a second signal generation circuit that generates a selection signal in the second address direction. Circuit.

  According to a fifteenth aspect of the present invention, in a storage device that accesses a memory array in which memory cells are arrayed at a first address and a second address, the access mode information is used to change the logical address map shape of the memory array. The address invalidation means for invalidating the external address or a part thereof, and the external address are inputted every cycle in which the external address for accessing in the first address direction is inputted. A first signal generation circuit that generates a selection signal in the first address direction based on the second signal generation circuit that receives an external address and generates a selection signal in the second address direction based on the address configuration selection signal; Equipped with.

  According to a sixteenth aspect of the present invention, in a storage device that accesses a memory array in which memory cells are arrayed at a first address and a second address, based on access configuration information that changes a logical address map shape of the memory array. The address invalidating means for invalidating the external address or a part thereof for each cycle in which the external address for access in the first address direction is input, and the address invalidating means include the access form information And a Fuse ROM.

  According to a seventeenth aspect of the present invention, in a storage device that accesses a memory array in which memory cells are arrayed at a first address and a second address, based on access mode information that changes a logical address map shape of the memory array. The address invalidating means for invalidating the external address or a part thereof for each cycle in which the external address for access in the first address direction is input, and the address invalidating means include the access form information And a ROM rewritable from the outside.

  The invention according to claim 18 is an address control method in a storage device for accessing a memory array in which memory cells are arrayed at a first address and a second address, and changes a logical address map shape of the memory array. Based on the access form information to be performed, each time an external address for access in the first address direction is input, a part of the external address is replaced with the first address or the second address, and the access form Information is set during the standby period or simultaneously with the active operation.

  The invention according to claim 19 is an address control method in a storage device for accessing a memory array in which memory cells are arrayed at a first address and a second address, and changes a logical address map shape of the memory array. Based on the access form information to be performed, for each cycle in which an external address for access in the first address direction is input, a part of the external address is replaced with the first address or the second address, and the logical address The number of activations of the sense amplifier is controlled according to the map shape.

  The invention according to claim 20 is an address control method in a storage device for accessing a memory array in which memory cells are arrayed at a first address and a second address, and changes a logical address map shape of the memory array. Based on the access form information to be performed, for each cycle in which an external address for access in the first address direction is input, a part of the external address is replaced with the first address or the second address, and the logical address The compression rate of decoding is varied according to the map shape.

  The invention according to claim 21 is an address control method in a storage device for accessing a memory array in which memory cells are arrayed at a first address and a second address, and changes a logical address map shape of the memory array. Based on the access form information to be performed, each time an external address for access in the first address direction is input, a part of the external address is replaced with the first address or the second address, and the access form An address control method for generating an address configuration selection signal corresponding to the setting of the logical address map shape by a control signal to which information is applied or a combination of a plurality of control signals, and executing the replacement based on the address configuration selection signal .

  According to a twenty-second aspect of the present invention, in the address control method for a storage device according to the twenty-first aspect, the first and second addresses are generated by a common address generating unit, and an output destination of the common address generating unit Are switched by the address configuration selection signal.

  The invention described in claim 23 is the address control method in the storage device according to claim 21, comprising first and second address generating means for generating the first and second addresses by an external address, The input destination of the external address is switched by an address configuration selection signal.

  The invention according to claim 24 is an address control method in a storage device for accessing a memory array in which memory cells are arrayed at a first address and a second address, and changes a logical address map shape of the memory array. The external address or a part thereof is invalidated for each cycle in which an external address for access in the first address direction is input based on the access type information to be accessed. It is set at the same time as the operation.

  The invention according to claim 25 is an address control method in a storage device for accessing a memory array in which memory cells are arrayed at a first address and a second address, and changes a logical address map shape of the memory array. The external address or a part thereof is invalidated for each cycle in which the external address for accessing in the first address direction is input based on the access form information to be performed, and the sense amplifier is controlled according to the logical address map shape. Control the number of activations.

  The invention according to claim 26 is an address control method in a memory device for accessing a memory array in which memory cells are arrayed at a first address and a second address, and changes a logical address map shape of the memory array. The external address or a part of the external address is invalidated for each cycle in which the external address for the access in the first address direction is input based on the access form information to be compressed, and decoding is compressed according to the logical address map shape. Variable rate.

  The invention according to claim 27 is an address control method in a memory device for accessing a memory array in which memory cells are arrayed at a first address and a second address, and changes a logical address map shape of the memory array. A control signal for invalidating the external address or a part thereof and applying the access form information for each cycle in which an external address for access in the first address direction is input based on the access form information Alternatively, an address configuration selection signal corresponding to the setting of the logical address map shape is generated by a combination of a plurality of control signals, and the invalidation is executed based on the address configuration selection signal.

  The invention according to claim 28 is the address control method for a storage device according to claim 27, wherein the first and second addresses are generated by a common address generation means, and an output destination of the common address generation means Are switched by the address configuration selection signal.

  The invention according to claim 29 is the address control method for a storage device according to claim 27, comprising first and second address generating means for generating the first and second addresses by an external address, The input destination of the external address is switched by an address configuration selection signal.

  The invention according to claim 30 is a system comprising a storage means and a control means for accessing and controlling the storage means, wherein the control means supplies access status information for the storage means at a time, and the access The form information is supplied at the same time as or before the start of the access, and the storage means displays the logical address map form of the memory array in which the memory cells are arrayed at the first address and the second address as the access form information. Change according to.

According to a thirty-first aspect of the present invention, the control means supplies the access form information using one of address information, data, and code information based on a control signal.
The invention according to claim 32 is a system comprising a storage means and a control means for accessing and controlling the storage means, wherein the control means supplies access status information for the storage means and the access The form information is supplied from code information by a control signal, and the storage unit changes the logical address map form of the memory array in which the memory cells are arrayed at the first address and the second address according to the access form information. The code information is received in accordance with the edge of the pulse signal having a constant period.

  According to a thirty-third aspect of the present invention, in the system according to the thirty-third aspect, the control means supplies the access mode information from code information based on a control signal, and the storage means stores the code information at a constant period. It is received at the edge of the pulse signal.

As described above in detail, according to the inventions described in claims 1 to 17, it is possible to provide a storage device capable of achieving efficient access and reducing current consumption.
As described in detail above, according to the invention described in claims 18 to 29, it is possible to provide a storage device address control method capable of achieving efficient access and reduction of current consumption.

  As described above in detail, according to the inventions described in claims 30 to 33, it is possible to provide a system capable of achieving efficient access and reducing current consumption.

(First embodiment)
Hereinafter, a first embodiment embodying the present invention will be described with reference to FIGS.
FIG. 3 is a schematic configuration diagram of the module 10.

  The module 10 is an MCM (Multi Chip Module) and includes a CPU 11 and a memory device 12, which are mounted on a substrate 13. The CPU 11 is connected to the memory device 12 and accesses the memory device 12.

  The CPU 11 gives access mode information to the memory device 12 once before the start of access or at any time. The memory device 12 has a function of changing the logical address map shape according to the access mode information. More specifically, the memory device 12 changes the logical address map shape in response to access mode information, X address, and Y address applied from the outside (CPU 11). Therefore, the CPU 11 functions as a memory controller that controls the logical address map shape of the memory device 12.

  The logical address map shape is determined by the depth of the X address and the Y address. The capacity of the memory cell array is constant. Accordingly, the memory device 12 changes the depth of the X address and the depth of the Y address in a complementary manner.

  The memory device 12 includes an external address terminal for inputting an address signal having the number of bits necessary for designating the maximum value of the X address and the maximum value of the Y address by a plurality of logical address map shapes.

  For example, a memory device having a capacity of 128 Mbits (32 I / O, 4 bank configuration) generally (standard) has 1 MB of memory cells for 1 I / O in each bank. These memory cells include a plurality (4096) of word lines selected by a 12-bit row address (X address) and a plurality (256) of bit lines selected by an 8-bit column address (Y address). An array is arranged. A memory device such as an SDRAM is configured to capture an X address and a Y address by an address multiplex method. Accordingly, a general memory device has 12 address pins for capturing a 12-bit X address, and captures a Y address from these address pins.

On the other hand, the memory device 12 of this embodiment changes the depth of the X address and the depth of the Y address according to the logical address map shape.
FIG. 4 shows a first memory array M1 formed in a logical address map shape (first shape) similar to the general memory device described above. FIG. 5 shows a second memory array M2 formed in a logical address map shape (second shape) in which the X address is deeper and the Y address is shallower than FIG.

The first memory array M1 has a logical address map shape of an X address depth m (number of logical word lines 2 ^m ) and a Y address depth n (logical page length 2 ⁿ ). Incidentally, mark the 2 ^m as 2 ** m in the figure) the second memory array M2, a logical address map shape X address depth m + 1 (logical number of word lines 2 ^{m + 1),} Y address depth n- 1 (logical page length 2 ^n-1 ).

In the first memory array M1, a logical one of 2 ^m word lines is selectively activated, and the information of 2 ⁿ memory cells is amplified and held by the corresponding sense amplifier in the same number. The

In the second memory array M2, a logical ^{one of} 2 ^{m + 1} word lines is selectively activated, and the information of 2 ^n-1 memory cells is amplified by the corresponding sense amplifier by the same number. And retained.

Here, arbitrary memory cell information is accessed by a random access request along the Y direction based on the Y address applied from the outside.
In the case of the first memory array M1 (FIG. 4), the memory device 12 includes four memory devices 12 according to the burst length based on the first Y address Y1 (indicated by a circle in the figure) applied from the outside. Internal Y address signals (Y1 + 0, Y1 + 1, Y1 + 2, Y1 + 3) are sequentially generated. The memory device 12 serially accesses the memory cells selected by the internal row address signal continuously from the outside.

  Similarly, the memory device 12 sequentially generates four internal Y address signals (Y2 + 0, Y2 + 1, Y2 + 2, Y2 + 3) based on the second Y address Y2, and the internal row. The memory cells selected by the address signal are continuously serially accessed from the outside.

  Further, the memory device 12 similarly generates four internal Y address signals (Y3 + 0, Y3 + 1, Y3 + 2, Y3 + 3) sequentially based on the third Y address Y3, and the internal Y address. The memory cells selected by the signal are continuously serially accessed from the outside.

  In the serial access described above, access to the head addresses Y1, Y2, and Y3 having the same (common) X address is called a page operation by random access. An access to the Y address added (+ 0, + 1, + 2, + 3) to the head address Y1, Y2, Y3 is called a burst operation (the burst length of the burst operation is 1, 2, 4, 8,..., But here the burst length is 4).

When the X address changes, after precharging (equalizing) the memory device 12, the word line corresponding to the changed X address is selectively activated, and the memory cell is connected to the bit line corresponding to the Y address. to access. Here, the page operation is completed three times (3 × 4 = 12 accesses), but the page operation can be performed at maximum 2 ⁿ / 4 (2 ⁿ accesses).

  On the other hand, in the case of the second memory array M2 (FIG. 5), the memory device 12 responds to the burst length based on the first Y address Y1 (indicated by parentheses in the figure) applied from the outside. Four internal Y address signals (Y1 + 0, Y1 + 1, Y1 + 2, Y1 + 3) are sequentially generated. The memory device 12 serially accesses the memory cells selected by the internal row address signal continuously from the outside.

  Next, when the X address changes, the memory device 12 once performs a precharge (equalize) operation, selectively activates a word line corresponding to the changed X address, and four internal Ys based on the second Y address Y2. Address signals (Y2 + 0, Y2 + 1, Y2 + 2, Y2 + 3) are sequentially generated, and the memory cells selected by the internal Y address signal are serially accessed externally.

Further, when the X address changes, the memory device 12 once performs a precharge (equalize) operation, selectively activates the word line corresponding to the changed X address, and four internal Y addresses based on the third Y address Y3. Signals (Y3 + 0, Y3 + 1, Y3 + 2, Y3 + 3) are sequentially generated, and serially externally access the memory cells selected by the internal row address signal. Here, the page operation is finished once (4 accesses), but the page operation can be performed at maximum 2 ^n-1 / 4 (2 ^n-1 accesses).

Consider the occupation ratio of the I / O bus in the first memory array M1 and the second memory array M2. In the first memory array M1, the number of accesses that can be continued with respect to one X address is as large as 2 ⁿ times, and the occupation ratio of the I / O bus can be increased. On the other hand, in the second memory array M2, the number of continuous accesses to one X address is 2 ^n-1 times, which is half that of the first memory array M1, and the I / O bus occupation ratio is There is a possibility of being limited lower than the first memory array M1.

  Next, consider the current consumption in the first memory array M1 and the second memory array M2. The current consumption of each memory array M1, M2 corresponds to the activation of the word line and the charge / discharge current due to the activation of the sense amplifier.

  Let P be the current consumption of the word line and the sense amplifier when the first memory array M1 is precharged once. At this time, when the second memory array M2 is precharged once, it is P / 2. Consider the current consumption when the first memory array M1 is operated with priority on the X address. When access is performed while changing the X address in a burst length of 4 and a page operation once (4 accesses), the average consumption current of the activation of the word line and the sense amplifier per access is P / 4 (= P ÷ 4) It is. When the second memory array M2 is operated in the same manner, the average current consumption of the word line and access of the sense amplifier per access is P / 8 (= (P / 2) / 4). As described above, in the X address priority operation in which the page is not fully utilized, the second memory array M2 is more advantageous in terms of current consumption.

  Therefore, when the memory device is accessed with an operation preferentially in the Y address direction, the I / O bus occupation rate may be higher when the logical address map of the first memory array M1 is used. On the other hand, when the memory device is accessed with an operation preferentially in the X address direction, the current consumption efficiency is better when the logical address map of the second memory array M2 is used.

FIG. 1 is a block diagram for explaining an outline of a memory device (SDRAM) 12.
The SDRAM 12 includes a clock buffer 21, a command decoder 22, an address buffer 23, an input / output buffer 24, a control signal latch 25, a mode register 26, an address generation circuit 27, a write / read (I / O) control circuit 28, and a DRAM core 29. Have.

  The clock buffer 21 receives a clock enable signal CKE and an external clock signal CLK from an external device, and outputs an internal clock signal CLK1 generated based on them to each circuit.

  The command decoder 22 inputs an external command COM from an external device in response to the internal clock signal CLK1 from the clock buffer 21, that is, the clock signal CLK. In the present embodiment, the external command COM is composed of a chip select signal / CS, a column address strobe signal / CAS, a write enable signal / WE, and a row address strobe signal / RAS. Then, the command decoder 22 responds to the internal clock signal CLK1, and at that time, the external command COM, that is, the write command from the state (H level or L level) of each signal / CAS, / WE, / CS, / RAS, Various commands such as a read command and a refresh command are decoded. The command decoder 22 outputs these decoded commands from the external command COM to the address buffer 23, the input / output buffer 24, the control signal latch 25, the mode register 26, and the I / O control circuit 28 as internal commands and enable signals. .

  The address buffer 23 has a buffer function and a latch function, and inputs address signals A0 to A12 and bank address signals BA0 and BA1 from an external device based on an internal command from the command decoder 22. The address buffer 23 amplifies the input address signals A0 to A12 and the bank address signals BA0 and BA1, latches address data based on them, and outputs them to the control signal latch 25, the mode register 26 and the address generation circuit 27.

  Note that a standard memory device having substantially the same memory capacity as the memory device 12 operates with 12-bit address signals A0 to A11 and 2-bit bank addresses BA0 and BA1. Therefore, the memory device 12 has more address pins for inputting the 1-bit address signal A12 to the standard memory device.

  The input / output buffer 24 is activated based on an enable signal from the command decoder 22, and receives write data DQ0 to DQ31 and a mask control signal DQM from an external device. Input / output buffer 24 outputs write data DQ0 to DQ31 to I / O control circuit 28 in response to internal clock signal CLK1. The input / output buffer 24 outputs the read data DQ0 to DQ31 from the I / O control circuit 28 to the external device in response to the internal clock signal CLK1. The input / output buffer 24 masks the write data DQ0 to DQ31 in response to the mask control signal DQM.

  The control signal latch 25 inputs the internal command from the command decoder 22 and the address data from the address buffer 23. The control signal latch 25 outputs control signals for various processing operations such as write data write, read data read, refresh, and self-refresh to the DRAM core 29 based on these internal commands and address data. To do.

  The mode register 26 inputs an internal command (mode register set command) from the command decoder 22 and address data from the address buffer 23. The mode register 26 holds various processing operation modes performed on the DRAM core 29 based on these internal commands and address data.

The mode register 26 outputs a control signal based on the held mode information.
The mode information held by the mode register 26 includes access mode information. The access form information is information indicating the logical address map shape of the DRAM core 29. The mode register 26 outputs an address configuration selection signal generated based on the access form information to the address generation circuit 27.

  The address generation circuit 27 inputs address data based on the address signals A0 to A12 from the address buffer 23. Then, the address generation circuit 27 generates the row address data and the column address data generated corresponding to the logical address map shape of the DRAM core 29 at that time based on the mode of the mode register 26 and the address configuration selection signal. Output to. The address generation circuit 27 has a function of automatically generating a column address incremented from the input address based on the burst length set in the mode register 26.

  The I / O control circuit 28 performs input or output control based on an internal command from the command decoder 22. The I / O control circuit 28 outputs write data (32 bits) from the input / output buffer 24 to the DRAM core 29, and outputs read data (32 bits) from the DRAM core 29 to the input / output buffer 24.

  The DRAM core 29 is composed of a plurality of (four in this embodiment) banks. Each bank receives a control signal from the control signal latch 25, row address data from the address generation circuit 27, and column address data. To do. That is, bank address signals BA0 and BA1 corresponding to the number of banks of the DRAM core are input to the address buffer 23, and the control signal latch 25 and the address generation circuit 27 are provided for each bank.

  The DRAM core 29 executes various processing operations such as write data write, read data read, refresh, and self-refresh for a built-in memory cell array based on the control signal and address data. Accordingly, the DRAM core 29 writes the write data DQ0 to DQ31 input from the input / output buffer 24 into the memory cell at a predetermined address based on the control signal and the address data.

FIG. 2 is a principle diagram for explaining the function of changing the logical address map shape according to the access mode information.
The memory device 12 includes an address configuration selection circuit 30, a changeover switch 31, a row related circuit 32, a column related circuit 33, first and second decoders 34 and 35, and a memory cell array 36. For example, the address configuration selection circuit 30 includes the command decoder 22 and the mode register 26 shown in FIG. The changeover switch 31, the row related circuit 32 and the column related circuit 33 are included in the address generation circuit 27 of FIG. 1, and the first and second decoders 34 and 35 and the memory cell array 36 are included in the DRAM core 29. The configuration may be changed as appropriate. Alternatively, the address configuration selection circuit 30 may be provided separately.

  The address configuration selection circuit 30 receives a plurality of control signals and a plurality of address signals. The address configuration selection circuit 30 analyzes a command supplied from the outside at that time based on a plurality of control signals. When the command at that time is a command for changing the logical address map shape, the address configuration selection circuit 30 generates the address configuration selection signal ASS generated to change the logical address map shape based on the address signal at that time. Is output to the changeover switch 31 and the first and second decoders 34 and 35.

  An external input address and an address configuration selection signal ASS are input to the changeover switch 31. The changeover switch 31 switches the external input address to be supplied to the row related circuit 32 or the column related circuit 33 in response to the address configuration selection signal ASS. The signal to be switched is an external address signal added to an external address signal applied to a standard memory device having the same memory capacity.

  That is, in the case of the memory device 12 of FIG. 1, the external address signal A12 corresponds to it. The memory device 12 supplies the external address signal A12 to the row related circuit 32 or the column related circuit 33 in response to the access mode information.

  The row-related circuit 32 supplies a column address generated based on the supplied address signal to the first decoder 34. The column-related circuit 33 supplies the column address generated based on the supplied address signal to the second decoder 35.

The first decoder 34 decodes the supplied address signal, generates a column selection signal for selecting a bit line (or column line) corresponding to the address signal, and supplies the column selection signal to the memory cell array 36. The number of selectable bit lines differs depending on the selected logical address map shape. In the present embodiment, the maximum number is 2 ⁿ (n = 8) depending on the address signals A0 to A7 (FIG. 1). Therefore, the second decoder 35 is configured to generate a selection signal for selecting one of 2 ⁿ bit lines.

The first decoder 34 includes clamping means 34a. The clamping means 34a is provided for clamping the input of the circuit that is not required by the logical address map shape.
Selection of selecting one of 2 ⁿ bit lines (one of 2 ⁿ sense amplifiers) when the logical address map shape (first memory array M1) shown in FIG. 4 is selected A signal is generated based on the address signals A0 to An-1. On the other hand, when the logical address map shape (second memory array M2) shown in FIG. 5 is selected, a selection signal for selecting one of 2 ^n-1 bit lines (actually 2 ⁿ lines). Two of the bit lines) are generated based on the address signals A0 to An-2.

  Therefore, when the second memory array M2 is selected, the operation of the circuit portion to which the address signal An-1 is input is stabilized (actually, a plurality of bit lines corresponding to the logical address map shape are simultaneously selected). Therefore, the input is clamped by the clamping means 34a.

  For example, a decoder to which four bit lines are connected selects one of the four bit lines based on 2-bit address signals A0 and A1. The number of wirings selected with respect to the number of wirings connected to the decoder is called a compression rate. Accordingly, the compression rate of the first decoder 34 at this time is 1/4.

  The clamping means clamps one address signal (for example, A1) to a predetermined level (decoder type is H level when NAND logic is used, and L level when NOR logic is used). In this case, the decoder selects two of the four bit lines connected by the 1-bit address signal A0. At this time, the compression rate of the decoder is ½.

  That is, the clamp means changes the compression rate of the decoder. Therefore, the clamping unit 34 a of the present embodiment clamps a predetermined address to a level corresponding to the configuration of the first decoder 34 so as to vary the compression rate of the first decoder 34.

The second decoder 35 decodes the supplied address signal, generates a row selection signal for selecting a word line corresponding to the address signal, and supplies the row selection signal to the memory cell array 36. The number of selectable word lines differs depending on the selected logical address map shape. In this embodiment, as shown in FIG. 5, the maximum number of word lines is 2 ^{m + 1} (m = 12) by address signals A0 to A12 (FIG. 1). Become. Accordingly, the first decoder 34 is configured to generate a selection signal for selecting one of 2 ^{m + 1} word lines.

The second decoder 35 includes clamping means 35a. The clamping means 35a is provided for clamping an input of a circuit that is not required by the logical address map shape.
When the logical address map shape (first memory array M1) shown in FIG. 4 is selected, a selection signal for selecting one of 2 ^m word lines is generated based on the address signals A0 to Am. . On the other hand, when the logical address map shape (second memory array M2) shown in FIG. 5 is selected, selection signals for selecting one of 2 ^{m + 1} word lines are address signals A0 to Am + 1. Is generated based on

  Therefore, when the first memory array M1 is selected, the operation of the circuit portion to which the address signal Am + 1 is input is stabilized (actually, a plurality of sub word lines are simultaneously selected according to the logical address map shape). Therefore, the input is clamped by the clamping means 35a.

  The clamp unit 35 a clamps a predetermined address to a level corresponding to the configuration of the second decoder 35 in order to vary the compression rate of the second decoder 35, similarly to the clamp unit 34 a of the first decoder 34.

  The number of selected word lines is changed by changing the number of sub word lines driven at one time. That is, the memory cell array 36 is connected to the main word line driven by the selection signal generated by the decoder 35 and to the main word line via a plurality of gates, and is driven secondarily by driving the main word line. A sub word line is provided. For example, a sub word line is provided for each column block. When the main word line is driven, the sub word line is driven by the gate that responds to the driving. Therefore, the number of sub word lines to be driven is made to correspond to the access type information by taking the logic of the main word line driving and the access type information at the gate for driving the sub word line. Thereby, the logical address map shape can be substantially changed according to the access mode information.

FIG. 7 is an explanatory diagram of the configuration corresponding to the configuration of the memory cell array and the first memory array M1 (see FIG. 4).
The memory cell array 36 includes cells 37 arrayed by 2 ^m word lines and 2 ⁿ bit lines, and a sense amplifier 38 connected to each bit line.

Of the plurality of word lines, one of the word lines based on the logic of the address signal XA <0: m> (address signals A0 to A11) is activated by the X decoder 35 (FIG. 2). Further, 2 ⁿ sense amplifiers 38 corresponding to the selected word line are activated. Cell information is read out from the 2 ⁿ cells 37 connected to the selected word line to the corresponding sense amplifier 38. Among the plurality of sense amplifiers 38, one based on the logic of the address signal YA <0: n> (address signals A0 to A7) is connected to a data bus line (not shown) by the Y decoder 34 (FIG. 2). In this way, a read or write operation is performed on the selected cell 37 through the sense amplifier 38 connected to the data bus line.

FIG. 8 is an explanatory diagram of the configuration corresponding to the configuration of the memory cell array and the second memory array M2 (see FIG. 5).
The memory cell array 36 is composed of two divided column blocks, one of which is selected by an address signal XAm + 1. Each block includes 2 ^m sub-word lines and 2 ^n-1 sense amplifiers 38, respectively. Therefore, the memory cell array 36 has two sub word lines selected by substantially the same X address, and these word lines correspond to one word line in FIG.

One of the plurality of sub word lines is activated by the X decoder 35 based on the logic of the address signal XA <0: m + 1> (address signals A0 to A12). Then, 2 ⁿ⁻¹ sense amplifiers 38 corresponding to the selected sub word line are activated, and cell information is read out from the plurality of cells 37 connected to the sub word line to the corresponding sense amplifiers 38 respectively. One of the plurality of sense amplifiers 38 based on the logic of the address signal YA <0: n-1> (address signals A0 to A6) is connected to a data bus line (not shown) by the Y decoder 34 (FIG. 2). The In this way, a read or write operation is performed on the selected cell 37 through the sense amplifier 38 connected to the data bus line.

Accordingly, in the memory cell array 36 shown in FIG. 7, cell information from 2 ⁿ cells 37 connected to the word line activated by one X address XA is latched in the sense amplifier 38, respectively. Therefore, access to the cell 37 selected with the same X address is performed only by designating the Y address, so that the access time is short and the current consumption is small.

On the other hand, in the memory cell array 36 corresponding to the logical address map shape shown in FIG. 8, cell information from 2 ⁿ⁻¹ cells 37 connected to one activated sub word line is latched by the sense amplifier 38. . The sub word line activated at this time is ½ of the length of the word line in FIG. Further, the number of sense amplifiers 38 to be activated is ½ compared to the case shown in FIG. Therefore, the number of cells 37 accessible by the same X address is ½, but the current consumption is also ½.

  In FIG. 8, the two column blocks constituting the memory cell array 36 are selected by the expanded X address XAm + 1. Therefore, the output destination of the X address XAm + 1 is switched from the row related circuit 32 to the column related circuit 33. That is, the memory device 12 replaces the X address XAm + 1 given from the outside with the direction of selecting the bit line with the Y address from the direction of selecting the word line with the X address.

The X word XAm + 1 selects a sub word line for the column block and also selects the sense amplifier 38.
As described above, according to the present embodiment, the following effects can be obtained.

  (1) The memory device 12 is configured such that the logical address map shape can be changed. The CPU 11 controls the logical address map shape of the memory device 12 according to the access mode. As a result, efficient access can be performed.

  (2) The memory device 12 changes the number of sense amplifiers 38 activated by a part of the X address based on the logical address map shape. As a result, current consumption can be reduced.

  (2) Depending on the logical address map shape, part of the address signal supplied from the outside is replaced from the X direction to the Y direction or vice versa. As a result, the logical address map shape can be easily changed.

(3) The address configuration is set by the mode register setting command.
As a result, there is no need to provide a dedicated terminal, and an increase in the shape of the memory device 12 can be suppressed.

In addition, you may change the said embodiment into the following aspects.
In the above embodiment, the address configuration selection circuit 30 is provided to generate the address configuration selection signal ASS, and the changeover switch 31 and the first and second decoders 34 and 35 send the address signal from the X direction in response to the signal ASS. As shown in FIG. 9, the changeover switch 31, the first and second decoders 34 and 35 accept externally supplied access form information, and respond directly to the information as shown in FIG. You may comprise so that a map shape may be changed.

  In the above embodiment, the X direction is the word line selection direction (row direction) and the Y direction is the bit line selection direction (column direction). However, the X direction and the column direction may be the row direction. In that case, the address signal supplied from the outside is replaced from the Y direction to the X direction.

(Second embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to FIGS.
For convenience of explanation, the same components as those in the first embodiment are denoted by the same reference numerals, and a part of the explanation is omitted.

FIG. 10 is a schematic block diagram of the memory device 40.
The memory device 40 includes a command generation circuit 41, a mode register 42, and an address generation circuit 43. For example, the command generation circuit 41 includes the clock buffer 21 and the command decoder 22 shown in FIG. As shown in this figure, the circuit may be changed as appropriate as long as it has a desired function (function of changing the logical address map shape).

  The command generation circuit 41 is connected to the clock terminal and the command terminal, and receives the clock signal CLK and the external command COM shown in FIG. In response to the clock signal CLK, the command generation circuit 41 decodes various commands from the state of the external command COM, that is, each signal / CAS, / WE, / CS, / RAS (see FIG. 1). The command generation circuit 41 outputs an ACT signal in the case of an active command, a READ / WRITE signal (hereinafter referred to as an RD / WR signal) in the case of a read / write command, and an MRS signal in the case of a mode register set command. .

  The mode register 42 is connected to an address terminal and inputs external address signals A0 to A12. The mode register 42 holds mode information of various processing operations performed on the DRAM core 29 based on the MRS signal from the command generation circuit 41 and the address signals A0 to A12. The mode information includes access mode information.

  That is, the mode register 42 holds the incasual access form information from the outside (the CPU 11 in FIG. 3) in the mode register 42. Then, the mode register 42 outputs an address configuration select signal (hereinafter simply referred to as select signal) ASS corresponding to the held access mode information.

  Address generation circuit 43 includes an X address generation circuit 44 and a Y address generation circuit 45. The X address generation circuit 44 receives an ACT signal, a select signal ASS, and address signals A0 to A12. The X address generation circuit 44 receives the address signals A0 to A12 as row addresses in response to the ACT signal and outputs the row addresses to the DRAM core 29. At this time, the X address generation circuit 44 validates or invalidates some of the address signals A0 to A12 based on the select signal ASS.

  In the case of the logical address map shape (first memory array M1) shown in FIG. 4, the word lines are selected and activated by address signals A0 to A11. On the other hand, in the case of the logical address map shape (second memory array M2) shown in FIG. 5, the word lines (sub-word lines) are selected and activated by the address signals A0 to A12.

  Therefore, when the memory device 40 is set to operate as the first memory array M1, the X address generation circuit 44 invalidates the address signal A12 and outputs the address signals A0 to A11 as row addresses. On the other hand, when the memory device 40 is set to operate as the second memory array M2, the X address generation circuit validates the address signal A12 and outputs the address signals A0 to A12 as row addresses.

  The Y address generation circuit 45 receives an ACT signal, a select signal ASS, and address signals A0 to A7. The Y address generation circuit 45 receives the address signals A0 to A7 as column addresses in response to the ACT signal, and outputs the column addresses to the DRAM core 29. At this time, the Y address generation circuit 45 validates or invalidates some of the address signals A0 to A7 based on the select signal ASS.

  In the case of the logical address map shape (first memory array M1) shown in FIG. 4, the bit lines are selected and activated by address signals A0 to A7. On the other hand, in the case of the logical address map shape (second memory array M2) shown in FIG. 5, the bit lines are selected and activated by the address signals A0 to A6.

  Therefore, when the memory device 40 is set to operate as the first memory array M1, the Y address generation circuit 45 validates the address signal A7 and outputs the address signals A0 to A7 as column addresses. On the other hand, when the memory device 40 is set to operate as the second memory array M2, the Y address generation circuit 45 invalidates the address signal A7 and outputs the address signals A0 to A6 as column addresses.

FIG. 11 is an operation waveform diagram of FIG.
The memory device 40 performs signal input / output with the outside in response to the rising edge of the clock signal CLK. When the external command COM is a mode register set command (MRS), the memory device 40 receives the address signals BA0, BA1, A0 to A12 or a part thereof at that time as the register setting information V, and performs various processing based on the information V. Set the mode.

  At time t1, the memory device 40 sets the logical address map shape in the first memory array M1 based on the register setting information V. Next, the memory device 40 invalidates a part of the address signals A0 to A12 (address signal A12) received in response to the next active command (ACT), and 4096 word lines based on the address signals A0 to A11. One word line selected from the above is activated. Thereby, the cell information of the memory cell connected to the word line is read out to the sense amplifier.

  Next, the memory device 40 receives the address signals A0 to A7 in response to the read command (RD), and sense amplifiers (shown in FIG. 7) selected from the 256 sense amplifiers based on the address signals A0 to A7. The sense amplifier 38 of # 00 is connected to the data bus line. As a result, cell information of the memory cell corresponding to the address signals A0 to A7 (Y address) received by the read command is output to the outside.

  Thereafter, the memory device 40 receives the read command RD and the Y addresses A0 to A7 continuously or intermittently for each system clock CLK, and can perform page operations (# 80 → # 7F → # FF) by them. . Up to 256 addresses, which are Y addresses, can be continuously read from the I / O data bus. Therefore, at this time, read data from 256 memory cells can be read continuously to the I / O data bus, and the occupation ratio of the I / O data bus by the read data is high.

  At time t2, the memory device 40 sets the logical address map shape in the second memory array M2 by the register setting information V received in response to the mode register set command (MRS). Next, the memory device 40 receives the address signals A0 to A12 (A12 (XAm + 1 in FIG. 8) = “L” in FIG. 8) received in response to the next active command (ACT). One sub-word line selected from is activated. Thereby, the cell information of the memory cell connected to the sub word line is read out to the sense amplifier.

  Next, the memory device 40 receives the address signals A0 to A7 in response to the read command (RD), invalidates a part of the address signals A0 to A7 (address signal A7), and 128 by the address signals A0 to A6. A sense amplifier selected from among the sense amplifiers (the sense amplifier 38 at the bottom stage # 00 shown in FIG. 8) is connected to the data bus line. As a result, the cell information of the memory cell corresponding to the address signals A0 to A6 (Y address) received by the read command is output to the outside.

  Thereafter, the memory device 40 receives the read command RD and the Y addresses A0 to A7, and performs a page operation (# 7F) by them. Next, the memory device 40 deactivates the word line (sub-word line) and the sense amplifier by the precharge command (PRE) and returns to the standby state. Next, the memory device 40 sets the address signals A0 to A12 (A12 (XAm + 1 in FIG. 8) = “H”) received in response to the active command (ACT) after the specified clock (4 clocks in FIG. 11). Based on this, one sub word line selected from 8192 sub word lines is activated. Thereby, the cell information of the memory cell connected to the sub word line is read out to the sense amplifier.

  Next, the memory device 40 receives the address signals A0 to A7 in response to the read command (RD), invalidates a part of the address signals A0 to A7 (address signal A7), and 128 by the address signals A0 to A6. A sense amplifier selected from the sense amplifiers (middle # 00 sense amplifier 38 shown in FIG. 8) is connected to the data bus line. As a result, the cell information of the memory cell corresponding to the address signals A0 to A6 (Y address) received by the read command is output to the outside.

  At this time, the length of the activated sub word line is shorter than the word line of the first memory array M1, and the number of sense amplifiers activated is smaller than that of the first memory array M1. Therefore, although the page length of the second memory array M2 is limited to half, if the access is within the Y address YA <6: 0>, the current consumption of active and precharge required for the same number of accesses is halved. .

FIG. 12 is a block diagram showing an example of the address generation circuit 43.
The address generation circuit 43 includes an X address generation circuit 44, a Y address generation circuit 45, and an inverter circuit 46.

  The X address generation circuit 44 includes twelve first buffer latch circuits 44a corresponding to the address signals A0 to A11 and a second buffer latch circuit 44b corresponding to the address signal A12. The second buffer latch circuit 44b includes clamping means (not shown). It should be noted that the circuit configuration may be changed as appropriate, such as being provided in the clamping means and the column decoder 48 or connected as another circuit.

  The Y address generation circuit 45 includes seven first buffer latch circuits 45a corresponding to the address signals A0 to A6 and a second buffer latch circuit 45b corresponding to the address signal A7. The second buffer latch circuit 45b includes clamping means (not shown). Note that the circuit configuration may be changed as appropriate, such as providing the clamping means in the row decoder 47 or connecting it as a separate circuit.

  The inverter circuit 46 outputs an inverted select signal obtained by logically inverting the input select signal ASS to the second buffer latch circuit 44 b of the X address generation circuit 44. The select signal ASS is input to the second buffer latch circuit 45 b of the Y address generation circuit 45. Therefore, both the second buffer latch circuits 44b and 45b operate in a complementary manner.

  In the X address generation circuit 44, the first buffer latch circuit 44a latches the address signals A0 to A11 and outputs the latch signal to the row decoder 47. The second buffer latch circuit 44b latches the address signal A12 and outputs a latch signal or a signal clamped at a predetermined level in response to the inverted select signal.

  In the Y address generation circuit 45, the first buffer latch circuit 45a latches the address signals A0 to A6, respectively, and outputs the latch signal to the column decoder 48. The second buffer latch circuit 45b latches the address signal A7 and outputs a latch signal or a signal clamped at a predetermined level in response to the select signal ASS.

As described above, according to the present embodiment, the following effects can be obtained.
(1) The memory device 40 invalidates a part of the X address or the Y address according to the changed logical address map shape. As a result, since the external address input is constant regardless of the shape, it is possible to save the trouble of changing the supplied signal in accordance with the map shape.

In addition, you may change the said embodiment into the following aspects.
The X address generation circuit 44 may have a means for clamping an output signal so that a subsequent circuit (for example, a decoder) corresponding to the invalidated address signal A12 does not malfunction. Furthermore, the Y address generation circuit 45 may have a means for clamping the output signal so that a subsequent circuit (for example, a decoder) corresponding to the invalidated address signal A7 does not malfunction.

(Third embodiment)
A third embodiment embodying the present invention will be described below with reference to FIGS.
For convenience of explanation, the same reference numerals are given to the same configurations as those in the first and second embodiments, and a part of the explanation is omitted.

FIG. 13 is a schematic block diagram of the memory device 50, and FIG. 14 is an operation waveform diagram thereof.
The memory device 50 includes a command generation circuit 41, an address configuration register 51, and an address generation circuit 43.

  The address configuration register 51 is connected to an address configuration setting terminal and inputs an address configuration setting signal. The address configuration register 51 receives the ACT signal from the command generation circuit 41.

  The address configuration register 51 determines whether or not the address configuration signal has been changed in response to the ACT signal. The address configuration signal is supplied from the outside (for example, the CPU 11 in FIG. 3) in the logic corresponding to the logical address map shape. That is, the address configuration register 51 determines whether or not the logical address map shape has been changed every time an active command is received based on the ACT signal, and stores the address configuration setting based on the determination result. Then, the address configuration register 51 outputs a select signal ASS corresponding to the setting.

  Such a memory device 50 requires a terminal to which an address configuration signal is applied, but the logical address map shape can be changed without using a mode register set command. Therefore, the cycle (number of clocks) for receiving the active command is reduced as compared with the above embodiment, and the access speed can be improved as a whole.

In addition, you may change the said embodiment into the following aspects.
The address configuration setting may be determined by the system clock signal CLK.
That is, the address configuration register 51 is connected to the clock terminal and receives the system clock signal CLK. The address configuration register 51 determines whether or not the logical address map shape has been changed based on the address configuration signal in response to the rising edge (or falling edge, rising edge and falling edge) of the system clock signal CLK, and the determination result The address configuration setting is stored based on Then, the address configuration register 51 outputs a select signal ASS corresponding to the setting. When configured in this manner, the logical address map shape can be easily changed as compared with the case where the mode register set command is applied. Furthermore, the select signal ASS can be generated by the clock signal CLK earlier than the command generation circuit 41 accepts various commands as compared with the above embodiment. Accordingly, it is possible to prevent an access delay without delaying the operation of the address generation circuit 43 that receives the X address signal.

  In the second and third embodiments, the X address generation circuit and the Y address generation circuit may be shared. That is, as shown in FIG. 15, the memory device 60 includes an X / Y shared address generation circuit 61, a changeover switch 62, latch circuits 63 and 64, a column-related circuit 65, and a row-related circuit 66. The changeover switch 62 is provided corresponding to the address signals A0 to A12, and connects the shared address generation circuit 61 to the column related circuit 65 or the row related circuit 66 in response to the address configuration select signal ASS2.

  The column related circuit 65 is a circuit including an X decoder, and the row related circuit 66 is a circuit including a Y decoder. A latch circuit 63 is inserted and connected between the column-related circuit 65 and the changeover switch 62, and a latch circuit 64 is inserted and connected between the row-related circuit 66 and the changeover switch 62.

  The address configuration select signal ASS2 includes the logic of a control signal for controlling switching so that the output signal of the shared address generation circuit 61 is supplied to the column related circuit 65 or the row related circuit 66 according to its operation, and the address configuration select signal ASS. It is a signal that includes logic.

FIG. 16 is a block diagram showing an example of the shared address generation circuit 61.
The shared address generation circuit 61 includes seven first buffer latch circuits 61a corresponding to the address signals A0 to A6, a second buffer latch circuit 61b corresponding to the address signal A7, and five first buffer latch circuits 61b corresponding to the address signals A8 to A11. A third buffer latch circuit 61c and a fourth buffer latch circuit 61d corresponding to the address signal A12 are provided.

  The changeover switch 62 includes first to third switches 62a to 62c. The first switch 62 a supplies the output signal of the first buffer latch circuit 61 a to the row related circuit 66 or the column related circuit 65. The second switch 62 b invalidates / validates the output signal of the second buffer latch circuit 61 b with respect to the row related circuit 66 or supplies it to the column related circuit 65. The third switch 62c determines whether the output signal of the fourth buffer latch circuit 61d is invalid / valid for the column-related circuit 65.

Such a configuration can reduce the area occupied by the address generation circuit, and is effective in reducing the size of the memory device.
(Fourth embodiment)
Hereinafter, a fourth embodiment of the present invention will be described with reference to FIGS.

In the present embodiment, the logical address map shape can be changed in an asynchronous memory. Incidentally, since the schematic configuration of the asynchronous memory is already known, the drawings and description are omitted.
This memory device determines the address signal ADD as an X address (row address) at the falling edge of the chip enable signal (/ CE) or the row address strobe signal (/ RAS). Next, the memory device determines the address signal ADD as a Y address (column address) by a read or write control signal or the like, and accesses a cell specified by the address. The operation waveform at that time is shown in FIG.

  The change of the logical address map shape is applied to a terminal that is not used when the chip enable signal / CE (or the row address strobe signal / RAS) falls. For example, an I / O terminal, an extended address terminal ADD2, and an address configuration setting terminal are used.

  Further, the logical address map shape may be changed by a completely asynchronous memory device such as SRAM (Static RAM) or flash memory. The operation waveform at that time is shown in FIG.

  In an asynchronous memory device, the address map may be controlled in accordance with the following illegal entry method (control method from outside that is not normally used for access from outside).

  In the illegal entry method, the address configuration select signal in the memory device is generated earlier than the word enable signal from the chip enable signal / CE, as in the case of using the synchronous mode register set command (MRS method). To do. As a result, the access delay can be prevented without delaying the operation of the X address generation circuit or the selector switch (see FIG. 15) for switching its output.

The illegal entry method will be described in detail.
FIG. 19 is a waveform diagram illustrating a mode setting cycle for address configuration.
The memory device has a dedicated terminal for setting the mode for address configuration, and imports necessary information for determining the type of address configuration from the dedicated terminal, thereby preventing external access delay and preventing malfunction. And safe operation of normal operation can be guaranteed.

  That is, the memory device does not perform normal operation when the chip enable signal / CE1 is at the H level. During this period, the address code Code based on the address signal ADD is taken in response to the program mode signal / PE (= address configuration setting terminal) input from the dedicated terminal. Specifically, the memory device activates the input of the address code at the fall of the program mode signal / PE, and latches the address code information at the rise of the signal / PE.

On the other hand, when the chip enable signal / CE1 is at the L level, the memory device enters an operation state corresponding to external access and takes in an address signal ADD corresponding to external access.
In the figure, t1 to t5 are external specification timing conditions.

  At the timing shown in the drawing, the input circuit of the external dedicated terminal is activated at the fall of the program mode signal / PE, and the decoding operation for the address signal is started. Then, the decoding result is determined at the rising edge of the program mode signal / PE, and the input circuit is deactivated. With this operation, power consumption can be reduced.

  In the mode setting cycle for the address configuration described above, the logic of the program mode signal / PE may be inverted. The address code may be input from a data terminal (referred to as DQ or I / OPin).

Further, as will be described later, the mode may be determined after repeating the program cycle by the code method several times.
FIG. 20 is an explanatory diagram of commands.

  When this command is used, a memory device of a specification system that recognizes a command with respect to a reference clock (system clock CLK or chip enable signal / CE1) and performs an external access operation is targeted.

  Accordingly, in the memory device of the specification system that does not operate by a command with respect to the chip enable signal / CE1 as shown in FIG. 17 or FIG. 18, information for simply determining the address for each type of address configuration based on FIG. And may be used as the number of times for mode setting.

  Commands (1) to (6) and (8) to (10) are commands used in normal operation, and commands (7) and (11) are commands that do not make sense in normal operation. Command 7 is a write (WR) operation, but no data is input (masked) because signals / LB and / UB are at the H level. Command (11) is a read (RD) operation, but no data is output because it is similarly masked by signals / LB and / IB.

  In this manner, by setting a command not used for normal operation (an illegal command) as information for determining each type of address configuration, information can be set without providing a dedicated terminal.

  FIG. 21 is a waveform diagram for explaining a mode setting cycle for address configuration. By continuously inputting a plurality of commands (11) in FIG. 20, information necessary for mode setting for address configuration is indicated by an address code. The case where it takes in as is shown.

  The memory device captures the address signal ADD as the address code Code in response to the command (11). This operation is repeated N times. When the N address codes Code fetched corresponding to the command (11) from the first time to the Nth time all match, the address code Code is validated to set the mode for address configuration.

  When the command (11) matches N-1 times, the mode setting for address configuration may be performed based on the address code Code fetched corresponding to the Nth command (11). Further, the address code Code may be taken in any cycle (for example, the first time). Various other applications can be developed.

The address code for setting the mode may be determined by determining the number of address bits corresponding to the number of types of address configurations.
In the case of N mode setting cycles as shown in FIG. 21, a counter circuit is used inside the device. When the upper bits of the counter circuit change with respect to N mode setting cycle entries, the circuit configuration is determined.

FIG. 22 is an operation waveform diagram of the entry control circuit which is a mode setting circuit for program address configuration.
As shown in FIG. 22A, the first entry circuit outputs the first address enable signal proaddz at the H level in the third cycle, and outputs the first entry signal proentz in the fourth cycle. Then, the first entry circuit simultaneously resets the first address enable signal proaddz and the first entry signal proentz. Thus, the memory device changes the previously determined address configuration information to the latest address configuration information according to the address code information fetched in the fourth cycle by the first entry signal proentz.

  As shown in FIG. 22B, the first entry circuit resets the count when it receives another command (device active active command or read / write command) during the counting. As a result, the first address enable signal proaddz and the enable signal proaddz are held at the L level.

That is, in the mode setting for determining each type of address configuration, if the same command for that purpose does not continue for a specified number of times, it is canceled. (The memory device maintains the previously determined address configuration information)
FIG. 23 is an operation waveform diagram of the entry control circuit (second entry circuit) which is a mode setting circuit for the program address configuration corresponding to FIG.

  The second entry circuit outputs the H level address enable signal peaddz in response to the L level program mode signal / PE, and then outputs the H level enable signal peaddz in response to the H level program mode signal / PE. To do. As a result, the memory device changes the previously determined address configuration information to the latest address configuration information according to the address code information fetched by the second entry signal proentz.

FIG. 24 is an operation waveform diagram of the entry signal generation circuit.
As shown in FIG. 24A, the signal generation circuit outputs a composite signal entz in response to the first entry signal proentz. Further, as shown in FIG. 24B, the signal generation circuit outputs a composite signal entz in response to the entry signal pentz.

FIG. 25 is an operation waveform diagram of the mode setting address buffer for address configuration.
The address buffer activates the input circuit in response to the H level address enable signal peaddz and outputs the address signal az <0: 3>. The same operation is performed in response to the first address enable signal proaddz.

FIG. 26 is an operation waveform diagram of the mode setting address latch for address configuration.
The address latch is a mode setting address signal paz for address configuration of the code code obtained by latching the address signal az <0: 3> output in response to the H level address enable signal peaddz in response to the composite signal entz. Output as <0: 3>. The same operation is performed in response to the first address enable signal proaddz.

  The mode setting decoder for address configuration decodes the mode setting address signal paz <0: 3> for address configuration and outputs address configuration selection signals for several types of address maps.

FIG. 27 is an operation waveform diagram of the mode setting decoder.
The decoder decodes the mode setting address signal paz <0: 3>, selects one of several types of address configuration select signals for the address map, and sets it to the H level.

As described above, according to the present embodiment, the following effects can be obtained.
(1) In the asynchronous memory device, as in the above embodiments, it is possible to achieve efficient access and reduce current consumption by changing the logical address map shape.

(2) By adopting the illegal entry method, it is not necessary to change the conventional part, and it can be easily handled with little effort.
In addition, you may change the said embodiment into the following aspects.

The number of bits of the memory cell, the address configuration, the address configuration switching type, and the like may be changed as appropriate.
If the depth of the X address <the depth of the Y address, the address configuration setting terminal can be shared by address terminals that are not used when active. In addition to the active command, the command for setting the address configuration can be a precharge command or another new command.

  -The function that can change the address map is functionalized independently for each bank. The ability to set (change) the logical address map for each bank further improves system performance.

-The function that can change the address map may be fixed arbitrarily by the customer by bonding, product fixing by internal fuse, or internal ROM function.
The vendor may fix each product for a specific application, or the customer may rewrite and use the ROM in the memory device for each system (characteristic).

-The position of the address bit to be clamped may be changed as appropriate.
-You may change the position of the address bit to invalidate suitably.
In each of the above embodiments, the logical address map shape can be changed at any time from the outside, but a ROM such as bonding or Fuse is provided, and the logical address map shape is changed to a desired shape at the time of shipment or user use. You may make it maintain the shape. Further, a ROM rewritable from the outside may be provided, and the logical address map shape may be changed as necessary. In these cases, the logical address map shape is fixed over a short period or a long period. Therefore, existing programs and CPUs can be used. Further, the trouble of changing the logical address map shape for each row access cycle can be saved.

  In each of the above embodiments, the memory device that takes in the X address and the Y address by the address multiplex method is embodied. Also good.

The block diagram for demonstrating the outline of SDRAM. The schematic block diagram of the memory of 1st embodiment. 1 is a block diagram of a memory system. Explanatory drawing of the address structure suitable for Y direction priority operation | movement. Explanatory drawing of the address structure suitable for a X direction priority operation | movement. Explanatory drawing of the consumption current by an address structure and access order. Explanatory drawing of an address map. Explanatory drawing of an address map. FIG. 3 is a schematic block diagram of another memory device. The schematic block diagram of the memory device of 2nd embodiment. FIG. 11 is a timing chart of FIG. 10. The block diagram of an address generation circuit. The schematic block diagram of the memory device of 3rd embodiment. FIG. 14 is a timing chart of FIG. 13. FIG. 3 is a schematic block diagram of another memory device. The block diagram of an address generation circuit. The timing diagram in the asynchronous memory of the fourth embodiment. Timing diagram in a fully asynchronous memory. The wave form diagram explaining a mode setting cycle. An explanatory diagram of commands. The wave form diagram explaining a mode setting cycle. The operation waveform diagram of a program mode setting circuit. The operation waveform diagram of a program mode setting circuit. The operation | movement waveform diagram of a synthetic | combination entry signal generation circuit. The operation waveform diagram of the mode setting address buffer. The operation waveform diagram of the address latch for mode setting. FIG. 6 is an operation waveform diagram of a mode setting decoder.

Explanation of symbols

11 CPU as control means
12 Memory Device as Storage Unit 10 System

Claims (33)

In a storage device that accesses a memory array in which memory cells are arrayed at a first address and a second address,
Map changing means for controlling the logical address of the memory array to change the logical address map shape of the memory array;
The logical address map shape is set in the storage device during the standby period or at the time of switching from standby to active by external access. In a storage device that accesses a memory array in which memory cells are arrayed at a first address and a second address,
Map changing means for controlling the logical address of the memory array to change the logical address map shape of the memory array;
A storage device that changes the address map during a period from activation to deactivation of a circuit based on the first or second address. In a storage device that accesses a memory array in which memory cells are arrayed at a first address and a second address,
Map changing means for controlling the logical address of the memory array to change the logical address map shape of the memory array;
A storage device that changes the logical address map shape by changing the depth of at least one of the first and second addresses. In a storage device that accesses a memory array in which memory cells are arrayed at a first address and a second address,
Map changing means for controlling the logical address of the memory array to change the logical address map shape of the memory array;
A storage device comprising a control terminal for controlling the logical address. In a storage device that accesses a memory array in which memory cells are arrayed at a first address and a second address,
Map changing means for controlling the logical address of the memory array to change the logical address map shape of the memory array;
The memory array includes a plurality of banks, and a logical address map shape can be set for each bank.   6. The storage device according to claim 1, wherein the map changing unit changes the logical address map shape every time the memory array is activated. In a storage device that accesses a memory array in which memory cells are arrayed at a first address and a second address,
On the basis of access mode information that changes the logical address map shape of the memory array, a part of the external address is assigned to the first address or every cycle when an external address for access in the first address direction is input. Address control means for replacing with the second address;
An address configuration selection circuit that generates an address configuration selection signal according to the setting of the logical address map shape by a combination of a control signal to which the access form information is applied, or a plurality of control signals,
The address control means is a storage device that performs the replacement based on the address configuration selection signal. In a storage device that accesses a memory array in which memory cells are arrayed at a first address and a second address,
On the basis of access mode information that changes the logical address map shape of the memory array, a part of the external address is assigned to the first address or every cycle when an external address for access in the first address direction is input. Address control means for replacing with the second address;
A first signal generation circuit for generating a selection signal in the first address direction and a second signal for generating a selection signal in the second address direction based on an address configuration selection signal and inputting an external address. A storage device comprising: an address generation circuit having a switching unit for switching to a generation circuit. In a storage device that accesses a memory array in which memory cells are arrayed at a first address and a second address,
On the basis of access mode information that changes the logical address map shape of the memory array, a part of the external address is assigned to the first address or every cycle when an external address for access in the first address direction is input. Address control means for replacing with the second address;
A first signal generation circuit for inputting an external address and generating a selection signal in the first address direction based on an address configuration selection signal;
A storage device comprising: a second signal generation circuit for inputting an external address and generating a selection signal in the second address direction based on an address configuration selection signal. In a storage device that accesses a memory array in which memory cells are arrayed at a first address and a second address,
On the basis of access mode information that changes the logical address map shape of the memory array, a part of the external address is assigned to the first address or every cycle when an external address for access in the first address direction is input. Address control means for replacing with the second address;
The address control means is a storage device comprising a bonding or fuse ROM for storing the access mode information. In a storage device that accesses a memory array in which memory cells are arrayed at a first address and a second address,
On the basis of access mode information that changes the logical address map shape of the memory array, a part of the external address is assigned to the first address or every cycle when an external address for access in the first address direction is input. Address control means for replacing with the second address;
The address control means is a storage device comprising an externally rewritable ROM for storing the access mode information. In a storage device that accesses a memory array in which memory cells are arrayed at a first address and a second address,
An address that invalidates the external address or a part thereof for each cycle in which an external address for access in the first address direction is input based on access mode information that changes the logical address map shape of the memory array With invalidation means,
The address invalidating means includes a means for clamping an arbitrary address in order to vary the compression rate of decoding. In a storage device that accesses a memory array in which memory cells are arrayed at a first address and a second address,
An address that invalidates the external address or a part thereof for each cycle in which an external address for access in the first address direction is input based on access mode information that changes the logical address map shape of the memory array Invalidation means,
An address configuration selection circuit that generates an address configuration selection signal according to the setting of the logical address map shape by a combination of a control signal to which the access form information is applied, or a plurality of control signals;
The address invalidating means is a storage device that performs the invalidation based on the address configuration selection signal. In a storage device that accesses a memory array in which memory cells are arrayed at a first address and a second address,
An address that invalidates the external address or a part thereof for each cycle in which an external address for access in the first address direction is input based on access mode information that changes the logical address map shape of the memory array Invalidation means,
A first signal generation circuit for generating a selection signal in the first address direction and a second signal for generating a selection signal in the second address direction based on an address configuration selection signal and inputting an external address. A storage device comprising: an address generation circuit having a switching unit for switching to a generation circuit. In a storage device that accesses a memory array in which memory cells are arrayed at a first address and a second address,
An address that invalidates the external address or a part thereof for each cycle in which an external address for access in the first address direction is input based on access mode information that changes the logical address map shape of the memory array Invalidation means,
A first signal generation circuit for inputting an external address and generating a selection signal in the first address direction based on an address configuration selection signal;
A storage device comprising: a second signal generation circuit for inputting an external address and generating a selection signal in the second address direction based on an address configuration selection signal. In a storage device that accesses a memory array in which memory cells are arrayed at a first address and a second address,
An address that invalidates the external address or a part thereof for each cycle in which an external address for access in the first address direction is input based on access mode information that changes the logical address map shape of the memory array Invalidation means,
The address invalidating means includes a bonding or Fuse ROM for storing the access form information. In a storage device that accesses a memory array in which memory cells are arrayed at a first address and a second address,
An address that invalidates the external address or a part thereof for each cycle in which an external address for access in the first address direction is input based on access mode information that changes the logical address map shape of the memory array Invalidation means,
The address invalidating means is a storage device comprising an externally rewritable ROM that stores the access mode information. An address control method in a storage device for accessing a memory array in which memory cells are arrayed at a first address and a second address,
On the basis of access mode information that changes the logical address map shape of the memory array, a part of the external address is assigned to the first address or every cycle when an external address for access in the first address direction is input. Replace with the second address,
The access mode information is an address control method set during a standby period or simultaneously with an active operation. An address control method in a storage device for accessing a memory array in which memory cells are arrayed at a first address and a second address,
On the basis of access mode information that changes the logical address map shape of the memory array, a part of the external address is assigned to the first address or every cycle when an external address for access in the first address direction is input. Replace with the second address,
An address control method for controlling the number of activations of a sense amplifier in accordance with the logical address map shape. An address control method in a storage device for accessing a memory array in which memory cells are arrayed at a first address and a second address,
On the basis of access mode information that changes the logical address map shape of the memory array, a part of the external address is assigned to the first address or every cycle when an external address for access in the first address direction is input. Replace with the second address,
An address control method for varying a decoding compression rate in accordance with the logical address map shape. An address control method in a storage device for accessing a memory array in which memory cells are arrayed at a first address and a second address,
On the basis of access mode information that changes the logical address map shape of the memory array, a part of the external address is assigned to the first address or every cycle when an external address for access in the first address direction is input. Replace with the second address,
An address configuration selection signal corresponding to the setting of the logical address map shape is generated by a control signal to which the access form information is applied or a combination of a plurality of control signals, and the replacement is executed based on the address configuration selection signal Address control method.   22. The address control method according to claim 21, wherein the first and second addresses are generated by a common address generation means, and an output destination of the common address generation means is switched by the address configuration selection signal.   The address control method according to claim 21, further comprising first and second address generation means for generating the first and second addresses by an external address, and switching an input destination of the external address by the address configuration selection signal. An address control method in a storage device for accessing a memory array in which memory cells are arrayed at a first address and a second address,
Based on access mode information that changes the logical address map shape of the memory array, the external address or a part thereof is invalidated for each cycle in which an external address for access in the first address direction is input,
The access mode information is an address control method set during a standby period or simultaneously with an active operation. An address control method in a storage device for accessing a memory array in which memory cells are arrayed at a first address and a second address,
Based on access mode information that changes the logical address map shape of the memory array, the external address or a part thereof is invalidated for each cycle in which an external address for access in the first address direction is input,
An address control method for controlling the number of activations of a sense amplifier in accordance with the logical address map shape. An address control method in a storage device for accessing a memory array in which memory cells are arrayed at a first address and a second address,
Based on access mode information that changes the logical address map shape of the memory array, the external address or a part thereof is invalidated for each cycle in which an external address for access in the first address direction is input,
An address control method for varying a decoding compression rate in accordance with the logical address map shape. An address control method in a storage device for accessing a memory array in which memory cells are arrayed at a first address and a second address,
Based on access mode information that changes the logical address map shape of the memory array, the external address or a part thereof is invalidated for each cycle in which an external address for access in the first address direction is input,
An address configuration selection signal corresponding to the setting of the logical address map shape is generated by a control signal to which the access form information is applied or a combination of a plurality of control signals, and the invalidation is executed based on the address configuration selection signal Address control method.   28. The address control method according to claim 27, wherein the first and second addresses are generated by a common address generating means, and an output destination of the common address generating means is switched by the address configuration selection signal.   28. The address control method according to claim 27, further comprising first and second address generating means for generating the first and second addresses by an external address, and switching an input destination of the external address by the address configuration selection signal. In a system comprising storage means and control means for accessing and controlling the storage means,
The control means supplies occasional access form information to the storage means, and the access form information is supplied simultaneously with or before the start of access,
The storage means changes a logical address map form of a memory array in which memory cells are arrayed at a first address and a second address according to the access form information.   31. The system according to claim 30, wherein the control means supplies the access form information using one of address information, data, and code information based on a control signal. In a system comprising storage means and control means for accessing and controlling the storage means,
The control means supplies occasional access form information to the storage means, performs the supply of the access form information from code information by a control signal,
The storage means changes a logical address map form of a memory array in which memory cells are arrayed at a first address and a second address according to the access form information, and changes the code information to an edge of a pulse signal having a constant period. System to receive according to. The control means performs the supply of the access form information from code information by a control signal,
The system according to claim 30, wherein the storage means receives the code information in accordance with an edge of a pulse signal having a constant period.

Images