JPH05108471A - Memory device - Google Patents

Abstract

PURPOSE:To shorten cycle time at the time of continuously accessing adjacent pages in a memory space. CONSTITUTION:This system is provided with an up-counter 5 and a down- counter 6 as means which predict the addresses of a second block transfer access cycle continuing in a high-order address direction and a low-order address direction from an address given at a first block transfer access cycle, address comparators 7 and 8 as comparison means judging whether the address outputted from the prediction means is equal to the address outputted by a data processor 11, an effective signal generation device 9 as a means selecting DRAM 2 or 1 at high speed or low speed by the comparison means, and a selector 23. N- words from the head of a page given by the address of the second block transfer access cycle are transferred from high speed DRAM 2, and remaining words are transferred from low speed DRAM 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device connected to a data processing device having a block transfer function.

[0002]

2. Description of the Related Art In recent years, the demand for large-capacity, high-speed, low-cost memory has been increasing with the progress of computers. Among them, in the fields that require large memory,
A dynamic random access memory (hereinafter abbreviated as DRAM) is mainly used, but it is insufficient in terms of speed, especially in cycle time.

In particular, when block data transfer is performed, the access time of the first word accounts for a large proportion of the entire cycle time, and in order to improve this, a DRAM capable of high-speed access has recently appeared. But
The cost is quite high and it is only used for some memory devices.

Static random access memory
Since the minimum cycle time and the access time are equal to each other (hereinafter abbreviated as SRAM), the insufficient speed of the DRAM can be solved.

However, at present, DRAM is superior to SRAM in terms of cost reduction and large capacity, and the main memory device has not yet been composed of only SRAM.
Under such circumstances, there has been proposed a device that accelerates the response of the memory device to the access of the data processing device at the lowest possible cost.

An example of a conventional memory device will be described with reference to the block diagram shown in FIG. 4 and the timing chart shown in FIG. In this example, a nibble-mode DRAM with the same access time is used to form a 2-bank memory device.

In the nibble mode DRAM, a maximum of 4 bits (nibbles) of data can be accessed for a set of row address and column address. In FIG. 4, 3 is DRAM2
An address multiplexer for time-divisionally providing addresses to 4 and 25 as row addresses (page addresses) and column addresses, 4 is a memory controller that outputs signals for controlling the timing of reading and writing of DRAMs 24 and 25, and 11 is block transfer A data processing device having a function, 12 is an address bus of the memory device, 13 is a data bus of the memory device, 23 is a selector for selecting data of bank # 0 or bank # 1, 24 is a DRAM of bank # 0, 25 Is D in bank # 1
RAM, 26 is a D latch for holding data from the DRAM 24 of the bank # 0, 27 is a CAS # 0 signal for latching the column address of the DRAM 24, 28 is a CAS # 1 signal for latching the column address of the DRAM 25, 29 is DRA
R to latch the row address of M24 and DRAM25
AS # 0 signal, 31 is a bank switching signal.

First, in the read cycle, in the first transfer cycle, the row address 1 (see FIG. 4) is sent from the memory controller 4 to the selected memory device. DR
After setting up AM24 and DRAM25, RAS # 0
The signal 29 is set to low level to start access. When the row address has passed a predetermined hold time, the data processing device 11 sends a column address 1 (see FIG. 4), and then C
The AS # 0 signal 27 and the CAS # 1 signal 28 are set to the low level. In this way, the address from the memory controller 4 is latched and the access in the DRAM 24, 25 is started.

At this time, access is simultaneously started to both bank # 0 and bank # 1, but first the bank # 0 is selected by the selector 23. When bank # 0 is activated,
DR of bank # 0 by setting the CAS # 0 signal 27 to high level
The AM24 can be put in nibble mode.

When the data of the bank # 0 appears on the data bus 13, the memory controller 4 outputs the bank switching signal.
By setting 31 to the low level, the selector 23 selects the data of the bank # 1. Bank # 1 DRAM
Since 25 is being accessed at the same time as the DRAM 24 in bank # 0, the data in bank # 1 is valid and is sent to the data processor 11.

When the data processor 11 receives the data in the bank # 1, the CAS # 1 signal 28 goes high to precharge the DRAM 25 in the bank # 1 and enter the nibble mode. At this time, the bank switching signal 31 also goes high, and the system is ready to accept the data of bank # 0. When the data processor 11 is ready to receive the next data and the bank # 0 is selected by the selector 23, the DRAM 24 of the bank # 0 outputs the data accessed in the nibble mode onto the data bus 13.

When the reading of the bank # 0 is completed, the bank # 1 is selected by the selector 23. Bank #
1 has already completed nibble mode access,
The data is output on the data bus 13. In this way, one cycle of data transfer is completed, and the memory controller 4 precharges the RAS # 0 signal 29, CAS # 0 signal 27, and CAS # 1 signal 28 for the next cycle.

In the write cycle, the D latch 26 is used,
When the data in bank # 0 is received and the DRAM 24 in bank # 0 cannot be accessed yet, the data is held.
When the data of the bank # 1 is also output to the data bus 13, the data of the bank # 0 and the bank # 1 are simultaneously written by setting the CAS # 0 signal 27 and the CAS # 1 signal 28 to the low level at the same time.

[0014]

In the configuration of the above-mentioned conventional example, the memory is divided into two banks and data is alternately read and written from the bank # 0 and the bank # 1 to increase the precharge time and the cycle at the time of block transfer. I was improving my time.

However, in the conventional configuration, the cycle time can be improved only by accessing within the same page, and when the adjacent pages are continuously accessed, a new row address must be output, and therefore the speed is increased. Had been an obstacle for.

Further, in the case of a block transfer cycle, unless the access time of the first word is improved, the cycle time cannot be greatly shortened. However, if a high speed DRAM is used to achieve this, the memory device becomes very difficult. It had the drawback of becoming expensive.

The present invention has been made in view of the above conventional problems, and an object of the present invention is to provide a memory device that shortens the cycle time when consecutively accessing adjacent pages of a memory space.

[0018]

According to the present invention, means for predicting an address in a second block transfer access cycle that is continuous in an upper address direction and a lower address direction from an address given in a first block transfer access cycle. And fast NRA from the top of the page given by the address of the second block transfer access cycle.
Transfer from M, transfer remaining words from slow DRAM,
It is characterized in that the cycle time is improved when consecutively accessing adjacent pages.

[0019]

According to the present invention, the cycle time for continuous access to adjacent pages can be shortened, and the performance equivalent to that when the main memory is composed of only high-speed DRAM can be realized at low cost.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. 1, 1 is a low-speed DARM that constitutes the main memory, 2 is a high-speed DRAM that constitutes the first word of each page of the main memory, and 3 is a row address (page address) and a column address as addresses to DARM 1 and 2 respectively. Address multiplexer for giving division, 4 is DARM1
The memory controller 5 outputs a signal for controlling the timing of reading and writing 2 and 2, and the like, and 5 is an up counter for a page address that adds 1 to the row address given in the first block transfer cycle, and 5A is an up counter output. 6 is a page address down counter that subtracts 1 from the row address given in the first block transfer cycle.
6A is a down counter output. Reference numeral 7 is an address comparator for determining whether or not the row address given in the second block transfer cycle is an adjacent row address on the upper side from the row address given in the first block transfer cycle. It is a signal. Reference numeral 8 is an address comparator for determining whether or not the row address given in the second block transfer cycle is an adjacent row address on the lower side from the row address given in the first block transfer cycle, and 8A is a match. It is a signal. 9 is a high speed DRAM for the first word
2 is a valid signal generator that outputs a timing signal for reading and writing to 2 and 9A is a valid signal. Reference numeral 11 is a data processing device having a block transfer function, and 30 is a RAS # 1 signal for latching the row address of the high speed drum 2. In addition, the same parts as those in FIG. 4 are designated by the same reference numerals, and the description thereof will be omitted.

In the embodiment shown in FIG. 1, of the addresses output from the data processing device 11, A20 to A11 are connected to the memory device, the main memory accessed by the data processing device 11 is 1 MB, and the data width is 16 bits (1 word). Also, the case where the nibble mode DRAM is used and the leading word is a high speed DRAM (N = 1) will be described.

First, FIG. 2 is a memory map showing the structure of the memory space in one embodiment of the present invention. DR in general
The AM gives access by giving an address in a time division manner. For example, in the case of 1 M word DARM, the necessary 20-bit address is multiplexed and the first 10 bits are given as a row address, and then the remaining 10 bits are given as a column address.

The memory space given by the row address is called a page (exemplified by page0 to 1024). Here, since the page address is given by A20 to A11, there are 1K pages of 1K bytes per page. Also, N
= 1, so the first word of each page is high-speed DRAM
2 and the remaining words are placed in slow DARM1. Therefore, the portion constituted by the high-speed DRAM 2 needs only 16K bits (2K bits).

The operation of the memory device configured as described above will be described. First, since the memory device is accessed from the data processing device 11 in the read cycle, the block address 1 of the first transfer cycle is output (not the start address of the page). At this time, the row address is given to the DARM 1 by the address multiplexer 3. A row address obtained by adding 1 to the row address is given to the address comparator 7 by the counter output 5A of the page address up counter 5, and the address comparator 8 is given by the counter output 6A of the page address down counter 6. A row address obtained by subtracting 1 from the row address is given.

Once DRAM 1 is set up, RAS
The # 0 signal 29 is set to low level to start access. When the row address has passed a predetermined hold time, the address multiplexer 3 supplies the column address to the DRAM 1. After that, the memory controller 4 causes the DRAM
1 is supplied with the CAS # 0 signal 27, and the CAS # 0 signal 27
A continuous column address is generated in the DRAM 1 by toggling 27.

In this way, continuous access within the same page is possible. Since the row address does not change as long as the same page is accessed, the match signals 7A and 8A from the address comparators 7 and 8 are false.
(High level).

When the block address of the second transfer cycle is output from the data processing device 11 and the row address is the row address adjacent to the row address of the first cycle, the address comparator 7 or the address comparator 8 The coincidence signals 7A and 8A are set to true (low level).

For example, when the row address of the second transfer cycle is an adjacent row address on the upper side of the row address of the first transfer cycle, the address comparator 7 outputs a coincidence signal 7A and the lower side of the row address. If the row addresses are adjacent to each other, the address comparator 8 outputs the coincidence signal 8A. The valid signal generator 9 receives the coincidence signals 7A and 8A from the address comparator 7 or the address comparator 8,
The valid signal 9A is output to the memory controller 4. As a result, the memory controller 4 stores the R in the DRAM 2.
Send AS # 1 signal 30. After this, the memory controller 4
When the CAS # 1 signal 28 is applied to the DRAM 2 from
The RAM 2 outputs the data (first word) onto the data bus 13. The valid signal 9A becomes false (high level) after the time required to output the first word has passed, and the words after that become DRA.
It is read from M1.

The operation of the memory device will now be described in more detail with reference to the timing chart shown in FIG. Figure 3
Shows the flow of time in the right direction in the horizontal direction and shows the movement of signals in the vertical direction.

First, in the read cycle, the block transfer address is output from the data processor 11, and the row address is given to the DRAM 1 by the memory controller 4. At this time, the row address and the row address given by the page address up counter 6 are compared by the address comparator 7. If the comparison results do not match,
The valid signal 9A remains false (high level), and the memory controller 4 sets the RAS # 0 signal 29 to the low level to start access to DARM1 and sets the switching signal 31 to the low level to cause the selector 23 to perform DRA.
Select the data from M1. When the row address has passed the hold time, the memory controller 4 gives the column address to DARM1, and then the CAS # 0 signal 27
To low level. Thus, the memory controller 4
The address from is latched and access in the DRAM is started.

When the access time has elapsed and the read data from DARM1 appears on the data bus 13, CAS #
The 0 signal 27 is set to high level to prepare for the next nibble mode access. After the CAS hold time has elapsed, CAS # 0 again
The signal 27 is set to low level to start nibble mode access. Since 4 words are transferred in one block transfer,
By toggling the CAS # 0 signal 27 for four cycles, four words of word 0, word 1, word 2 and word 3 are continuously read from the DRAM 1.

Next, the data processing device 11 outputs the second block transfer address, and the memory controller 4 gives the row address to the DRAM 1. At this time, if the row address is equal to the row address of the adjacent page on the upper side of the row address given in the previous transfer cycle,
The coincidence signal 7A is sent from the address comparator 7 to the valid signal generator 9, and as a result, the valid signal 9A of the valid signal generator 9 becomes low level.

Therefore, the memory controller 4 receives the valid signal 9A and gives the RAS # 1 signal 30 to the DARM2 so that the first word of the second transfer cycle is the DARM.
Access to the DARM2 is started as read from No. 2.

Further, the switching signal 31 is set to the high level and the selector 23 selects the data from the DARM2. Thereafter, the CAS # 1 signal 28 is applied to the DARM2, and when the access time elapses, data appears on the data bus 13. At the same time, RAS to DARM1
The # 0 signal 29 goes low, and preparations are made to read out the words after the first word.

Since DARM2 has a faster access time than DARM1, the leading word appears on the data bus 13 faster than in the first transfer cycle. After the head word is read from the DRAM2, the RAS # 1 signal 30 of the DARM2 is set to the high level. In addition, the CAS # 0 signal 27 to the DRAM 1
To low level to prepare to read the second word. Then, as in the first transfer cycle, the CAS
By toggling the # 0 signal 27 for 3 cycles,
Three words of word 1, word 2, and word 3 are continuously read from DARM1.

Also in the write cycle, data is written in the same sequence as in the read cycle except that the write signal is set to the low level.

As described above, according to the present embodiment, the first word of each page of the memory device is composed of the high-speed DRAM, the remaining words are composed of the low-speed DRAM, and is given in the first block transfer access cycle. By providing means for predicting the addresses of the second block transfer access cycle that is continuous in the upper address direction and the lower address direction from the obtained address, the head word can be read from the high speed DRAM. Therefore, when the adjacent pages are continuously accessed, the cycle time can be greatly improved.

[0039]

As described above, in the memory device of the present invention, N words from the top of the page are composed of a high-speed DRAM,
A high-speed memory device can be realized by configuring the remaining (M−N) words in the low-speed DRAM and reading / writing N words from the beginning in the block transfer cycle to the high-speed DRAM. In addition, no large-scale peripheral circuits are required, high-speed DRAM is used only for the minimum required parts, and the rest is large-capacity low-speed DR
By using AM, a large-capacity memory device can be realized at low cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a memory map showing a configuration of a memory space according to an embodiment of the present invention.

FIG. 3 is a timing chart showing the operation of FIG.

FIG. 4 is a block diagram of a memory device in a conventional example.

FIG. 5 is a timing chart showing the operation of FIG.

[Explanation of symbols]

1 ... Low speed DRAM, 2 ... High speed DRAM, 3 ... Address multiplexer, 4 ... Memory controller, 5 ...
Up counter, 6 ... Down counter, 7, 8 ... Address comparator, 9 ... Effective signal generating device, 11 ... Data processing device, 12 ... Address bus, 13 ... Data bus, 23
... Data selector, 27 ... CAS # 0 signal, 28 ... CA
S # 1 signal, 29 ... RAS # 0 signal, 30 ... RAS # 1
Signal, 31 ... Bank switching signal.

Claims (2)

[Claims] 1. In a memory device for outputting data according to an address output from a data processing device having a block transfer function, N words from the beginning in the same page composed of M words having the same upper address are fast dynamic random. The remaining (M−N) words are composed of an access memory, and the remaining (M−N) words are a set of memories composed of a dynamic random access memory slower than the high speed dynamic random access memory and an address given in the first block transfer access cycle. And means for predicting the addresses of the second block transfer access cycles consecutive in the upper address direction and the lower address direction, and the address output from the address predicting means is equal to the address output by the data processing device. A comparison means to determine whether Data selecting means for selecting whether to output the leading N words from the high-speed dynamic random address memory or the low-speed dynamic random access memory, depending on whether or not the generated address matches or does not match the address output from the data processing device. Is provided, and when accessing consecutive pages, N
A memory device characterized by transferring words from a high speed dynamic random access memory. 2. An address predicting means is provided with a means for obtaining a value obtained by adding 1 to a page address given in the first block transfer access cycle and a means for obtaining a value obtained by subtracting 1 from the page address. The memory device according to claim 1, wherein the memory device comprises: