JPS6314434B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to an access method that reduces memory read time when accessing a memory space.

(2) Prior art and problems Space expansion registers (commonly called bank registers) are used to effectively utilize the memory space of electronic computers.
As shown in FIG. 1, a plurality of memory spaces are switched and used according to the values set in the bank registers. That is, the first 16KW of the addressed memory space is used as the common part CM, the remaining 48KW is used as banks BNK0, BNK1, etc., and the bank to be used is specified by the value of the bank register BKR to switch banks. Access to the memory is performed by specifying an address within the bank using address information provided by the processor. A circuit for accessing such a memory has conventionally been constructed as shown in FIG. That is, in FIG. 2, the common part and banks BNK0, BNK1, etc. are switched using the upper 2 bits of the 16 bits of address information given by the processor, and when the upper 2 bits are "00", the common part CM is accessed. Then, 16KW of array MA0, which is the common part of the memory array, is accessed. When the upper bits of the address are other than “00”, the contents of bank register BKR and the upper bits of the address are decoded together by the decoder DEC,
Specify memory arrays MA1 to MAn. The correspondence between the memory arrays and the above-mentioned BNK0, BNK1, . . . is that memory arrays MA1 to MA3 correspond to BNK0, and so on. When using dynamic memory, the access signals are RAS (row access signal),
Two types of CAS (column access signals) (2nd to 15th bits of the above address information, the upper side is the row address,
(lower side indicates column address) are applied separately,
The address is determined by the fall timing of the RAS and CAS signals, and is latched into the designated memory by the decoder output. (The memory selection signal of the decoder output is punched by the RAS/CAS timing signal to create the RAS and CAS signals.) A time chart of each signal in the above operation is shown in FIG. As mentioned above, in the conventional access circuit, the top two address information on the address bus
Logic circuit for determining whether the contents of bank register BNK are valid or invalid by checking the bits.
LG is required, and if it is not after the address judgment time ADT from when the signal passes through the gate circuit and is input to the decoder circuit, and the decoding time DCT from when the decoding result is output from the decoder circuit, memory selection is required. It is not possible to output the signal RAS/CAS timing signal, which increases the time delay in memory access.

(3) Object of the Invention An object of the present invention is to provide an access method that can improve the above-mentioned drawbacks, eliminate time delay when accessing memory space, and shorten memory access time.

(4) Structure of the invention The structure of the present invention to achieve the above object is as follows:
The memory space is divided into one common part CM and multiple banks.
Divided into BNK0 and BNKn and bank register
In a memory access method in which memory is accessed while specifying a bank using BKR, the common section and the plurality of banks constituting the memory space are constituted by a dynamic memory composed of a plurality of memory arrays MA0 to MAn. , a selection bit for selecting the common section and the plurality of banks is inputted from the address information given by the processor, and the memory array MA corresponding to the common section is inputted.
A decoder R-DEC1 that outputs a signal for selecting the row address of 0, and a bank register BKR in which information specifying the plurality of banks is set.
and a decoder R-DEC which receives the contents of the bank register BKR and the selection bit and outputs a signal for selecting a row address of the memory arrays MA1 to MAn corresponding to the plurality of banks.
2, a logic circuit LG for gating the output of the signal of the bank register BKR according to the information of the selection bit, and the contents of the bank register BKR are inputted via the logic circuit LG;
The selection bit is input and all memory arrays
Equipped with a decoder C-DEC for outputting a signal for selecting the column address of MA0 to MAn,
The purpose of this method is to access the memory while specifying the memory array using the output signals from each of the decoders.

(5) Embodiment of the invention FIG. 4 is a block diagram showing an embodiment of the invention. In FIG. 4, the same symbols as in FIG. 2 indicate the same things, and R-DEC1 outputs an output signal when the upper two bits of the address designation bits are input and the state of the two bits is "00" to output the memory array.
R-DEC2, a decoder (using memory array MA0 as a common part) for selecting the row address RAS timing signal of MA0, receives the contents of bank register BKR and the upper two bits of the address, A decoder for selecting the row address RAS timing signal of the number (arrays other than memory array MA0 are used as banks), C-DEC selects the column address CAS of each bank according to the contents of the bank register BKR.
3 shows a decoder for selecting timing signals. The upper two bits of the address information given by the processor are decoded by the decoder R-DEC1 to generate a signal RAS0 for row address selection. In addition, the 4 bits of bank register BKR and the upper 2 bits of the address are decoder R-DEC2.
Signal for row address selection decoded by
Generate RAS1 to RASn. When generating the signal RAS for row address selection, a gate circuit that gates the output of bank register BKR when the upper two bits of the address information are "00" is not used, unlike in the past, so it can be decoded without time delay. , and the time for row address selection is accelerated. However, because the gate circuit is omitted, R-DEC1 and R-DEC2 are
Depending on the combination of input signals of DEC2, both may output signals at the same time, but the signal for column address selection, which will be described later, will be output from the logic circuit LG, which will be described later.
This does not affect memory address selection. Signal CAS for selecting column address
is decoded by the decoder C-DEC via the logic circuit LG which judges the upper two bits of the address information and determines whether the contents of the bank register BKR are valid or invalid, so its output is the row address. The signal for selection is becoming slower than RAS. Therefore, even if all the output sides of the memory array are dot-ORed, the column address signal selects one memory array, so the access operation can be performed normally. (Because the memory output is enabled by the column address selection signal CAS).
FIG. 5 is a time chart for FIG. 4 in which the column address selection signal RAS is applied to the decoder R-
Because it can be obtained early with DEC1 and R-DEC2,
There is no time delay for determining the upper bits of address information and generating a valid address, enabling high-speed memory access. Since no more than two memory accesses are activated by the row address selection signal RAS, an increase in the required power has little effect. Even if the row address selection signal RAS decoding circuit is removed and the row address signal is input to all memory arrays at the same time, the column address selection signal
Since the selection is made by CAS, logically normal operation is possible and the time delay of the address judgment circuit can be saved, but all memories are activated by the row address selection signal, and the power consumption of the entire memory is It becomes huge. Therefore, a decoder circuit that generates a row address selection signal is necessary.

(6) Effects of the Invention As described above, according to the present invention, there is no time delay when accessing the memory space, making it possible to shorten the access time.

[Brief explanation of the drawing]

Figure 1 is an explanatory diagram of conventional memory access, Figure 2
3 is a diagram showing the configuration of a conventional memory access circuit, FIG. 3 is a time chart of FIG. 2, FIG. 4 is a diagram of an embodiment of the present invention, and FIG. 5 is a time chart of FIG. 4. CM...common section, BNK0~BNK1...bank,
BKR...Bank register, MA0 to MAn...Memory array, R-DEC1, R-DEC2...Row address selection signal decoder, C-DEC...Column address selection signal decoder, LG...Logic circuit.

Claims (1)

[Claims] 1. A memory space is divided into one common part CM and a plurality of banks BNK0 to BNKn, and bank registers are
In a memory access method in which memory is accessed while specifying a bank using BKR, the common section and the plurality of banks constituting the memory space are constituted by a dynamic memory composed of a plurality of memory arrays MA0 to MAn. , a decoder that receives a selection bit for selecting the common section and the plurality of banks from address information given by the processor, and outputs a signal for selecting a row address of the memory array MA0 corresponding to the common section. R-DEC1, a bank register BKR in which information specifying the plurality of banks is set, and the contents of the bank register BKR and the selection bit are input, and the memory arrays MA1 to MAn corresponding to the plurality of banks are input. Decoder R-DEC2 that outputs a signal for selecting a row address
and a logic circuit LG for gating the output of the signal of the bank register BKR according to the information of the selection bit;
At the same time as the contents of BKR are input, the selection bit is input, and all memory arrays MA0 to
A memory access method comprising a decoder C-DEC for outputting a signal for selecting a column address of MAn, and accessing the memory while specifying a memory array using the output signals from each of the decoders.