JPH07141870A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To increase operational speed with simple constitution by latching a signal with an output of a decoding circuit to which an output signal of an input buffer taking in plural input signals synchronizing with a clock signal is supplied as it is and a required internal clock. CONSTITUTION:A row address strobe signal/RAS of an external input signal, a column address strobe signal/CAS, a write enable signal/RE, and a chip selector signal/CS are respectively supplied to corresponding input buffers 3-6, and output of the buffers is directly supplied to a mode decoder 7. And an output of the circuit 7 is latched by a latch circuit 8 which is activated by an internal clock ICLK synchronizing with a clock signal CLK. By using this constitution in which an input signal is taken in and decoded by making use of a setup time and a holding time for a clock signal of this input signal, decode deciding timing is made quick, then a semiconductor memory in which a circuit is simple and operational speed is increased is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example a synchronous DRAM (Dynamic R).
and Access Memory (dynamic random access memory).

[0002]

2. Description of the Related Art A so-called synchronous D whose operation is synchronized in accordance with a clock signal input from an external terminal.
There is RAM. For such a synchronous DRAM, for example, "HM5216800, HM5416800" issued by Hitachi, Ltd. on January 18, 1993.
Series Data Book ”.

[0003]

[Problems to be Solved by the Invention] Conventional Synchronous D
The RAM includes the input buffers 3 to 3 as illustrated in FIG.
Control signals / RAS, / CA fetched through 6
S, / WE, and / CS are held in the latch circuits 10 to 13 and supplied to the decoder circuit 7 that makes a mode determination. The latch circuits 10 to 13 use the clock signal CLK
Internal clock signal IC through input buffer 1 for receiving
The control signals thus fetched are latched in synchronization with LK. The operation of the input buffer 1 is validated by the internal clock enable signal ICKE fetched through the input buffer 2.

In the mode decision circuit as described above, since the signal inputted to the decoder circuit 7 is the latch signal, it seems that stable operation can be expected at first glance. However, as shown in the timing diagram of FIG. 9, the input signals (/ RAS, / CAS, / W are generated by the internal clock signal ICLK.
(E, / CS) is determined and then the mode determination is delayed because of decoding, and the output timing variation in the latch circuits 10 to 13 and the input to the decoder circuit 7 occur. There is a possibility that a whisker-like noise may be generated in the mode determination output due to a signal delay and a signal delay inside the decoder circuit 7 including a plurality of stages of logic gates. The actual mode determination becomes slower by providing a latch circuit so as not to respond to it. With the increase in the speed of synchronous DRAM, the delay of the above mode determination cannot be ignored, and the load on the address selection circuit and the sense amplifier, which are responsible for the actual memory access, becomes large, and the current consumption increases for the speed increase. The problem arises.

An object of the present invention is to provide a semiconductor memory device which realizes high speed with a simple structure. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, the output signals of the plurality of input buffers for respectively capturing the signals input from the plurality of external terminals are directly input to the decoder circuit, and the output signals of the decoder circuits are latched by the internal clock signal captured by the clock buffer.

[0007]

According to the above-mentioned means, since the input signal is taken in and decoded by utilizing the setup time of the input signal, the decoding confirmation timing can be made faster accordingly.

[0008]

FIG. 6 shows a block diagram of an embodiment of a synchronous DRAM to which the present invention is applied. The circuit elements forming each block in the figure are not particularly limited, but known MOSFETs (metal oxide semiconductor field effect transistors. In this specification, MOSFETs are collectively referred to as insulated gate field effect transistors). It is formed on the surface of one semiconductor substrate such as single crystal silicon by the manufacturing technology of integrated circuits.

The synchronous DRAM of this embodiment has 2
A plurality of banks BANK0 and BANK1 are provided, and each of these banks includes a memory array occupying most of the layout area, a row address decoder RD, a sense amplifier SA, and a column address decoder CD which are direct peripheral circuits. including.

Each of the memory arrays MARY forming the banks BANK0 and BANK1 has a plurality of word lines arranged in parallel in the vertical direction in the figure and a plurality of complementary bit lines arranged in parallel in the horizontal direction. including. At the intersections of these word lines and complementary bit lines, a large number of dynamic memory cells each composed of an information storage capacitor and an address selection MOSFET are arranged in a grid pattern.

The word lines forming the memory arrays MARY of the banks BANK0 and BANK1 are respectively coupled to the corresponding row address decoders RD and are alternatively set in the selected state. The row address decoder RD removes the most significant bit from the row address buffer RB i
The bit internal address signals X0 to Xi-1 are commonly supplied, and internal control signals RG0 and RG1 (not shown) are respectively supplied from the timing generation circuit TG.

The row address buffer RB is supplied with internal address signals P0 to Pi from the pre-address buffer PB and refresh address signals R0 to Ri from the refresh address counter RFC. The row address buffer RB further includes a timing generation circuit T
G to internal control signal RL (second internal control signal) and R
F is supplied.

An internal control signal RC is supplied to the refresh address counter RFC from the timing generation circuit TG. The internal control signals RG0 and RG1 are selectively formed according to the bank selection signals BS0 and BS1 supplied from the bank selection circuit BS to the timing generation circuit TG, and these bank selection signals BS0 and BS1 are supplied from the row address buffer RB to the banks. It is selectively formed in accordance with the most significant bit internal address signal Xi supplied to selection circuit BS. The row address buffer RB is a row address decoder RD of the banks BANK0 and BANK1.
And the refresh address counter RFC are optimally arranged so that the distance between them and the refresh address counter RFC is as short as possible.

In the synchronous DRAM, the operation thereof is synchronized according to the clock signal CLK, and the X address signals AX0 to AXi used for row selection of the memory array and the Y address signals AY0 to AYi used for column selection are common. The address multiplex method is adopted in which time-divisional input is performed via the external terminals, that is, the address input terminals A0 to Ai. As will be described later, the X address signal A for designating the row address RAD in synchronization with the first rising edge of the clock signal CLK is applied to the address input terminals A0 to Ai.
X0 to AXi are input, and Y address signals AY0 to AYi designating the column address CAD are input in synchronization with the next rising edge of the clock signal CLK.

The X address signal A is supplied to the pre-address buffer PB via the address input terminals A0 to Ai.
X0 to AXi and Y address signals AY0 to AYi are supplied, and an inverted internal control signal PLB (first internal control signal) is supplied from the timing generation circuit TG. The pre-address buffer PB is arranged close to the address input terminals A0 to Ai, and is optimally arranged so that the distance between these address input terminals is as short as possible.

The inverted internal control signal PLB is selectively set to the effective level, that is, the low level in response to the change of the clock signal CLK to the effective level, that is, the high level. Also,
The internal control signal RL has already been changed to the row address strobe signal / R when the clock signal CLK changes to the high level.
Although AS is set to the effective level, that is, the low level, it is selectively set to the effective level, that is, the high level.
The time from the rise of the clock signal CLK to the high level to the rise of the internal control signal RL is set with a relatively long margin. The internal control signal RF is selectively set to a high level when the synchronous DRAM is in the refresh mode, and the internal control signal RC is synchronous D.
When the RAM is in the refresh mode, it is set to the high level at a predetermined timing.

The pre-address buffer PB has X address signals AX0 to AXi or Y address signals AY0 to AYi input via address input terminals A0 to Ai when the synchronous DRAM is in a normal operation mode.
Is received and held in response to the falling change of the inverted internal control signal PLB to the low level, and is transmitted to the row address buffer RB and the column address buffer CB as the internal address signals P0 to Pi. The refresh address counter RFC is a synchronous DRA.
Internal control signal R when M is in refresh mode
A stepping operation is performed according to C to form refresh address signals R0 to Ri.

In the row address buffer RB, the synchronous DRAM is set to the normal operation mode and the internal control signal RF is set.
Is low level, the pre-address buffer PB
From the internal address signals P0 to Pi, that is, X
Address signals AX0 to AXi are fetched and held according to internal control signal RL. When the synchronous DRAM is in the refresh mode and the internal control signal RF is set to the high level, the refresh address signals R0 to Ri supplied from the refresh address counter RFC are fetched and held according to the internal control signal RL. And
Based on these X address signals or refresh address signals, internal address signals X0 to Xi are formed. Of these, the most significant bit internal address signal Xi is supplied to the bank selection circuit BS and the other internal address signals X0 to X0.
Xi-1 is commonly supplied to the row address decoders RD of the banks BANK0 and BANK1.

The bank selection circuit BS decodes the internal address signal Xi of the most significant bit supplied from the row address buffer RB and outputs the corresponding bank selection signal BS0.
And BS1 are selectively formed, and the timing generation circuit TG
And the data input / output circuit IO. Also, the row address decoder RD of the banks BANK0 and BANK1
Are selectively activated by the internal control signal RG0 or RG1 being set to a high level, and the internal address signal X
0 to Xi-1 are decoded and the corresponding memory array M
The ARY word line is selectively set to the high level selected state.

The complementary bit lines forming the memory array MARY of the banks BANK0 and BANK1 are coupled to the corresponding sense amplifier SA. These sense amplifiers S
A corresponding column address decoder CD supplies a bit line selection signal of a predetermined bit to A, and a timing generation circuit TG supplies an internal control signal PA0 or PA (not shown).
1 is supplied respectively. Internal control signals PL0 and PL
1 is selectively formed in accordance with bank selection signals BS0 and BS1.

The sense amplifiers SA of the banks BANK0 and BANK1 respectively include a plurality of unit circuits provided corresponding to the complementary bit lines of the corresponding memory array MARY, and each of these unit circuits has a pair of CMOs.
It includes a unit amplifier circuit formed by cross-connecting S inverters and a pair of switch MOSFETs. Of these, the unit amplifier circuit of each unit circuit is selectively supplied with the power supply voltage and the ground potential of the circuit via a pair of drive MOSFETs that are selectively turned on in accordance with the corresponding internal control signal PA0 or PA1. To be done. Switch MOSFE of each unit circuit
The gates of T are commonly coupled for every 16 pairs, and the corresponding bit line selection signal is commonly supplied from the corresponding column address decoder CD.

As a result, the unit amplifying circuit forming each unit circuit of the sense amplifier SA has the corresponding internal control signal P.
When A0 or PA1 is set to the high level, it is activated simultaneously and selectively, and the corresponding memory array MAR
A minute read signal output from a plurality of memory cells coupled to a selected word line of Y via a corresponding complementary bit line is amplified to be a high level or low level binary read signal. The switch MOSFET pairs forming each unit circuit of the sense amplifier SA are selectively turned on by 16 pairs when the corresponding bit line selection signal is set to the high level, and the corresponding 16 pairs of the corresponding memory array MARY are set. Complementary bit line and complementary common data line CD0
0 * -CD015 * or CD10 * -CD115 *
(Here, for example, the non-inverted common data line CD00T and the inverted common data line CD00B are collectively referred to as a complementary bit line CD.
It is expressed by adding * like 00 *. Further, a non-inverted signal or the like that is selectively set to a high level when it is validated is indicated by adding T to the end of its name. The same applies below)
And are selectively connected.

The column address decoder C of the banks BANK0 and BANK1 has a column address buffer C.
Internal address signals Y0 to Yi of i + 1 bits are commonly supplied from B, and corresponding internal control signals CG0 and CG1 (not shown) are respectively supplied from the timing generation circuit TG. Further, the column address buffer CB is supplied with the internal address signals P0 to Pi of i + 1 bits from the pre-address buffer PB, and the timing generation circuit TG is supplied.
Supplies the internal control signal CL (third internal control signal). The internal control signals CG0 and CG1 are selectively formed according to the address signal of the most significant bit, that is, the bank selection signals BS0 and BS1 that are input again in synchronization with the column address strobe signal CASB. Also,
The column address buffer CB is optimally arranged so that the distance between the column address decoders CD of the banks BANK0 and BANK1 is as short as possible.

In this embodiment, the internal control signal CL
Is selectively set to a valid level or high level in response to the column address strobe signal / CAS being already set to a valid level or low level when the clock signal CLK changes to a high level.
Internal control signal CL from the rise of LK to high level
The time to rise is set with a comparatively long margin. The synchronous DRAM has a burst mode in which read data of a plurality of memory cells coupled to a selected word line are continuously output, and a column address buffer C
B includes a burst counter for sequentially designating column addresses corresponding to a series of memory cells in this burst mode.

The column address buffer CB has an internal address signal P0 supplied from the pre-address buffer PB.
To Pi, that is, Y address signals AY0 to AYi are fetched and held according to the internal control signal CL, and internal address signals Y0 to Y are obtained based on these Y address signals.
i is formed and supplied to the column address decoder CD of each bank. When the synchronous DRAM is set to the burst mode, the stepwise operation is performed by using the fetched Y address signals AY0 to AYi as the head addresses to specify the column addresses of a series of memory cells to be continuously accessed.

The column address decoders CD of the banks BANK0 and BANK1 are selectively activated by setting the corresponding internal control signal CG0 or CG1 to high level. In this operating state, each column address decoder CD decodes the internal address signals Y0 to Yi supplied from the column address buffer CB and selectively sets the corresponding bit line selection signal to the high level.

Complementary common data lines CD00 * to CD015 * and CD10 * to C in which 16 designated complementary bit lines of the memory array MARY forming the banks BANK0 and BANK1 are selectively connected.
D115 * is coupled to data input / output circuit IO. The data input / output circuit IO is supplied with bank selection signals BS0 and BS1 from the bank selection circuit BS and internal control signals MU and ML from the timing generation circuit TG. The internal control signal MU is selectively set to the high level when the data mask signal DQMU is set to the high level at the rising edge of the clock signal CLK,
The internal control signal ML is selectively set to high level when the data mask signal DQML is set to high level. The bank selection signals BS0 and BS1 are selectively formed according to the address signal of the most significant bit input in synchronization with the column address strobe signal CASB.

The data input / output circuit IO includes complementary common data lines CD00 * to CD015 * and CD10 * to CD.
It includes 32 write amplifiers and 32 main amplifiers corresponding to 115 *, and 16 data input buffers and 16 data output buffers, respectively. Of these, the output terminals of the respective write amplifiers and the input terminals of the main amplifier are connected to corresponding complementary common data lines CD00 * to CD01.
5 * or CD10 * to CD115 are commonly linked. Also, the input terminals of each write amplifier are commonly coupled to the output terminals of the corresponding two data input buffers, and the input terminals of each data input buffer are coupled to the corresponding data input / output terminals D0 to D15.

The output terminals of each main amplifier are commonly connected to the input terminals of the corresponding two data output buffers.
The output terminal of each data output buffer is coupled to the corresponding data input / output terminal D0-D15. Bank BANK0
The bank selection signal BS0 is commonly supplied to the write amplifiers and the main amplifiers corresponding to, and the bank selection signal BS1 is commonly supplied to the write amplifiers and the main amplifiers corresponding to the bank BANK1. The internal control signal ML is commonly supplied to the write amplifiers and the data output buffers corresponding to the lower 8-bit data input / output terminals D0-D7, and the upper 8-bit data input / output terminals D8-D.
The internal control signal MU is commonly supplied to the write amplifier and the data output buffer corresponding to 15.

Each data input buffer of the data input / output circuit IO corresponds to the corresponding data input / output terminals D0 to D1 when the synchronous DRAM is selected in the write mode.
The 16-bit write data supplied via 5 is fetched and transmitted to the corresponding two write amplifiers. Each write amplifier has a corresponding bank selection signal BS0.
Alternatively, when BS1 is set to the high level and the corresponding internal control signal MU or ML is set to the low level, it is selectively brought into the operating state, and the write data transmitted from the corresponding data input buffer is used as a predetermined complementary write signal. Then, the corresponding complementary common data lines CD00 * to CD015
* Or bank B via CD10 * to CD115 *
Eight pieces are selectively written to the selected 16 memory cells of the memory array MARY of ANK0 or BANK1.

Each main amplifier of the data input / output circuit IO has a corresponding bank selection signal BS0 or BS0 when the synchronous DRAM is selected in the read mode.
When 1 is set to the high level, it is selectively activated. In this operating state, each main amplifier is connected to the corresponding complementary common data line CD00 * to CD015 * or CD10 * to C from the selected 16 memory cells of the memory array MARY of the bank BANK0 or BANK1.
The binary read signal output via D115 * is further amplified and transmitted to the corresponding data output buffer.

Each of the data output buffers is brought into an operating state all at once or eight by selectively turning the corresponding internal control signal MU or ML to the low level, and further reads the read data transmitted from the corresponding main amplifier. After the amplification, the data is output to the outside of the synchronous DRAM through the corresponding data input / output terminals D0 to D15. The data input / output circuit IO sends the read data to the clock signal CLK.
C to selectively delay and output by the specified cycle of
Includes AS latency control circuitry.

The synchronous DRAM of this embodiment has 16 bits for the designated bank BANK0 or BANK1.
A memory having a so-called 2 bank × 16 bit structure for simultaneously inputting or outputting bit storage data is used. The input and output operations of storage data are performed by a data mask signal DQMU.
And DQML, that is, the internal control signals MU and ML, can be selectively prohibited in 8-bit units.

The timing generation circuit TG includes a clock signal CLK supplied from the outside, a clock enable signal CKE which is a start control signal, a chip selection signal / CS, a row address strobe signal / RAS, a column address strobe signal / CAS, and a write. Based on the enable signal / WE, the data mask signals DQMU and DQML, and the bank selection signals BS0 and BS1 supplied from the bank selection circuit BS, the above various internal control signals are selectively formed and supplied to each section.

FIG. 1 shows a block diagram of an embodiment of the mode determination section included in the timing generation circuit TG. The clock signal CLK is taken in through the input buffer 1. The input buffer 1 is activated by the input buffer 2 receiving the clock enable signal CKE and the internal signal ICKE output through the inverter circuits N1 and N2 provided at the output part thereof. That is, the input buffer 1 is activated when the signal ICKE is set to the high level, takes in the clock signal CLK, and supplies the internal clock signal ICLK to the internal circuit.

In this embodiment, in order to shorten the time until the mode determination timing and simplify the circuit, although not particularly limited, the above / RAS, / CAS, / WE and / C are set.
Each control signal of S is taken in through the input buffers 3, 4, 5 and 6 and input to the decoder circuit 7 as it is.

A latch circuit 8 is provided at the output section of the decoder circuit 7 to take in the mode determination signal MDECOUT and latch it at the rising edge of the internal clock signal ICLK. The output signal of the latch circuit 8 is output as the mode determination signal MODE. As will be described later, the address signal is also used for the final mode determination. Since the address signal is held by the latch circuit provided in the address buffer as described above, the signal is used in combination with the mode determination signal MODE.

FIG. 2 shows a timing chart for explaining an example of the operation of the mode determining section. Signal C
With KE set to high level, clock signal CLK
Is made effective, and the internal clock signal ICLK changes with a delay by the amount of passing through the input buffer 1 and the inverter circuits N3 and N4.

Each signal of the input signals (/ RAS, / CAS, / WE and / CS) is input so as to have a setup time and a hold time with respect to the clock signal CLK. In this embodiment, the input signal (/ RA
S, / CAS, / WE and / CS) are input buffers 3
The input signal input during the setup time is decoded during the setup time and the hold time and is output as the decode signal MDECOUT because the configuration is such that it is supplied to the decoder circuit 7 as it is through 6 to 6.

When the internal clock signal ICLK changes from low level to high level, the latch circuit 8 latches the signal MDECOUT and outputs the mode signal MODE. As a result, the mode is determined in synchronization with the rising edge of the internal clock signal ICLK, and each internal circuit corresponding to the mode determination output can be activated at an early timing, so that the operation speed can be increased. That is, the cycle of the clock signal CLK can be shortened accordingly. If the cycle of the clock signal CLK is constant, the memory access time after the mode determination can have a time margin, and the operation margin can be improved and the power consumption can be reduced. Since the latch circuits can be integrated into one, the circuit can be simplified.

Table 1 below shows an example of a truth table of commands in the synchronous DRAM. In the table, H represents a high level, L represents a low level, X represents Don't care which may be H or L, and V represents an effective address input. The address terminals are composed of A0-A9, and are directed to a synchronous DRAM of about 4 Mbits and a x16 bit structure. A column address is designated by A0-A7.

[0042]

[Table 1]

FIG. 3 shows a timing diagram of another embodiment of the present invention. In this embodiment, the setup and hold time of the address signal is used to perform the decoding operation for address selection. That is, similarly to the above, the address signal input with the setup time and the hold time with respect to the clock signal CLK is directly supplied to the decoder circuit without passing through the latch circuit as described above.

The decoder circuit is provided with a function of comparing with the redundant address, and the comparison / judgment is also performed by utilizing the setup and hold times provided for inputting the address signal. As a result, at the timing when the internal clock signal ICLK rises to the high level, it is determined whether the normal circuit or the redundant circuit is selected,
If the redundancy comparison hits, the selection of the redundancy circuit is confirmed in place of the normal circuit, and if the redundancy comparison is a hit, the normal circuit is selected as it is.

That is, in this embodiment, the operation of selecting the redundant circuit and the operation of selecting the normal circuit are the same, and the internal clock signal I
Since it is performed in synchronization with the rising edge of CLK, the timing signal for word line selection, the activation signal of the sense amplifier, the timing signal for column selection, and the timing signals necessary for memory access such as the main amplifier control signal are common. The normal circuit and the redundant circuit can access the same. As a result, the timing adjustment inside the semiconductor memory device can be facilitated, and the circuit can be simplified and speeded up.

Although the concrete structure of the address signal and the decoder circuit as described above is not shown, basically, in the embodiment circuit of FIG. 1, the input buffers 3 to 6 are replaced by the address buffers, and the decoder is used. It is sufficient that the circuit 7 is provided with a decoding function for decoding an address for selecting a word line or a data line and a redundancy comparing function.

FIG. 4 shows a logic circuit diagram of an embodiment of the mode determining section shown in FIG. The circuit symbols of this embodiment partially overlap with those of FIG. 1 in order to prevent the circuit from becoming complicated, but it should be understood that each has a separate circuit function. This also applies to FIG. 5 below.

The clock signal CLK is taken in through the NAND gate circuit G1 controlled by the output signal of the inverter circuit N1 which receives the input initial stage control signal PWDM. The control circuit 7 is activated by the signal ICKE and is activated by the gate circuit G1 and the inverter circuit N2.
The clock signal CLK input through and is supplied as an internal clock signal ICLK to the internal circuit through the inverter circuits N3 and N4.

Shown as a typical input signal / RA
The S signal is an input first stage control signal PWD similar to the above.
It is taken in through the NAND gate circuit G2 controlled by the output signal of the inverter circuit N4 which receives M, and is supplied to the decoder circuit 7 as the internal signal RASB through the inverter circuits N6 and N7. Other input signals supplied to the decoder circuit 7 are also fetched through the same circuit as described above.

The latch circuit 8 for latching the output signal MDECOUT formed by the decoder circuit 7 is composed of the following circuits. Clocked inverter circuit CN1 for input and clocked inverter circuit CN2 for feedback
And the inverter circuit N10 are latched, and the output signal of the clocked inverter circuit CN1 is transmitted to the input of the inverter circuit N10. The signal of the common output section of CN1 and CN2 is supplied to the input clocked inverter circuit CN3 of the next-stage latch circuit. The next-stage latch circuit is a clocked inverter circuit CN4 for feedback.
And the NAND gate circuit G3 are latched, and the internal state control signal S is applied to the other input of the NAND gate circuit.
The TATE and the internal clock signal ICLK are supplied.

The internal clock signal ICLK is inverted by the inverter circuit N8, and the inverter circuit N8 outputs the inverted signal.
9 forms an in-phase signal. As a result, when the internal clock signal ICLK is at a high level, the input stage latch circuit is placed in the hold state and the next stage latch circuit is placed in the through state. That is, the high level of the internal clock signal ICLK causes the input clocked inverter circuit CN1 to be in the output high impedance state, activates the feedback clocked inverter circuit CN2, and causes the output signal of the decoder circuit 7 to return to the feedback. It is held by the clocked inverter circuit CN2 for.

In the next stage latch circuit, the clock signal ICL is used.
The high level of K activates the clocked inverter circuit CN3 for input and puts the clocked inverter circuit CN4 for feedback in the output high impedance state. The NAND gate circuit G3 uses the internal clock signal I
If the signal STATE is at the high level due to the high level of CLK, it acts as an inverter circuit.
A signal corresponding to OUT is output, and if it is at high level, the output is set to low level correspondingly.

When the internal clock signal ICLK changes to the low level, the input stage latch circuit goes into the through state, the output signal of the decoder circuit 7 is taken in, and the next stage latch circuit brought into the hold state returns to the previous state. Hold.
In this way, by using the input stage and the output stage as the latch circuit to operate as a master / slave flip-flop circuit, a stable mode determination signal MOD can be obtained.
E can be obtained.

FIG. 5 shows a logic circuit diagram of another embodiment of the mode determining section shown in FIG. In this embodiment, the internal clock signal ICLK is generated by the delay circuit, the inverter circuit N5 and the NAND gate circuit G2 to generate a pulse for a certain period of time during which the internal clock signal ICLK rises from the low level to the high level, and the input signal / RAS is fetched. The latch circuit is held in the input buffer. As a result, even if the input signal / RAS changes due to external noise or the like at the timing when the internal clock signal ICLK rises to a high level, it is not accepted and the reliability is improved.

Other input signals / CAS, / WE and / CS
For the above, the input circuit similar to the above is used to form the input signal of the decoder circuit 7. The latch circuit provided in the output section of the decoder circuit 7 and forming the mode determination signal MODE is composed of a one-stage circuit. Then, the internal clock signal supplied thereto is generated in synchronization with the rising edge of the internal clock signal as described above.
Since the shot pulse is input in the opposite phase through the three inverter circuits, it is in the through state and the hold state complementarily with the input latch circuit, and is in the through state at the timing when the one shot pulse is generated, At other timings, the hold state occurs and the mode determination signal MO
Output DE.

FIG. 7 shows a synchronous DR according to the present invention.
A schematic diagram of a main part of a computer system to which AM is applied is shown. Bus and central processing unit CPU, peripheral device control unit, dynamic RAM (D
RAM) or the synchronous DRAM (SD according to the present invention
RAM) and its memory control unit, a static RAM (SRAM) as a backup memory, a backup parity and its control unit, a read only memory (ROM) in which a program is stored, a display system, etc., and this computer system is configured. It

The peripheral device control section is connected to an external storage device, a keyboard KB and the like. Display system is video R
It is composed of an AM (hereinafter referred to as VRAM), etc., and V is connected to a display as an output device.
The stored information in the RAM is displayed. This video RAM
Is a synchronous DRAM (SDRAM) according to the present invention.
Can be replaced with A power supply unit is provided for supplying power to internal circuits of the computer system. The central processing unit CPU controls the operation timing of each memory by forming a signal for controlling each memory. When used in such a system, even if the system clock is speeded up and the memory cycle is shortened in response to the speeding up of the central processing unit CPU,
This can be dealt with by the input circuit of the synchronous DRAM as described above.

The operational effects obtained from the above embodiments are as follows. That is, (1) The output signals of the plurality of input buffers that respectively receive the input signals input from the plurality of external terminals in synchronization with the clock signal are directly supplied to the decoder circuit, and the output signals of the decoder circuits are supplied to the clock buffer. By latching with the captured internal clock signal, the setup time and hold time of the input signal with respect to the clock signal are used to capture the input signal and decode it. The effect of being able to speed up is obtained.

(2) An address signal input in synchronism with a clock signal is supplied to a decoder circuit through an address buffer, the decoder circuit makes a comparison / determination with a redundant address, and the above comparison is performed in synchronization with an internal clock signal. By selecting the normal circuit or the redundant circuit corresponding to the determination, the address signal is fetched and the redundant comparison is performed by using the setup time and the hold time of the input signal with respect to the clock signal. It is possible to obtain the effect that the operation timing of can be similarly advanced.

(3) According to the above (1), it is possible to obtain an effect that the memory access time after the mode is determined can be extended, the operation margin can be increased, and the power consumption can be reduced.

(4) By the above (2), the operation timings of the normal circuit and the redundant circuit can be made the same, so that a series of timings such as the word line selection timing and the sense amplifier activation timing can be made common. An effect that the circuit can be simplified can be obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 6, the synchronous DRAM can have any bit configuration such as so-called x1 bit or x8 bit configuration. In addition, the synchronous DRAM,
An arbitrary number of banks can be provided, and each bank can be divided into a plurality of mats. The data input / output terminals D0 to D15 may be dedicated as data input terminals and data output terminals.

In the embodiment shown in FIG. 1, the decoder circuit for making the mode decision may be similarly supplied with the address signal required for the mode decision. That is, the address signals A8 and A9 used for the mode determination are set so that the output of the address buffer is directly supplied to the decoder circuit 7 and the address decoder is supplied with a signal through a latch circuit or the like as necessary. Embodiments can be adopted. The example circuit of FIG. 4 or FIG. 5 can adopt various embodiments as needed.

The present invention has been described in the case of being applied to a so-called synchronous DRAM in which an address signal and a control input signal are supplied in synchronization with a clock signal, but the present invention is not limited to this, and for example, a static RAM. The present invention can be similarly applied to a semiconductor memory device such as a ROM or a ROM having a structure in which an address signal and a control input signal are supplied in synchronization with a clock signal.

[0065]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, the output signals of the plurality of input buffers that respectively receive the input signals input from the plurality of external terminals in synchronization with the clock signal are directly supplied to the decoder circuit, and the output signals of the decoder circuits are captured by the clock buffer. By latching with the internal clock signal, the setup time and the hold time of the input signal with respect to the clock signal are used to capture the input signal and decode the input signal, which simplifies the circuit and speeds up the decoding confirmation timing. be able to.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a mode determination unit included in a timing generation circuit of a synchronous DRAM according to the present invention.

FIG. 2 is a timing chart for explaining an example of the operation of the mode determination unit in FIG.

FIG. 3 is a timing chart for explaining a redundancy comparison operation of the semiconductor memory device according to the present invention.

FIG. 4 is a logic circuit diagram showing an embodiment of a mode determination unit in FIG.

5 is a logic circuit diagram showing another embodiment of the mode determination unit in FIG. 1. FIG.

FIG. 6 is a block diagram showing an embodiment of a synchronous DRAM to which the present invention is applied.

FIG. 7 is a schematic diagram of a main part showing an embodiment of a computer system to which a synchronous DRAM according to the present invention is applied.

FIG. 8 is a block diagram showing an example of a mode determination unit in a conventional synchronous DRAM.

9 is a timing chart for explaining an example of the operation of the mode determination unit in FIG.

[Explanation of symbols]

1 to 6 ... Input buffer, 7 ... Decoder circuit, 8 ... Latch circuit, 9 ... Control circuit, 10-13 ... Latch circuit, N1 to N21 ... Inverter circuit, CN1 to CN4 ...
Clocked inverter circuit, G1 to G5 ... NAND gate circuit, BANK0 to BANK1 ... Bank, MARY ... Memory array, RD ... Row address decoder, SA ... Sense amplifier, CD ... Column address decoder, BS ... Bank selection circuit, RB ... Row address Buffer, CB ... Column address buffer, PB ... Pre-address buffer, R
FC ... Refresh address counter, IO ... Data input / output circuit, TG ... Timing generation circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masahiro Katayama 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Hiritsu Cho-LS Engineering Co., Ltd.

Claims (3)

[Claims] 1. A plurality of input buffers for respectively capturing signals input from a plurality of external terminals, and a clock buffer for capturing a clock signal input from an external terminal,
A semiconductor memory device comprising: a decoder circuit for decoding an output signal of the input buffer; and a latch circuit for latching an output signal of the decoder circuit with an internal clock signal fetched by the clock buffer. 2. The semiconductor memory device is a synchronous DRAM whose operation is synchronized according to a clock signal input from an external terminal, and the signal is a control signal designating an operation mode. Claim 1
Semiconductor memory device. 3. An address signal input in synchronism with a clock signal supplied from an external terminal is supplied to a decoder circuit through an address buffer, and the decoder circuit makes a comparison decision with a redundant address, and an internal clock signal. A semiconductor memory device characterized in that a normal circuit or a redundant circuit corresponding to the comparison judgment is selected in synchronism with the above.