JPH07307090A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To obtain a synchronous semiconductor memory having a new pipe line system which can cope with quick cycle by using access paths of plural systems together. CONSTITUTION:This memory is a synchronous DRAM controlling the inside synchronizing with a system clock signal, and has two systems of access paths which can independently operate each other for one memory array M-ARY. Corresponding to these systems, a column system processing circuit consisting of two groups (S), (F) of column address decoders C-ADCR, column address latch circuits C-ALATs, data write amplifiers DWAMPs, data read amplifiers DRAMPs, and data latch circuits DLATs is provided. Also, this memory is constituted with a column address buffer C-ADB, data multiplexer DMPX, data input buffer DIB, data output buffer DOB, control circuit/timing generating circuit CONT/TG, and a row system processing circuit corresponding to the row address decoder R-ADCR.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a new pipe capable of coping with high-speed cycles in a synchronous semiconductor memory device such as a synchronous DRAM which internally controls in synchronization with a system clock signal. The present invention relates to a technique effectively applied to a semiconductor memory device that can be controlled by a line method.

[0002]

2. Description of the Related Art In recent years, some high-speed DRAMs have been proposed in order to increase the speed of the main memory device (DRAM) in response to the increase in the speed of microprocessors. For example, synchronous DRAM is one of them, and it is about to be developed by most DRAM makers. The features are that internal control is performed in synchronization with the system clock signal and high-speed data throughput is possible by the burst mode (column access).

As a circuit architecture for realizing this burst mode, there are a pipeline system, a prefetch system, and a hybrid system thereof. The pipeline system is the most compatible with random access and the degree of freedom of burst length. It is considered a flexible method.

In this synchronous DRAM, for example, as shown in FIG. 8, a memory array M-ARY, a column address decoder C-ADCR, a sense amplifier SA,
Row address decoder R-ADCR, column address buffer C-ADB, row address buffer R-ADB,
Data input buffer DIB, data output buffer DOB
And a control circuit / timing generation circuit CONT / TG etc., one set of column-related and row-related processing circuits is provided for one memory array M-ARY.

The basic operation of this synchronous DRAM is the same memory system as the DRAM, and precharge and refresh are required to perform read and write operations. The DRAM performs these operations by controlling the clock timing, while the synchronous DRAM
Is characterized in that it is controlled using command signals.
This command signal is defined by combining control signals such as bar RAS, bar CAS, and bar WE according to DRAM, but the clock signal itself has no meaning.

Next, four command signals ((1) bank active signal, (2) read signal, (3) write signal, (4)
The basic operation of the synchronous DRAM will be described below with reference to the timing chart of FIG. 9 using the bank precharge signal.

In the example of FIG. 9, the command signal is taken in in the T1 cycle, the command signal is decoded and the subsequent operation is started, and necessary control, in this example, the bank active operation is performed. .

(1) Bank Active Operation In the T1 cycle, the row address signal and the bank address signal are simultaneously taken in. These address signals select the activated bank and the word line corresponding to the row address signal. The information of all the memory cells connected to the selected word line is amplified and latched by the sense amplifier similarly to the DRAM. Only in this state, read / write operations can be performed on the memory array. In the synchronous DRAM, the read / write operation is performed on this sense amplifier and latch.

(2), (3) Read / Write Operation In the T2 cycle, a necessary operation is performed in response to a read or write command signal. At the same time, the column address signal is taken in. In this read / write operation, there are two concepts of burst length and latency. The burst length indicates the number of times the subsequent operation is repeated by the read / write command signal, and the latency indicates at what cycle the correct data comes out from the command signal at the time of reading. In this example, the burst length is set to "2" and the latency is set to "1".

At the time of writing, the I / O is in the input state, and the input data signal is fetched at the same timing as the write command signal. At the time of reading, the I / O is in the output state, and when the latency is set to "1", correct data comes out from the next T3 cycle. Since the burst length is "2", T is used to output the second data.
NOP cycle is included in 3 cycles. In this NOP cycle, the command signal has no particular meaning and is used only for continuing operations such as read / write.

(4) Bank precharge operation Next, when it is desired to access data from a bank different from the previous bank or data of another word line, the same as in the DRAM before inputting a new bank active command signal in the T5 cycle. At the T4 cycle, the bank precharge command signal is required.

As described above, the synchronous DRAM
The basic operation of is performed using four command signals: (1) bank active signal, (2) read signal, (3) write signal, and (4) bank precharge signal.

As a technique relating to such a semiconductor memory device as a synchronous DRAM, for example, the Institute of Electronics and Communication Engineers, issued November 30, 1984,
It is described in documents such as "LSI Handbook" P485 to P533.

[0014]

However, the technique based on the pipeline system of the synchronous DRAM as described above is considered to be the most flexible system in terms of compatibility with random access and burst degree flexibility. However, the present inventor has found that the current circuit system has a problem in improving high speed.

That is, the currently used pipeline system realizes a high-speed throughput by dividing the access path (column system) into two or three stages, that is, by shortening the pitch, thereby achieving a higher speed. In order to support the system cycle, it is necessary to increase the stage division.

However, in such a pipeline system, since the operation of amplifying the data signal cannot be further divided, there arises a problem that it cannot cope with a cycle shorter than the time required for it.

Therefore, an object of the present invention is to improve such a current pipeline system so that even under a high-speed system clock signal, internal access path control uses a divided internal signal and a plurality of systems are used. Another object of the present invention is to provide a semiconductor memory device such as a synchronous DRAM by a new pipeline system which can cope with a higher speed cycle without shortening the pitch by using it together with the access path.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0019]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the semiconductor memory device of the present invention is applied to a synchronous type semiconductor memory device which internally controls in synchronization with a system clock signal, and a plurality of address decoders are provided for one memory array. Corresponding to these address decoders, a plurality of access paths that can operate independently of each other are provided.

As the internal signal for controlling the access path, a frequency-divided signal (double frequency division) from the system clock is used.

In particular, a pipeline system is used as the circuit architecture, and when it is applied to a synchronous DRAM having two column address decoders, it has two access paths.

Further, the semiconductor memory device is used in a data processing system having a microprocessor, a main memory device and the like built therein, and the main memory device is constituted by the semiconductor memory device.

[0024]

According to the above-described semiconductor memory device, by having access paths of a plurality of systems, when an arbitrary access request occurs, one of the plurality of systems takes charge of the access path and the next access request. As a result, any other system can take charge of the request, and any available system can respond to the access request.

As a result, in response to consecutively generated access requests, any one of the access paths of a plurality of systems can always respond to the access, whereby the throughput can be improved.

In particular, when the pipeline method is used, the operation cycle of the access path is divided into a plurality of stages for processing, and each division is performed even if the pipeline pitch is not shortened to cope with the speedup of the system. Since the operated stages can be operated in parallel, it is possible to cope with a faster system cycle.

For example, in the case of a synchronous DRAM having two access paths, when any access request is issued, one of them is in charge of the access request.
The other is responsible for the next access request, and can alternately respond to the access request.

In this case, which path responds to the first access request is determined by the internal state of the semiconductor memory device at that time, that is, the state of the clock signal, and is completely distinguished from the outside. It is not possible. However, there is no significant difference in electrical characteristics.

Further, when the main memory device of the data processing system is constituted by a semiconductor memory device such as a synchronous DRAM, high-speed data processing via the main memory device can be favorably coped with as the microprocessor speeds up. can do.

[0030]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a functional block diagram showing the main structure of a semiconductor memory device according to an embodiment of the present invention, and FIGS. 2A and 2B show the mat structure of the memory array of this embodiment and the conventional example. FIG. 3 is a circuit connection diagram of a mat structure in the present embodiment, FIG. 4 is a functional block diagram showing a main structure of a data processing system to which the semiconductor memory device of the present embodiment is applied, and FIG.
7A and 7B are explanatory diagrams and timing charts of the access paths during the read operation, the write operation, and the read / write mixed operation in this embodiment.

First, the main structure of the semiconductor memory device of this embodiment will be described with reference to FIG.

The semiconductor memory device of this embodiment is, for example, a synchronous DRAM having two access paths of a plurality of access paths and performing internal control in synchronization with a system clock signal. Array M
-ARY and two sets of column address decoder C-ADC
R (S), (F), column address latch circuit C-ALA
T (S), (F), data write amplifier DWAMP (S),
(F), data read amplifiers DRAMP (S), (F) and data latch circuits DLAT (S), (F) and one column address buffer C-ADB, data multiplexer DMPX, data input buffer DIB, data output buffer DOB and control circuit / timing generation circuit C
Row address decoder R in addition to ONT / TG
It is composed of a buffer (not shown) corresponding to ADCR.

That is, the synchronous DRA of this embodiment
M has two access paths that can operate independently of each other for one memory array M-ARY, and the column address decoder C corresponds to these two access paths.
-ADCR (S), (F), data write amplifier DWAM
P (S), (F), data read amplifier DRAMP (S),
Two sets of column-type address processing circuits and data processing circuits such as (F) are provided.

This synchronous DRAM has an external clock signal CL having a repeating period of a predetermined pulse width.
In addition to K, control signal bar RAS, bar CAS, bar WE
Are input to the control circuit / timing generation circuit CONT / TG, and these control signals are combined to define four command signals of a bank active signal, a read signal, a write signal, and a bank precharge signal.

Further, the control circuit / timing generation circuit CO
2 according to the clock signal CLK input to NT / TG
Access path control signal φ for controlling access path of system
SP and φFP are generated, and this access path control signal φ
SP and φFP are pulse signals which are generated by doubling the frequency in synchronization with the clock signal CLK and are alternately generated, and are input to the column address latch circuits C-ALAT (S), (F) and the data latch circuit DLAT. It is used as a switching signal for two access paths.

For example, during the data read operation, the column address latch circuit CA corresponding to the access path is used.
LAT (S), (F) are access path control signals φSP, φ
Alternately switched by the FP, and during the data write operation, the column address latch circuit C-ALAT (S),
(F) and the data latch circuit DLAT are alternately switched.

Further, an output control signal φ for controlling the data multiplexer DMPX by this clock signal CLK.
DO is generated and is a pulse signal generated by being delayed in synchronization with the clock signal CLK, and the data multiplexer DMPX can be switched according to the two access paths during the read operation.

Also, the mat structure in the memory array M-ARY is as shown in FIG. 2 (a), for example, as shown in FIG. 2 (a), the circuits around the memory array M-ARY (S) and (F) are reduced as much as possible. In order to reduce the increase in chip size as compared with the DRAM shown in (1), a shared method that can be executed simultaneously or in parallel as the sense amplifier SA is adopted,
The two memory arrays M-ARY (S) and (F) are commonly used.

In this case, the circuit connection diagram of the mat structure can be shown as shown in FIG.
Column address decoder C-ADCR of each system
(S), (F), column address switch C-ASW
From (S), (F) to memory array M-ARY (S), (F)
Shared sense amplifier S via internal bit line
This is done by accessing A.

Synchronous DR constructed as described above
The AM is, for example, as shown in FIG. 4, a microprocessor MPU, a cache memory device, a main memory controller connected to these via a system bus, a bus controller, a graphic controller, a main memory device connected to the main memory controller, and a graphic. It is used in a data processing system composed of a display connected to the controller, and is connected to an external bus through a bus controller.

In this data processing system, the main memory is a synchronous DR having the high speed mode of this embodiment.
A data rewriting operation at the time of a miss in the cache storage device, which is composed of AM and is performed from the main storage device to the cache storage device via the main storage controller, and to the display via the graphic controller. It is well used for operations that require high-speed data processing, such as data graphics output operations.

Further, in this data processing system, a pipeline system is used as a circuit architecture for realizing the burst mode, aiming at speeding up of the main memory device in response to speeding up of the microprocessor MPU. Since it is divided into three stages and each of the divided stages can be operated in parallel, the configuration is flexible in terms of compatibility with random access and freedom of burst length.

Next, with respect to the operation of this embodiment, the operation of the synchronous DRAM will be described with reference to FIGS.

The basic operation is, as described above, using the four command signals of the bank active signal, the read signal, the write signal and the bank precharge signal, the bank active operation, the read operation and the write operation. , Bank precharge operation is performed.

Here, the read operation, the write operation, and the read / write mixed operation, which are the features of the present embodiment, will be sequentially described based on the access paths and timing charts of FIGS. 5 to 7. .

(1). Read operation (FIGS. 5 (a) and 5 (b)) The operation starts from the T1 cycle of the clock signal CLK, and at the beginning of this T1 cycle, the access path control signal φ
SP occurs, and one access path (S) side is activated. Then, the address signal Add “1” in the column address buffer C-ADB is set to the access path control signal φS.
Column address latch circuit C-ALAT (S) by P
Take in. This address signal is latched as a valid internal address signal until the next access path control signal φSP is output (until the beginning of the T3 cycle).

During this time, data is read from the memory cell selected by the word line and bit line of the memory array M-ARY corresponding to the address signal, and the column address decoder C-ADCR (S) and data read amplifier D are read.
A series of operations up to amplification is performed via RAMP (S).
Therefore, the amplified data signal is supplied to the data multiplexer D by the output control signal φDO at the beginning of the T3 cycle.
MPX is switched and delayed as two cycles, for example, and taken out as an output data signal from the data output buffer DOB.

Then, when the T2 cycle is started, the access path control signal φFP is generated this time, and the other access path (F) side is activated. Similarly, the address signal Add "2" at this time is sent to the column address latch circuit C-
It is latched as an internal address signal until it is taken into ALAT (F) and the next access path control signal φFP is output (until the beginning of the T4 cycle). Read here,
The amplified data signal is taken out as an output data signal in the same manner as above by the output control signal φDO signal at the beginning of the T4 cycle.

During the time from the T2 cycle to the T3 cycle, as shown in the internal address signal internal Add (S) and internal Add (F), the read operations of the access path (S) and the access path (F) are performed. Although overlapping, both access paths are independent of each other, so that both operations can be compatible.

Further, since a series of operations from the fetching of the address signal to the reading and amplification thereof uses two cycles, the cycle time can be easily shortened even with a device having a relatively slow access time.

Further, in the T3 cycle to the T11 cycle, the address signals Add "3" to Add "1 are added.
The same operation as the T1 cycle and the T2 cycle is repeatedly performed for 1 ″, whereby the read operation is executed by alternately switching between the two access paths (S) and (F).

(2). Write operation (FIGS. 6 (a) and 6 (b)) At the beginning of the T1 cycle of the clock signal CLK, the access path control signal φSP causes the address signal Add "1",
Input data signal "1" is taken in. This address signal is sent to the column address buffer C-AD as in the read.
The column address latch circuit C-ALAT (S) is fetched from B, while the input data signal is fetched from the data input buffer DIB to the data latch circuit DLAT (S). These are effectively held until the next data signal is fetched in the T3 cycle.

In the period of 2 cycles during this period, the data latch circuit DLAT (S) drives the data write amplifier DWAM.
P (S), column address decoder C-ADCR (S)
Through the memory array MA corresponding to the address signal
A data write operation is performed on the memory cell selected by the RY word line and bit line.

Then, in the T2 cycle, similarly, the access path control signal φFP is issued and the address signal Add is added.
A series of data write operation is performed from the acquisition of "2" and the input data signal "2". Further, in the T3 cycle to the T11 cycle, the address signal Add
T1 cycle and T for “3” to Add “11”
The same operation as two cycles is repeated.

As described above, even in the write operation, the two access paths can be operated alternately and independently, so that the internal address signal internal Add (S), internal Add (F), and internal data signal ( As shown in S) and (F), the write operations of the access path (S) and the access path (F) can be overlapped to achieve both operations.

(3). Mixed operation during read / write (Fig. 7
(a), (b)) When performing continuous operations from read to write and from write to read, the operation is the same as the above read and write operations, but from read operation to write operation In continuous operation, latency required for read operation (3 cycles) and I / O switching (input to output)
Since it takes 1 cycle for each, it is necessary to place a dummy cycle between the T3 cycle and the T6 cycle.

Further, when the operation is continuously performed from the write operation to the read operation, it is not necessary to place the dummy cycle as described above, and the continuous operation is possible.

In FIG. 7A, one access path (S) side writes data into the memory cell of the selected memory array M-ARY corresponding to the address signal by the write operation and the other access Pass (F)
The side reads data from the memory cell of the selected memory array M-ARY corresponding to the address signal by the read operation.

As described above, in the read operation and the write operation, the two access paths can be operated alternately and independently, so that high throughput can be realized even for continuous access requests. it can.

Next, the basic operation of the sense amplifier SA in the shared system in the map configuration of the memory array M-ARY will be described with reference to FIG.

For example, the memory array M-ARY (S)
When the word line of the mat on the side is selected, the signal line SH (F) becomes the Low level, and the bit line on the side of the memory array M-ARY (F) from the sense amplifier SA, as in the normal shared system. Detach. At the same time, the signal line SH
(S) becomes High level, and the memory array M-AR
The signal from Y (S) is transmitted to the sense amplifier SA, and the amplification operation of the sense amplifier SA is performed in this state.

After that, if the conventional shared system is still used, the memory array M-ARY (F) side remains separated from the sense amplifier SA, and the memory array M-AR.
Y (F) side column address decoder C-ADCR
Although access from (F) becomes impossible, in the present embodiment, the signal line SH is immediately output after the amplification is completed.
(F) is set to High level, and the memory array M-AR
The bit line on the Y (F) side is also connected to the sense amplifier SA.

By doing so, after that, access from either side of the memory array M-ARY (S) or the memory array M-ARY (F) becomes possible, and two access paths are alternately and independently provided. Can be operated. Here, the timing of setting the signal line SH (F) to the High level is possible as long as the data is not destroyed even during the amplification.

Therefore, the synchronous DRAM of this embodiment is
According to the semiconductor memory device of the present invention, one memory array M
-For ARY, two sets of column address decoders C-
ADCR (S), (F), data write amplifier DWAMP
(S), (F), data read amplifier DRAMP (S),
By providing the column processing circuit such as (F), when an arbitrary access request occurs, the access path by one column processing circuit takes charge of this.
For the next access request, the access path by the other column processing circuit can handle this,
Since it is possible to alternately respond to consecutive access requests, it is possible to improve throughput.

In particular, by constructing this synchronous DRAM in the main storage device of the data processing system and using the pipeline system in response to the speeding up of the microprocessor MPU, there are three access paths, and more than three access paths. Since it can be divided into multiple stages and each stage can be operated in parallel, in addition to compatibility with random access and flexibility of burst length, it is possible to support even faster system cycles. .

Further, a shared system is adopted as the sense amplifier SA, and two memory arrays M-ARY (S),
Since it is shared by (F), the number of circuits around the memory array M-ARY can be reduced as much as possible, and the increase in chip size can be made as small as possible compared with the conventional synchronous DRAM.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the semiconductor memory device of this embodiment, the synchronous DR having two access paths is used.
Although the case of application to the AM has been described, the present invention is not limited to the above-described embodiment, and a DRAM having three or more access paths or another system clock synchronous semiconductor memory device such as SRAM, Further, it can be widely applied to a data processing system having the synchronous semiconductor memory device built therein.

[0070]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

(1). By having a plurality of column address decoders for one memory array and having a plurality of access paths that can operate independently of each other in correspondence with these plurality of column address decoders, When one access request is generated, one of the plurality of systems takes charge of this request, and one of the sequentially available systems can respond to the access request. Also, the throughput can be improved.

(2) In the above (1), in particular, by using an internal signal generated by dividing the operation cycle of the access path into a plurality of stages for processing and dividing the system signal, When a pipeline system in which each of the stages is operated in parallel is used as the circuit architecture, it is possible to cope with a higher system cycle without shortening the pipeline pitch.

(3) In the above (1), for example, a synchronous DRAM is used, and two access paths capable of operating independently of each other corresponding to two column address decoders are provided.
In the case of (1) above, in the case of system possession, when any access request occurs, one of them can always take charge of this, and the other can always take charge of the next access request. There is no restriction on the order as described above, and it becomes possible for the access paths of the two systems to alternately respond to access.

(4) In the above (1), for example, the main memory is used in a data processing system including a microprocessor and a main memory, and the main memory is used for the synchronous D.
When the semiconductor memory device such as RAM is used, high-speed data processing can be favorably performed as the microprocessor speeds up.

(5) According to the above (1) to (4), the present invention is applied to a device having a relatively long access time by using a plurality of access paths and a pipeline system together, and a high data throughput can be achieved. It is possible to obtain a realizable synchronous semiconductor memory device and a data processing system incorporating the same.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing a main configuration of a semiconductor memory device according to an embodiment of the present invention.

2A and 2B are explanatory views showing a mat structure of a memory array of this embodiment and a conventional example.

FIG. 3 is a circuit connection diagram of a mat structure in this embodiment.

FIG. 4 is a functional block diagram showing a main configuration of a data processing system to which the semiconductor memory device of this embodiment is applied.

5A and 5B are an explanatory diagram and a timing chart of an access path during a read operation in this embodiment.

6A and 6B are an explanatory diagram and a timing chart of an access path during a write operation in this embodiment.

7A and 7B are an explanatory diagram and a timing chart of an access path during a read / write mixed operation in the present embodiment.

FIG. 8 is a functional block diagram showing a main configuration of a semiconductor memory device which is an example of a conventional technique.

FIG. 9 is a timing chart showing a basic operation in a semiconductor memory device which is an example of a conventional technique.

[Explanation of symbols]

 M-ARY memory array, C-ADCR column address decoder C-ALAT column address latch circuit DWAMP data write amplifier DRAMP data read amplifier DLAT data latch circuit C-ADB column address buffer DMPX data multiplexer DIB data input buffer DOB data output buffer CONT / TG control circuit / timing generation circuit R-ADCR row address decoder C-ASW column address switch SA sense amplifier MPU microprocessor R-ADB row address buffer

Claims (4)

[Claims] 1. A synchronous semiconductor memory device for performing internal control in synchronization with a system clock signal, comprising a plurality of address decoders for one memory array, corresponding to the plurality of address decoders. A semiconductor memory device having a plurality of access paths capable of operating independently of each other by using an internal signal divided from the system clock signal. 2. A pipeline architecture is used as a circuit architecture, in which an operation cycle of the access path is divided into a plurality of stages for processing, and each of the plurality of stages is operated in parallel. The semiconductor memory device described. 3. The semiconductor memory device is a synchronous DR
AM and has two column address decoders as the plurality of address decoders, and outputs the system clock signal to 2 in correspondence with the two column address decoders.
It has two internal signals that are doubled and two access paths that can operate independently of each other. When any access request occurs, one of them takes charge of this and the next 3. The semiconductor memory device according to claim 1, wherein the other side always handles the access request, and the two access paths always respond alternately to the access. 4. The semiconductor memory device is used in a data processing system including at least a microprocessor and a main memory device, and the main memory device is configured by the semiconductor memory device. 3. The semiconductor memory device according to item 3.