JP3276487B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, a synchronous DRAM (Dynamic Random A) employing an address multiplex system.
(Access Memory: dynamic random access memory) and a technique particularly effective for use in shortening the cycle time.

[0002]

2. Description of the Related Art There is a so-called synchronous DRAM whose operation is synchronized according to a predetermined clock signal. The synchronous DRAM employs a so-called address multiplex system in which an X address signal used for selecting a row of a memory array and a Y address signal used for selecting a column are time-divisionally input via a common external terminal. .

A synchronous DRAM adopting an address multiplex system is disclosed in, for example, "HM521680" issued by Hitachi, Ltd. on January 18, 1993.
0, HM54416800 series data book ".

[0004]

As shown in FIG. 4, a conventional synchronous DRAM employing an address multiplex system has an input terminal having a common external terminal for inputting an address, that is, address input terminals A0 to Ai. And a row address buffer RB and a column address buffer CB which are commonly coupled to each other. Address input terminals A0 to Ai
The X address signal input in a time-sharing manner through
As shown in the example, the internal control signal RL rises to the high level and is taken into the row address buffer RB, and the Y address signal is taken up by the internal control signal CL and taken into the column address buffer CB. Internal control signal RL is applied to row address strobe signal RAS at the rising edge of clock signal CLK.
B (here, a so-called inverted signal or the like which is selectively set to a low level when it is made valid is indicated by adding a B to the end of its name; the same applies to the following). And the internal control signal CL is selectively set to the high level on condition that the column address strobe signal CASB is set to the low level at the rising edge of the clock signal CLK.

However, the present inventors faced the following problems in an attempt to further increase the speed of the synchronous DRAM. That is, the synchronous DRAM is
As described above, the operation is synchronized according to the clock signal CLK, and its main input / output specification is the clock signal CL.
It is defined based on the rising edge of K. However, the clock signal CLK and the address input terminals A0 to Ai
Paying attention to the time relationship between the X address signal and the Y address signal input through the clock signal CLK.
From the high level to the internal control signals RL and CL being high level, the delay time t corresponding to the transmission delay time of the corresponding logic gate of the timing generation circuit, etc.
In addition to the requirement of dr or tdc, the row address buffer RB and the column address buffer CB are optimally arranged under the respective conditions, so that a relatively large skew occurs due to the arrangement position and inter-bit variation. As a result, a relatively large setup time t _AS and hold time t _AH are required between the clock signal CLK and the X address signal, that is, the row address RAD or the Y address signal, that is, the column address CAD. Is limited in speed.

An object of the present invention is to reduce the address setup time and address hold time of a synchronous DRAM or the like employing an address multiplex method, and to promote the cycle time thereof.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0008]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, an address multiplex system is adopted in which an X address signal provided for row selection and a Y address signal provided for column selection are input in a time-sharing manner through a common address input terminal, and the operation thereof is performed in a predetermined manner. In a synchronous DRAM or the like which is synchronized according to a clock signal, the synchronous DRAM is arranged via an address input terminal in accordance with a first internal control signal which is arranged close to an address input terminal and is selectively set to a valid level in response to a rise of the clock signal. A pre-address buffer that captures and holds an input X-address signal or Y-address signal is provided.
In response to the row address strobe signal or the column address strobe signal being already at the valid level at the point in time when the clock signal changes to the valid level, the second or third internal control signal which is selectively brought to the valid level, respectively, is received. A row address buffer and a column address buffer which capture and hold the X address signal or the Y address signal held in the pre-address buffer are provided.

[0009]

According to the above-mentioned means, the X address signal and the Y address signal input in a time-division manner via the address input terminal are first taken into the optimally arranged pre-address buffer, and then optimally placed under the respective conditions. Since the signals can be transmitted to the arranged row address buffer and column address buffer, the setup time and hold time of the X address signal and the Y address signal with respect to the clock signal can be reduced, and the cycle time of a synchronous DRAM or the like can be shortened. it can.

[0010]

FIG. 1 is a block diagram showing one embodiment of a synchronous DRAM to which the present invention is applied. FIG. 2 shows a signal waveform diagram of one embodiment of the synchronous DRAM of FIG. The configuration and operation of the synchronous DRAM of this embodiment and the features thereof will be described with reference to these drawings. Although the circuit elements constituting each block in FIG. 1 are not particularly limited, a known M
OSFET (Metal Oxide Semiconductor Field Effect Transistor; In this specification, a MOSFET is generally referred to as an insulated gate field effect transistor), a single semiconductor substrate surface such as single crystal silicon is manufactured by an integrated circuit manufacturing technique. Formed on top.

Referring to FIG. 1, the synchronous DRAM of this embodiment includes two banks BANK0 and BANK1, each of which has a memory array occupying most of the layout area and a direct peripheral area thereof. Row address decoder RD, sense amplifier S
A and a column address decoder CD.

Here, banks BANK0 and BANK1
Includes a plurality of word lines arranged in parallel in the vertical direction in the drawing and a plurality of complementary bit lines arranged in parallel in the horizontal direction.
At the intersections of these word lines and complementary bit lines, a large number of dynamic memory cells composed of information storage capacitors and address selection MOSFETs are arranged in a grid.

The word lines constituting the memory arrays MARY of the banks BANK0 and BANK1 are respectively coupled to the corresponding row address decoders RD, and are alternatively selected. The row address decoder RD is supplied with i-bit internal address signals X0 to Xi-1 excluding the most significant bit from the row address buffer RB, and receives internal control signals RG0 and RG1 (not shown) from the timing generation circuit TG. Supplied. The row address buffer RB includes a pre-address buffer P
B supplies the internal address signals P0 to Pi, and the refresh address counter RFC supplies the refresh address signals R0 to Ri. The row address buffer RB is further supplied with an internal control signal RL (second internal control signal) and RF from the timing generation circuit TG. An internal control signal RC is supplied to the refresh address counter RFC from the timing generation circuit TG.
The internal control signals RG0 and RG1 are selectively formed according to the bank selection signals BS0 and BS1 supplied from the bank selection circuit BS to the timing generation circuit TG.
These bank select signals BS0 and BS1 are selectively formed in accordance with the most significant bit internal address signal Xi supplied from the row address buffer RB to the bank select circuit BS. The row address buffer RB is provided with a row address decoder R of the banks BANK0 and BANK1.
It is optimally arranged so that the distance between D and the refresh address counter RFC becomes as short as possible.

In this embodiment, the synchronous DRA
M is an X address signal A whose operation is synchronized according to a clock signal CLK and is used for row selection of a memory array.
X0 to AXi and a Y address signal AY0 used for column selection
To AYi are common external terminals, that is, address input terminals A
An address multiplexing method is used in which the data is input in a time-sharing manner through 0 to Ai. As shown in FIG. 2, X address signals AX0 to AXi designating the row address RAD are input to the address input terminals A0 to Ai in synchronization with the first rising edge of the clock signal CLK. Address signals AY0 to AY0 for designating the column address CAD in synchronization with the rising edge of
Yi is input. The X address signals AX0 to AXi and the Y address signals AY0 to AY0 are input to the pre-address buffer PB via address input terminals A0 to Ai.
Yi is supplied, and an inverted internal control signal PLB (first internal control signal) is supplied from the timing generation circuit TG.
The pre-address buffer PB is arranged close to the address input terminals A0 to Ai, and is optimally arranged so that the distance between the pre-address buffers PB and the address input terminals is as short as possible.

Here, the inverted internal control signal PLB is shown in FIG.
In response to the change of the clock signal CLK to the effective level, ie, high level, the clock signal CLK is selectively set to the effective level, ie, low level. Further, the internal control signal RL is
At the point in time when the clock signal CLK changes to the high level, the row address strobe signal RASB has already been set to the valid level, ie, the low level, and is selectively set to the valid level, ie, the high level. The time from the rise of the internal control signal RL to the rise of the internal control signal RL is set with a relatively large margin. Further, the internal control signal RF is selectively set to a high level when the synchronous DRAM is set to the refresh mode, and the internal control signal RC is set to a high level at a predetermined timing when the synchronous DRAM is set to the refresh mode. You.

When the synchronous DRAM is set in a normal operation mode, the pre-address buffer PB stores an X address signal AX0-AXi or a Y address signal AY0-AYi input through address input terminals A0-Ai.
In response to the falling change of the inverted internal control signal PLB to the low level, captures and holds the same, and transmits it to the row address buffer RB and the column address buffer CB as internal address signals P0 to Pi. In addition, the refresh address counter RFC has a synchronous DRA
When M is in the refresh mode, the internal control signal R
A step operation is performed according to C to form refresh address signals R0 to Ri.

On the other hand, when the synchronous DRAM is set to the normal operation mode and the internal control signal RF is set to the low level, the row address buffer RB stores the internal address signals P0 to Pi supplied from the pre-address buffer PB, that is, the X address. Signals AX0-AXi are converted to internal control signal RL
Capture and retain according to In addition, synchronous DR
When the AM is in the refresh mode and the internal control signal RF is set to the high level, the refresh address counter R
Refresh address signals R0 to R supplied from FC
i is captured and held in accordance with the internal control signal RL. Then, based on these X address signals or refresh address signals, internal address signals X0 to Xi are formed. Among them, the internal address signal Xi of the most significant bit is supplied to the bank selection circuit BS, and the other internal address signals X0 to Xi-1 are commonly supplied to the row address decoders RD of the banks BANK0 and BANK1.

Bank select circuit BS decodes internal address signal Xi of the most significant bit supplied from row address buffer RB, and corresponding bank select signal BS0.
And BS1 are selectively formed, and a timing generation circuit TG
And a data input / output circuit IO. Also, the row address decoder RD of the banks BANK0 and BANK1
Are selectively activated when the internal control signal RG0 or RG1 is set to a high level, and the internal address signal X
0 to Xi-1 to decode the corresponding memory array M
The ARY word line is alternatively set to a high level selected state.

Next, the complementary bit lines forming the memory array MARY of the banks BANK0 and BANK1 are coupled to the corresponding sense amplifier SA. To these sense amplifiers SA, a bit line selection signal of a predetermined bit is supplied from a corresponding column address decoder CD, and an internal control signal PA0 or PA1 (not shown) is supplied from a timing generation circuit TG. Note that the internal control signal P
L0 and PL1 are selectively formed according to bank selection signals BS0 and BS1.

The sense amplifiers SA of the banks BANK0 and BANK1 each include a plurality of unit circuits provided corresponding to the respective complementary bit lines of the corresponding memory array MARY. Each of these unit circuits is a pair of CMOs.
It includes a unit amplifier circuit formed by cross-connecting S inverters and a pair of switch MOSFETs. Among these, the power supply voltage and the ground potential of the circuit are selectively supplied to the unit amplifier circuit of each unit circuit via a pair of drive MOSFETs selectively turned on according to the corresponding internal control signal PA0 or PA1. Is done. The switch MO of each unit circuit
The gates of the SFETs are commonly connected every 16 pairs, and the corresponding bit line selection signal is supplied in common from the corresponding column address decoder CD.

As a result, the unit amplifier circuit constituting each unit circuit of the sense amplifier SA receives the corresponding internal control signal P
When A0 or PA1 is set to the high level, the operating state is selectively and simultaneously performed, and the corresponding memory array MAR is set.
The small read signal output from the plurality of memory cells coupled to the selected Y word line via the corresponding complementary bit line is amplified to be a high level or low level binary read signal. The switch MOSFET pairs forming each unit circuit of the sense amplifier SA are selectively turned on by 16 pairs by setting the corresponding bit line selection signal to a high level, and the corresponding memory array MAR
Y corresponding 16 sets of complementary bit lines and complementary common data lines CD00 * to CD015 * or CD10 * to CD1
15 * (here, for example, the non-inverted common data line CD00T
And the inverted common data line CD00B are indicated by asterisks like a complementary bit line CD00 *. Non-inverted signals and the like that are selectively set to a high level when they are valid are indicated by adding a T to the end of their names. The same applies to the following).

The column address decoder CD of the banks BANK0 and BANK1 has a column address buffer C
The internal address signals Y0 to Yi of i + 1 bits from B are commonly supplied, and the corresponding internal control signals CG0 and CG1 (not shown) are supplied from the timing generation circuit TG. The column address buffer CB is supplied with i + 1-bit internal address signals P0 to Pi from the pre-address buffer PB, and the timing generation circuit TG
Supplies an internal control signal CL (third internal control signal). The internal control signals CG0 and CG1 are selectively formed in accordance with the most significant bit address signal input again in synchronization with the column address strobe signal CASB, that is, the bank selection signals BS0 and BS1. Also,
The column address buffers CB are optimally arranged so that the distance between the column address buffers CD of the banks BANK0 and BANK1 is as short as possible.

In this embodiment, the internal control signal CL
As shown in FIG. 2, when the column address strobe signal CASB is already at the valid level, ie, the low level, at the time when the clock signal CLK changes to the high level, the valid level, ie, the high level is selectively set. However, the time from the rise of the clock signal CLK to the high level to the rise of the internal control signal CL is set with a relatively long margin. In addition, synchronous DRA
M has a burst mode for continuously outputting read data of a plurality of memory cells coupled to a selected word line, and a column address buffer CB sequentially stores column addresses corresponding to a series of memory cells in this burst mode. Includes a burst counter to specify.

The column address buffer CB has an internal address signal P0 supplied from the pre-address buffer PB.
To Pi, that is, the Y address signals AY0 to AYi are fetched and held in accordance with the internal control signal CL, and the internal address signals Y0 to YY are determined based on these Y address signals.
i is formed and supplied to the column address decoder CD of each bank. When the synchronous DRAM is set to the burst mode, the received Y address signals AY0 to AY0 to AY0
A step operation is performed with Yi as a start address, and a column address of a series of memory cells to be continuously accessed is designated.

The column address decoders CD of the banks BANK0 and BANK1 are selectively activated when the corresponding internal control signal CG0 or CG1 is set to a high level. In this operation state, each column address decoder CD decodes the internal address signals Y0 to Yi supplied from the column address buffer CB, and selectively sets the corresponding bit line selection signal to a high level.

Complementary common data lines CD00 * to CD015 * and CD10 * to C to which designated 16 sets of complementary bit lines of memory array MARY constituting banks BANK0 and BANK1 are selectively connected, respectively.
D115 * is coupled to data input / output circuit IO. The data input / output circuit IO is supplied with bank selection signals BS0 and BS1 from the bank selection circuit BS, and with the internal control signals MU and ML from the timing generation circuit TG. Note that the internal control signal MU is selectively set to the high level by setting the data mask signal DQMU to the high level at the rising edge of the clock signal CLK.
The internal control signal ML is selectively set to the high level by setting the data mask signal DQML to the high level. The bank selection signals BS0 and BS1 are selectively formed according to the most significant bit address signal input in synchronization with the column address strobe signal CASB.

Data input / output circuit IO includes complementary common data lines CD00 * -CD015 * and CD10 * -CD
It includes 32 write amplifiers and 32 main amplifiers and 16 data input buffers and 16 data output buffers, respectively, provided for 115 *. Of these, the output terminal of each write amplifier and the input terminal of the main amplifier are connected to corresponding complementary common data lines CD00 * to CD01.
5 * or CD10 * to CD115, respectively. The input terminals of each write amplifier are commonly connected to the output terminals of two corresponding data input buffers, and the input terminals of each data input buffer are connected to the corresponding data input / output terminals D0 to D15. Further, the output terminals of each main amplifier are commonly connected to the input terminals of two corresponding data output buffers, and the output terminals of each data output buffer are connected to the corresponding data input / output terminals D0 to D0.
No. 15. The write amplifier and the main amplifier corresponding to the bank BANK0 are commonly supplied with the bank selection signal BS0, and the write amplifier and the main amplifier corresponding to the bank BANK1 are commonly supplied with the bank selection signal BS1. The internal control signal ML is commonly supplied to the write amplifiers and the data output buffers corresponding to the lower 8 bits of the data input / output terminals D0 to D7, and the write amplifiers corresponding to the upper 8 bits of the data input / output terminals D8 to D15. The internal control signal MU is commonly supplied to the amplifier and the data output buffer.

Each data input buffer of the data input / output circuit IO has a corresponding data input / output terminal D0 to D1 when the synchronous DRAM is selected in the write mode.
Then, the 16-bit write data supplied through the line 5 is fetched and transmitted to the corresponding two write amplifiers. Each write amplifier is selectively activated by setting the corresponding bank selection signal BS0 or BS1 to high level and setting the corresponding internal control signal MU or ML to low level. After the transmitted write data is converted into a predetermined complementary write signal, the corresponding complementary common data lines CD00 * to CD0
15 * or via CD10 * to CD115 *, data is selectively written into the selected 16 memory cells of the memory array MARY of the bank BANK0 or BANK1 eight by eight.

On the other hand, when the synchronous DRAM is selected in the read mode, each main amplifier of the data input / output circuit IO selectively operates by setting the corresponding bank select signal BS0 or BS1 to high level. State. In this operation state, each main amplifier is connected to the memory array MARY of the bank BANK0 or BANK1.
Of the corresponding complementary common data lines CD00 * to CD015 * or CD10 * from the selected 16 memory cells.
The binary read signal output through CD115 * is further amplified and transmitted to the corresponding data output buffer. In addition, each data output buffer is selectively or simultaneously operated by the corresponding internal control signal MU or ML being set to the low level, or eight at a time, and further amplifies the read data transmitted from the corresponding main amplifier. After that, the data is output to the outside of the synchronous DRAM via the corresponding data input / output terminals D0 to D15. The data input / output circuit IO outputs the read data to the clock signal CLK.
C for selectively delaying and outputting only the designated cycle of
An AS latency control circuit is included.

As a result, the synchronous D of this embodiment is
The RAM stores the designated bank BANK0 or BANK1.
Is a so-called 2-bank × 16-bit memory that simultaneously inputs or outputs 16-bit storage data. The input and output operations of the storage data are performed by data mask signals DQMU and DQML, that is, internal control signals MU and According to the ML, it can be selectively inhibited in 8-bit units.

The timing generation circuit TG includes a clock signal CLK supplied from the outside, a clock enable signal CKE serving as an activation control signal, a chip selection signal CSB, a row address strobe signal RASB, a column address strobe signal CASB, and a write enable signal WEB. In addition, the various internal control signals are selectively formed based on the data mask signals DQMU and DQML and the bank selection signals BS0 and BS1 supplied from the bank selection circuit BS, and supplied to the respective units.

The synchronous DR of this embodiment is
AM is, as described above, the X address signals AX0 to AX input in a time-division manner via the address input terminals A0 to Ai.
A pre-address buffer PB which takes in and holds the Xi or Y address signals AY0 to AYi according to the internal control signal PL is provided, and the row address buffer RB and the column address buffer CB hold the pre-address buffer PB according to the corresponding internal control signal RL or CL. X
Address signal AX0-AXi or Y address signal A
Y0 to AYi are taken. In this embodiment, the pre-address buffer PB is optimally arranged so that the distance between the address input terminals A0 to Ai is minimized, and the row address buffer RB and the column address decoder CD are arranged.
Are optimally arranged so that the distance between the row address decoder RD of the banks BANK0 and BANK1 or the column address decoder CD is as short as possible. The internal control signal PL is selectively set to an effective level in response to the rising change of the clock signal CLK, and the internal control signal RL
And CL are selectively set to valid levels in response to the low level of the row address strobe signal or the column address strobe signal at the rising edge of the clock signal.

From the above, in the synchronous DRAM of this embodiment, the row address buffer RB and the column address buffer CB are optimally arranged under the respective conditions, and their output signals, that is, the internal address signals X0-X.
As shown in FIG. 2, the rising edges of the clock signal CLK and the X address signal are generated in each of i and Y0 to Yi, despite the relatively large skew caused by the disposition of each address buffer and the inter-bit variation. The timing condition between AX0 to AXi and AY0 to AYi is determined by the optimally arranged pre-address buffer PB.
This corresponds to only the transmission time to the conventional DRAM, which is sufficiently reduced as compared with a conventional synchronous DRAM having no pre-address buffer PB. As a result, the setup time t _AS and the hold time t _AH of the X address signals AX0 to AXi and the Y address signals AY0 to AYi with respect to the clock signal CLK are correspondingly reduced, and the synchronous D
It is possible to accelerate the cycle time of the RAM.

FIG. 3 is a block diagram showing one embodiment of a computer system to which the synchronous DRAM of FIG. 1 is applied. An application example of the synchronous DRAM of this embodiment and its features will be described with reference to FIG.

In FIG. 3, the computer system of this embodiment has a so-called stored program type central processing unit CPU as a basic component. Although not particularly limited, the central processing unit CPU includes a system bus SBU.
Through S, a random access memory RAM1 composed of a normal static RAM and a random access memory RAM2 composed of a synchronous DRAM to which the present invention is applied are connected. On the system bus SBUS,
A read-only memory R such as a mask ROM
The OM, the display control device DPYC, the peripheral device controller PERC, and the power supply device POWS are coupled. Further, a display device DPY is coupled to the display control device DPYC, and the peripheral device controller P
A keyboard KBD and an external storage device EXM are connected to the ERC.

The central processing unit CPU performs step operations in accordance with a control program stored in a read-only memory ROM in advance, and controls and controls each unit of the computer system. The random access memory RAM1 is used, for example, as a cache memory, and the random access memory RAM2 is used, for example, as a read only memory R.
A control program, operation data, and the like transmitted from the OM to the central processing unit CPU are temporarily stored and used as a buffer memory for relaying.

On the other hand, the display control device DPYC
Built-in image memory VRAM, display device DPY
For display control. Also, the peripheral device controller P
The ERC controls and controls various peripheral devices such as a keyboard KBD and an external storage device EXM.
A stable predetermined DC power supply voltage is formed based on the predetermined input AC voltage and supplied to each unit of the computer system.

In this embodiment, the synchronous DRAM constituting the random access memory RAM 2 includes the pre-address buffer PB as described above, and outputs the X address signals AX0 to AXi and the Y address signals AY0 to AYi for the clock signal CLK. The cycle time is shortened by shortening the setup time and the hold time. As a result, the speed of the random access memory RAM2 is increased, and thereby the speed of the computer system including the random access memory RAM2 is promoted. In addition, by configuring the image memory VRAM of the display control device DPYC as a synchronous DRAM, it is possible to promote a further increase in the speed of the computer system.

As shown in the present embodiment, by applying the present invention to a semiconductor memory device such as a synchronous DRAM employing an address multiplex system, the following operation and effect can be obtained. (1) An address multiplex system in which an X address signal provided for row selection and a Y address signal provided for column selection are input in a time-sharing manner through a common address input terminal, and its operation is performed. Are synchronized in accordance with a predetermined clock signal in a synchronous DRAM or the like, and the address input terminal is disposed in close proximity to the address input terminal according to a first internal control signal selectively set to a valid level in response to a rise of the clock signal. And a pre-address buffer for receiving and holding an X-address signal or a Y-address signal input through the memory, and at the subsequent stage, when the clock signal changes to a valid level, the row address strobe signal or the column address strobe signal is set to a valid level. The second level that is selectively made effective level in response to the Alternatively, by providing a row address buffer and a column address buffer that take in and hold an X address signal or a Y address signal held in a pre-address buffer according to a third internal control signal, an X address signal input via an address input terminal And the Y address signal is first taken into the optimally arranged pre-address buffer, and then transmitted to the optimally arranged row address buffer and column address buffer under the respective conditions.

(2) According to the above item (1), an effect is obtained that the setup time and the hold time of the X address signal and the Y address signal with respect to the clock signal can be correspondingly reduced. (3) According to the above items (1) and (2), the effect of accelerating the cycle time of the synchronous DRAM or the like can be obtained.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist of the invention. Needless to say, there is. For example, in FIG. 1, the synchronous DRAM can adopt an arbitrary bit configuration such as a so-called × 1 bit or × 8 bit configuration. Also, synchronous DRAM has
Any number of banks can be provided, and each bank can be divided into a plurality of mats. The data input / output terminals D0 to D15 can be dedicated as data input terminals and data output terminals. Further, the block configuration of the synchronous DRAM is not restricted by this embodiment, and various embodiments can be adopted for the combination of the start control signal, the address signal and the internal control signal, the logic level, and the like shown in FIG.

In the above description, the case where the invention made by the present inventor is mainly applied to the synchronous DRAM which is the field of application as the background has been described.
The present invention is not limited to this, and can be applied to, for example, various memory integrated circuits such as a dynamic RAM employing the same address multiplex system, and a logic integrated circuit device equipped with these memory integrated circuits. The present invention
The invention can be widely applied to at least a semiconductor memory device employing an address multiplex system, and a device and a system including such a semiconductor memory device.

[0043]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, an address multiplex system is adopted in which an X address signal provided for row selection and a Y address signal provided for column selection are input in a time-sharing manner through a common address input terminal, and the operation thereof is performed in a predetermined manner. In a synchronous DRAM or the like which is synchronized according to a clock signal, the synchronous DRAM is arranged via an address input terminal in accordance with a first internal control signal which is arranged close to an address input terminal and is selectively set to a valid level in response to a rise of the clock signal. In addition to providing a pre-address buffer that captures and holds an input X address signal or Y address signal,
In the subsequent stage, when the row address strobe signal or the column address strobe signal is already at the effective level when the clock signal changes to the effective level, the second or third signal is selectively made to be the effective level, respectively.
A row address buffer and a column address buffer that take in and hold an X address signal or a Y address signal held in a pre-address buffer in accordance with an internal control signal of The signal and the Y address signal are first taken into the optimally arranged pre-address buffer and then transmitted to the optimally arranged row address buffer and column address buffer under the respective conditions. , The setup time and the hold time can be shortened, and the cycle time of a synchronous DRAM or the like can be shortened.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a synchronous DRAM to which the present invention is applied.

FIG. 2 is a signal waveform diagram showing one embodiment of the synchronous DRAM of FIG. 1;

FIG. 3 is a block diagram showing one embodiment of a computer system to which the synchronous DRAM of FIG. 1 is applied.

FIG. 4 is a block diagram showing an example of a conventional synchronous DRAM.

FIG. 5 is a signal waveform diagram showing an example of the synchronous DRAM of FIG. 4;

[Explanation of symbols]

BANK0-BANK1 ... Bank, MARY ...
Memory array, RD... Row address decoder, SA
... Sense amplifier, CD ... Column address decoder, BS ... Bank selection circuit, RB ... Row address buffer, CB ... Column address buffer, PB
... Pre-address buffer, RFC ... Refresh address counter, IO ... Data input / output circuit, T
G: timing generation circuit. CPU: central processing unit, SBUS: system bus, RAM1 to RAM2: random access memory, ROM: read-only memory, DPYC:
..Display control device, VRAM ... Image memory, DPY ... Display device, PERC ... Peripheral device controller, KBD ... Keyboard, EXM
... External storage device, POWS ... Power supply device.

Claims (9)

(57) [Claims] 1. A take address multiplex system and a Y address signal is subjected to an X address signal and a column selection to be used for row selection is inputted through the common external terminal, its
Operation is synchronized according to a predetermined clock signal.
A body address storage device , wherein the semiconductor memory device captures and holds the X address signal or the Y address signal input via the external terminal according to a first internal control signal; holding uptake and row address buffer for according to the two internal control signals for holding captures the X address signal held in the pre-address buffer, the Y address signal held in the pre-address buffer in accordance with the third internal control signal ; and a column address buffer for said first internal control signal is valid of the clock signal level
The second internal control signal is selectively set to an effective level in response to the change to the effective level of the clock signal.
The row address strobe signal
Select the effective level in response to the effective level
And the third internal control signal is an effective level of the clock signal.
Column address strobe signal
Is selected as the effective level
A semiconductor memory device characterized in that it is a semiconductor memory device. 2. The method of claim 1, said semiconductor memory device, a semiconductor memory device according to feature the this <br/> and a synchronous DRAM. 3. The semiconductor memory device according to claim 1, further comprising a refresh address counter for outputting a refresh address signal to the row address buffer in a refresh mode. A semiconductor memory device, wherein an address buffer receives the second internal control signal and the fourth internal control signal and selectively takes in the X address signal or the refresh address signal. 4. The row address buffer according to claim 3, wherein the row address buffer captures the X address signal when the second internal control signal is set to a predetermined level, and sets the fourth internal control signal to a predetermined level. A semiconductor memory device which takes in the refresh address signal when the semiconductor memory device is turned on. 5. The semiconductor memory device according to claim 1, further comprising: a plurality of memory cells disposed at intersections of a plurality of word lines and a plurality of bit lines; A burst counter for generating a column address for selecting one of the plurality of memory cells in a burst mode for continuously outputting data of the plurality of memory cells connected to the selected word line. the semiconductor memory device according to feature to include. 6. In any one of claims 1 to 5, the pre-address buffer, a semiconductor memory device according to feature that is intended to be arranged close to the external terminal. 7. The semiconductor memory device according to claim 5, wherein the semiconductor memory device receives an output of the row address buffer and selects one of the plurality of word lines, and the column address decoder includes: A column address decoder for receiving an output of the address buffer and selecting one of the bit lines, wherein the row address buffer is disposed in proximity to the row address decoder; the semiconductor memory device according to feature to be arranged close to the column address decoder. 8. A plurality of memory cells provided at intersections of a plurality of word lines and a plurality of bit lines; a row address decoder for selecting one of the plurality of word lines based on X address information; a row address buffer for outputting the column address decoders and, the row address decoder holding the X address information for selecting one of said plurality of bit lines by the information, the holding the Y address information A column address buffer for outputting to the column address decoder, and holding the X address information and the Y address information;
Respectively and a pre-address buffer for outputting to said row address buffer and said column address buffer, the row address buffer receives a first internal control signal
Captures the X address information Te, the column address buffer receiving a second internal control signal
And the pre-address buffer receives the third internal control signal.
The X address information and the Y address information
Seen, the first internal control signal, based on the clock signal
And the second internal control signal includes a row address and the clock signal.
The third internal control signal is based on the clock signal and the column address.
The semiconductor memory device according to feature a call is based on the address strobe signal. 9. The semiconductor memory device according to claim 8, wherein the X address information and the Y address information are input by an address multiplex method, and the plurality of memory cells are dynamic memory cells. Semiconductor storage device.