JPS62256142A - Memory expansion system - Google Patents

Abstract

PURPOSE:To easily replace a cartridge equipped with a large capacity memory or a memory by writing the prescribed bits among data output signals in the memory and setting them as a part of address signals in the memory. CONSTITUTION:The prescribed bit of the data output signals in ROMs 1 and 2 is written in a register 3 and taken for some part of address signals (A14-A00) in the ROMs 1 and 2. Therefore even if due to the progress of LSI manufacturing techniques the full capacity of a memory LSI is improved to increase the number of address input wires, the increase in the full capacity of the memory LSI can be easily handled by increasing the number of bits of the register 3. If the bit width of the register 3 lies within the bit width of a data signal, no additional connection terminal is needed, and the modification of an address decoder circuit in a device main body is unnecessary. When the output of the prescribed bits from the register is controlled by a specific address signal, half a memory space allocated to an expansion memory is associated with a fixed segment in the memory LSI without fail and used for storing resident data.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a memory expansion method, and more particularly to a memory expansion method for a small-sized information processing device intended to be portable.

Conventional technology Conventionally, this type of memory expansion method has a memory LS on the board.
1. An address decoding circuit, a data buffer circuit, etc. were mounted and wired, and connected to the address bus and data bus of the system via a connector in a slot provided in the information processing device.

In recent years, there has been a strong demand for miniaturization of information processing equipment.
There is also a need for memory expansion methods to be smaller and easier to replace in order to accommodate portable devices. For this reason, a method has been adopted in which the memory LSI is housed in a cartridge-shaped or card-shaped case and removably installed in an information processing apparatus. In this case, the address decoding circuit and data buffer 1 are designed so that the memory LSI case can be made smaller.
Prepare circuits etc. inside the information processing device main body and store them in memory S(
is implemented inside the case.

In such conventional memory expansion methods, since the address decoding circuit is located on the main body side, the memory capacity must be a predetermined capacity. However, it has the disadvantage that it cannot be replaced with other memory, and has poor expandability.

OBJECT OF THE INVENTION The present invention has been made to eliminate the drawbacks of the conventional ones as described above, and provides a memory expansion system that allows easy replacement of cartridges or memories equipped with large-capacity memory LSIs, and is expandable. The purpose is to provide a method.

Another object of the present invention is to provide a memory expansion method that allows half of the memory space allocated to the expansion memory to always correspond to a certain section of the memory LSI and to be used for storing resident data.

The memory expansion method according to the present invention is a memory expansion method for a memory that is removable from the main body of an information processing device, and includes a storage means for writing predetermined bits of the data output signal of the memory. the predetermined bit of the storage means is part of an address signal to the memory, and the output of the output signal of the storage means is controlled by a predetermined specific address signal of the address signal. It is characterized by what it did.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, the memory device of this embodiment has one address input.
It consists of read-only memories (hereinafter referred to as ROM) 1 and 2 of 7 bits, 8 bits of data output, and a 1M bit capacity, and a 3-bit register 3.

To the ROMI, an address bus 14 is connected to 14-bit address inputs (A13 to A00) from an information processing apparatus (not shown) (hereinafter referred to as the apparatus main body). Also, ROM
1 is connected to a selection signal line 15 and a read signal line 17. A data bus 11 is connected to the data output (07 to Do) of ROMI, and the upper 8 bits of the data signal are sent to the ROMI.
It is output from M1 to the main body of the device.

An address bus 14 from the main body of the device is connected to the ROM 2 to 14-bit addresses (A13 to 800). In addition, the ROM2 has a selection signal tfj16 and a readout signal 1.
a17 is connected. ROM2 data output (D
7 to Do> are connected to a data path controller 2, and the lower 8 bits of the data signal are outputted from the ROM 2 to the main body of the device.

A data pathcoder 2a from the ROM2 is connected to the register 3, and the lower 3 bits of data output from the ROM2 (Do to D2) are connected to the register 3.
) is input, register write signal line 1 from the device main body
3 is connected. Also, the most significant bit of the address signal from the main body of the device is sent to the OE of the register 3 via the signal line 14a.
(out enable) input, and the address bus 18 from register 3 is input to the address input (A
16 to A14) respectively, and the address input top 3
Output the bit to ROM1.2.

In this configuration, when a pulse signal is input to the register 3 from the main body of the device via the register write signal line 13, the register 3 receives the data of the lower 3 bits (D0 to D2) of the data output of the ROM 2 via the data bus 12a. This value is taken into address input No. J (A16~A) of ROM1゜2.
14) respectively.

ROM1.2 has selection signal line 15.16 and readout signal line 1
7 and 131 are active, depending on the signal state of each address input A16 to AOO.
, 072 (1 byte of data among the 217 bytes) is output from each data output D7 to Do.

Therefore, in this embodiment, the selection signal line 15.1 from the main body of the device is
By appropriately controlling 6 and the read signal line 17,
The upper and lower 16 bits of data can be read simultaneously, or only the upper or lower 8 bits of data can be read.

As a system, it is sufficient to allocate 65,536 (215 x 2) bytes of memory space for extended memory.

FIG. 2 is a diagram showing the correspondence between the memory space of the device main body and the partitions of the memory LSr according to an embodiment of the present invention.
The relationship between I and the section will be explained.

If we define the output prohibition function of register 3 as fixing all outputs to ``1'' when the OE large input is ``1'', the OE large input is the first half of the memory space because the most significant bit of the address signal from the device main body is input. (When OE large input rOJ), the set value of register 3 becomes the upper address of ROM1.2, and in the latter half of the memory space (when OE large input "1"),
R.O.I.V.I.

In the upper address of 2, all 3 bits are "1".

In this example, the total capacity of the extended memory 0 is 65.536X22
-262,414 bytes, but this total capacity is 65.
If it is divided into sections of 536/2 bytes each, it can be divided into eight sections. As shown in Figure 2, if the partitions are named by numbering them in ascending order of the input value of the upper 3 bits of the address signal, then when accessing the first half of the memory space allocated to the extended memory, the settings in register 3 Depending on the value, you can access all sections from section 0 to section 7.

On the other hand, when accessing the latter half of the memory space, partition No. 7 can always be accessed.

In this way, in the latter half of the memory space, partition No. 7 can always be accessed, so information such as a program for partition switching and index data can be stored in partition No. 7. In other words, the latter half of the memory space is a resident section, and section No. 7 of the memory LSI can be used to store resident data.

In this way, a predetermined bit of the data output signal of ROM1.2 is written to the register 3, and this is written to the ROM1.2.
With the advancement of memory LSI manufacturing technology, memory LSI
Even if the total capacity of I increases and the number of address input lines increases, the increase in the total capacity of the memory LSI can be easily accommodated by increasing the number of bits of the register 3. In this case, as long as the bit width of register 3 does not exceed the bit width of the data signal, there is no need for an extra connection terminal, and there is no need to change the address decoding circuit of the device itself. It is possible to easily convert a cartridge or memory equipped with a memory LSI.

In addition, by controlling the output of a predetermined bit from the register 3 using a specific address signal, half of the memory space allocated to the extended memory can always be made to correspond to a certain section of the memory LSI as a resident section. It can be used to store data. At the same time, the remaining half of the memory space can be made to correspond to any section of the memory LSI according to the setting value of the register 3.

As explained above, according to the present invention, by writing a predetermined bit of the data output signal of the memory LSI into the register and making it part of the address signal of the memory LSI, It is possible to easily replace a cartridge or memory mounted with a large-sized memory LSI, and it is possible to provide an extensible memory expansion method.

Further, according to the present invention, by controlling the output of a predetermined bit from the register using a specific address signal, half of the memory space allocated to the extended memory is always kept in the memory LS.
The advantage is that it is possible to provide a memory expansion method that can be used to store resident data in correspondence with a certain partition of I.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a diagram showing the correspondence between the memory space of the main body of the apparatus and the partitions of the memory SL according to one embodiment of the present invention. Explanation of symbols of main parts 1.2... Read-only memory (ROM) 3...
····register

Claims (1)

[Claims] A memory expansion method for a memory that is removable from an information processing device main body, the memory having a storage means for writing a predetermined bit of a data output signal of the memory, the predetermined bit of the storage means being written into the memory. 1. A memory expansion method, characterized in that the output signal of the storage means is made part of an address signal to the address signal, and the output of the output signal of the storage means is controlled by a predetermined specific address signal of the address signal.