JPS61133097A - Memory write system - Google Patents

Abstract

PURPOSE:To reduce the procedure of parts management and to prevent the error of memory mounting, by connecting a jig to a machine and accessing the memory of the machine with a different address from the one which is generally used when the machine is used as a signal unit basing on the copy control program and by copying the contents of the master memory to a machine memory. CONSTITUTION:When making copy, blank ROM's are mounted at the specific position 84d1-815 of a machine 1, and copy the contents of master ROMs 111-1116 to the ROM 81-815 of the machine 1 according to the copy program from the copy control ROM 12 of a jig 10. In this case as the one side input terminal of an AND gate G1 of a logic circuit 16 is grounded through terminals 1e, 10e by the connection of the machine 1 and the jig 10, the ROM 81-815 of the machine side cannot be accessed with the address which is used when the machine is used as a single unit. Therefore, the access and copy is done using a different address according to the copy program of the copy control ROM 12. In this way, the procedure of parts management can be reduced, the errors in mounting the memory is prevented, and productivity will be improved.

Description

[Detailed Description of the Invention] 'Industrial Application Field The present invention relates to a memory writing method, which is a conventional technique for writing contents such as programs and data used when the device is used alone into the memory of a device with a built-in CPU. In recent years, RO is controlled by a built-in microcomputer.
Various electronic devices have been developed that are configured to read audio digital data written in M, convert it into an analog signal, and generate sound from a speaker.

The above-mentioned ROM, CPU, etc. are provided on a board called a voice synthesis board, and the manufacturer performs the task of writing voice data into the ROM as follows. First, the audio digital data is written and saved in a mask ROM separate from the device along with a microcomputer control program.
Next, during mass production, the audio data from this mask ROM was copied to the ROM of the device, and this was attached to the ROM IC connector.

In this case, if only one ROM is to be incorporated into the device, it is sufficient to make a copy ROM for the number of production valves in advance, attach it to the board like other parts, and pour it into the solder bath.
There are no particular problems.

Problems to be Solved by the Invention However, when there are many programs and audio data, and a large number of ROMs are required to be incorporated into a device, different audio data will be written to each ROM of the same shape and model number, and these A sticker or the like is pasted on each ROM to distinguish them from each other. For this reason, there are problems such as an increase in the effort required to manage parts, and there is also a problem that there is a high possibility that the parts will be incorrectly installed in the equipment.

Furthermore, when it becomes necessary to replace the ROM due to incorrect installation, etc., the ROM is not directly soldered, but is installed via an IC connector to facilitate replacement. For this reason, there were problems in that the number of parts increased and it was difficult to reduce the size and weight.

In the present invention, when writing predetermined contents to the memory of a device,
To provide a memory writing method that requires less time and effort for parts management, eliminates the risk of erroneously installing memory into equipment as in the past, and allows equipment to be configured with fewer parts, making it more compact, and allowing it to stand the test of time. With the goal.

Means to solve problems Part 2 shows a diagram of the performance realizing means of the present invention.

In the figure, 20 is a master memory means in which contents to be written to the device memory means 21 of the device 1 are stored, and 22 is a copy control memory means in which a copy control program is stored, both of which are provided in the jig 10. . 23 is a read and write control means composed of a CPU, and 24 is a device 1.
The device 1 is also provided with address switching means for switching the address so that when the device memory means 21 is connected to the jig 10, the device memory means 21 is accessed at an address different from the address when the device is used alone.

Operation In FIG. 2, when the jig 10 is connected to the i-device 1, the address switching means 24 makes it impossible to access the device memory means 21 at the address when the device is used alone, and the copy control program in the copy control memory means 22 is changed. Accordingly, the device memory means 21 is stored at an address different from the address when the device is used alone.
is accessed to copy the contents of the master memory means 20 to the device memory means 21.

Embodiment FIG. 1 shows a circuit diagram for explaining an embodiment of the system of the present invention. In the figure, 1 is the voice synthesis board of the device, and the CPU
2.10 board 3, decoder 4°5, DA converter 6, amplifier 7, ROM8+ described later.

82, . . . , 816, a logic circuit 16 is provided, and when the device is used alone, the ROM 81 is
The audio data read from the ROMs 8+ to 816 is subjected to OA conversion by the DA converter 6 in accordance with the control program for use of the equipment stored in the ROMs 816 to 816, and is supplied to the speaker 9 via the amplifier 7 for sound generation.

One input terminal of the AND gate G1 of the logic circuit 16 is connected to the write control signal output terminal for accessing addresses 0000 to 3FFF of the decoder 4, and the other input terminal is connected to the power supply +Vcc and the terminal 1e. There is.

Also, one input terminal of the AND gate G2 is connected to each BA described later.
It is connected to the write control signal output terminal for accessing addresses 8000 to BFFF of the decoder 4 connected to the AND gate provided in the NK, and the other input terminal is an output terminal for accessing the BANKφ of the decoder 5. connected to the terminal. ANDGATE G+.

The output terminal of β2 is connected to the chip select CSt of the ROM 81 via an OR gate G3.

In addition, the area accessed by addresses 0000 to 3FFF of ROM 8+ and the area accessed from addresses 8000 to BFFF
The areas accessed by address are structured the same way.

On the other hand, 10 is a jig and is a master ROM11+.

112,...+11 +6, copy control ROM1
2. A decoder 14 is provided, and its terminals 10a~
1C) e can be connected to terminals 1a to 1e of device 1. Terminal 10e is grounded. Master R
OM11+ to 1116 store audio data to be copied to ROM8+ to 816 of device 1 and a control program (hereinafter referred to as a single program) when the device is used alone, and ROM12 for copy control stores? Star ROM11
+ ~1116(7) Contents of device 1 ROM 8 +~
A copy control program (hereinafter referred to as a copy program) for copying to 816 is stored.

Here, when copying, insert a ROM with nothing written into it in the predetermined positions 81 to 816 of the device 1,
After that, according to the copy program from the copy control ROM 12 of the jig 10, the mask ROM 11+ to 1116
Copy the contents to the ROMs 81 to 816 of device 1.

In this case, please note that when copying the standalone program and audio data to ROM8+ to ROM816, do not access it at an address (for example, after 8000) that is different from the address used for access when using the device alone (for example, after 0000). It is necessary to make a copy. in general,
Since the program is to be accessed from address 0000 after being reset, copy it to the device side ROM 8.
If + to 816 remain accessed from the same address 0000 as when used alone, copy control ROM1
2 cannot be assigned to address 0000.

In addition, in this case, for example, a copy control ROM is provided on the jig 10 side.
12. When a copy control CPU is provided, the C on the jig 10 side
The address output and data output from both the PU and the CPU 2 on the device 1 side will be output to the data bus at the same time.
This causes inconvenience that prevents normal operation.

Therefore, in the method of the present invention, as described later, during copying, the CPU 2 of the device 1 accesses the copy control ROM 12 from address 0000, and the contents of the master ROM 11+ to 1116 are transferred to the device side ROM 8+ to 816 when the device is used alone. Access and copy only from address 8000 onwards, which is different from .

Now, when the jig 10 is connected to the device 1, one input terminal of the AND gate GI of the logic circuit 16 is connected to the terminals 1e and 10e.
Since it is grounded through the device side ROM8+~816
cannot be accessed from addresses 0000 to 3FFF.

FIG. 3 shows a flowchart for explaining the operation of the circuit diagram shown in FIG. In FIG. 1, the copy control ROM 12 is operated by a control signal from the CPU 2, and the copy control ROM 12 is operated by a control signal from the CPU 2.
Master ROM11 according to the copy program of OM12
The audio data, evening program, and single program are read from the buffers 15 and 1116 (step 100 in FIG. 3).
It is written to ROM8+ to 816 via PU 2 (step 101). In this case, the copy control ROM 12 is accessed from address 0000, while the ROM 8+ is accessed from address aooo by the write control signal from the decoder 4, and when the device is used alone, the ROM 8+ is accessed from address 0000.
It is written in the area from address o to address 3FFF.

Next, the address is incremented (step 102),
It is determined whether or not copying has been completed (step 103), and if not, the process returns to step 100 and the above operations are repeated.
If finished, the above operation ends.

In addition, reading from ROM11+ to 1116, ROM
Writing to 8+ to 816 is performed as follows.

ROM81.82.111.112 BANKO1RO
Set M83.84, 113, 114 as BANK to each ROM provided in jig io and i device 1.
Set each BANK from O to BANK7. The bank address (BA) from the 10 port 3 is sequentially supplied to each BANK as a read control signal by the decoder 14 and a write control signal by the decoder 5, and each BANK is sequentially placed into read mode and write mode in a time-sharing manner. control.

In this way, the ROM 8+ is accessed at an address different from the address when the device is used alone, and the mask ROMs 111 to 111 are accessed.
The contents of 6 are copied to ROMs 8+ to 816 in correspondence with each other.

When the copying is completed and the jig is removed from the device 1, one input terminal of the AND gate G+ of the logic circuit 16 is connected to the power supply terminal Vc.
Since it is connected to c, it can be accessed from address 0000. Here, when using device 1 alone,
ROM 8+ is an area of address 0000, that is, 80 which is written at the time of copying by the read control signal from the decoder 4.
It is accessed from area 00 and predetermined audio data is read out according to a single program in ROM 8+.

In addition, in the above embodiment, when the device is used alone, addresses from 0000 to
Even if you access address 3FFF, address 8000 ~ BFFF
Although the configuration is such that the same area of ROM8+ is selected even if the address is accessed, the configuration is not limited to this, and by appropriately changing the gate connection of the logic circuit 16, only addresses 8000 to BFFF can be accessed at one time. I can do it,
When the device is used alone, it may be configured so that only addresses 0000 to 3FFF can be accessed.

Furthermore, the logic circuit 16 may be configured to operate not only with positive logic but also with negative logic.

Further, the address number is not limited to the one in the above embodiment.

Further, although an 8-bit microcomputer is used in the above embodiment, a 4-bit or 16-bit microcomputer may also be used.

Further, as the master memory of the jig 10, in addition to the ROM as in the above embodiment, a magnetic tape, a floppy disk, etc. may be used.

Effects of the Invention The method of the present invention, when writing contents such as programs and data used when the device is used alone, to the memory of a device with a built-in CPU, writes the contents to be written to the device memory with the stored master memory. Connect a jig equipped with a copy control memory storing a copy control program used at times to the above device, and according to the copy control program controlled by the CPU, set an address different from the address when the device is used alone. Since the memory of the above device is accessed at the address and the above contents of the above master memory are copied to the memory of the above device, a memory with no information written is installed in the device in advance, and after that, If the contents of the master memory of the jig are copied to this memory using the specific address mentioned above, especially when a large number of memories are installed in the device, each memory can be managed one by one as before. This eliminates the need for parts management, greatly reduces the effort involved in parts management, and eliminates the risk of memory being installed incorrectly, which greatly improves productivity. (1) Since there is no C connector, the number of parts is small, and it has features such as being compact, lightweight, and can be constructed at low cost.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram for explaining an embodiment of the method of the present invention, FIG. 2 is a diagram of a function realizing means of the method of the present invention, and FIG. 3 is a flowchart for explaining the operation of the circuit diagram shown in FIG. . i/i device, 1a to 1e, 10a to 10e...terminal, 2
...CPU, 3...[0 port, 4,5.13゜1
4...Decoder, 81-816...Device side ROM,
10... Jig, 111-1116... Master ROM
. 12... ROM for copy control, 15... Buffer,
16...Logic circuit, G+, G2...AND gate, G3...OR gate.

Claims (1)

[Claims] When writing contents such as programs and data used when the device is used alone to the memory of a device with a built-in CPU, the contents to be written to the device's memory are stored in the master memory and the copy used at the time of writing. A jig equipped with a copy control memory storing a control program is connected to the device, and according to the copy control program controlled by the CPU, the device is moved to an address different from the address when the device is used alone. A memory writing method characterized in that the content of the master memory is copied to the memory of the device by accessing the memory of the device.