JP2968636B2 - Microcomputer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly to a microcomputer having a display function.

[0002]

2. Description of the Related Art Referring to FIG. 2, which shows a block diagram of a conventional microcomputer with a built-in display function, a conventional microcomputer with a built-in display function includes a microcomputer data memory for controlling data of the microcomputer. Since the RAM 1 cannot be used as a display character data memory (hereinafter referred to as VRAM) 3, a VRAM 3 having the same scale as the RAM 1 is provided, all the display character data in the temporary RAM 1 is transferred to the VRAM 3, and the display circuit (not shown). Used. The display character data may be congested with different display character address data and display character control data.

Next, a display circuit (not shown) identifies the display character address data or the display character control data by the data identification circuit 2 when reading the VRAM 3 and stores the display character address data in the address latch 7 and the display character control. Data is latched in the control latch 8, respectively.

[0004]

In a conventional microcomputer, an address latch and a control latch are required on the display circuit side, and display character address data and display character controller data are set irregularly. When data and display character control data are mixed , two data must be read at a time, and when there is no display character control data, only the display address data must be read. Therefore, it is difficult to design the read timing of the VRAM. When two data are read at a time, there is a problem that the read time is strict because the data is read in a time-division manner.

[0005]

A microcomputer according to the present invention comprises a data memory for a microcomputer for storing display character data including display character address data and display character control data, wherein the display character data is stored in the display character address. A data identification circuit for determining whether the data is the display character control data, a first dedicated memory for transferring and storing the display character data from the data memory when the display character data is display character address data; When the character data is display character control data, a microcomputer having a second dedicated memory for transferring and storing the display character data from the data memory, wherein the display character data is transferred from the data memory to the data identification circuit. And the data identification circuit It is determined whether the display character data is the display character address data or the display character control data, and if the display character data is the display character address data, the display character data is transferred from the data memory to the first dedicated memory. When the display character data is display character control data, a display preparation operation of transferring the display character data from the data memory to the second dedicated memory is performed for all data stored in the data memory. By doing so, the first dedicated memory and
And reading of the second dedicated memory from the display circuit.
It is a configuration that.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

Referring to FIG. 1, which shows a schematic diagram of a microcomputer according to an embodiment of the present invention, a VRAM 3 of the microcomputer according to an embodiment of the present invention includes an address memory 4 as a memory for display character addresses and a display character control. And a control memory 5. The display character data is transferred from the RAM 1 used in the microcomputer to the data identification circuit 2 and the data identification circuit 2 determines whether the data is address data or control data. Transfer data.

A microcomputer according to an embodiment of the present invention will be described in detail with reference to FIG. CP
The RAM 1 is a microcomputer data memory in which display character data is stored in a data bus 51 of U.
1 is connected via a readout circuit 23, and an address memory 14 and a control memory 15 for storing display character data for a display circuit via a write circuit 29 and a write circuit 32, respectively. Further, the data bus 51 is also connected to the data discriminating circuit 12, the output of which is used as the write enable signal 54 to form the write circuit 29 and the selector 3
5 to the write circuit 32 and the selector 36 via the inverter 30.

The RAM address increase clock 50 is input to the address generation circuit 21, the selector 35 and the selector 36, and is output when one data transfer is completed. The address generation circuit 21 is connected to the RAM 11 via the decoder 22.

To the selector 35 and the selector 36, an address memory increase clock 52 and a control memory increase clock 55, which are signals for increasing addresses when the display circuit reads the address memory 14 and the control memory 15, respectively, are inputted. Further, the clock signal of the address generation circuit 24 and the address generation circuit 27 is selected by the transfer enable signal 53.
Address generation circuit 24 and address generation circuit 27 are connected to address memory 14 and control memory 15 via decoder 25 and decoder 26, respectively.

A read circuit 28 and a read circuit 31 are provided in the address memory 14 and the control memory 15, respectively, and are configured to output an address memory output 33 and a control memory output 34, respectively.

Next, the operation of the microcomputer according to one embodiment of the present invention will be described. When data is transferred from the RAM 11 to the address memory 14 and the control memory 15, the transfer enable signal 53 is set to, for example, "1".
Level. The display character data stored in the RAM 11 is output to the data bus 51 via the read circuit 23. At this time, the write enable signal 54 becomes, for example, "1" level for display character address data by the data discriminating circuit 12 and "0" level for display character control data.

If the transfer data is display character address data, the write enable signal 54 becomes "1" level. As a result, the write circuit 29 becomes active, and the address memory 1 pointed to by the address generation circuit 24.
The value of the data bus 51 is written to the address 4 as it is. When the write enable signal 54 is "1", the inverter 30 makes the write circuit 32 and the selector 36 inactive and does nothing.

When the writing is completed, the RAM address increase clock 50 is output, so that the clock is supplied to the address generation circuit 21 and the address generation circuit 24, the address is increased by one, and the preparation for the next data transfer is completed.

On the other hand, if the transfer data is the display character control data, the write enable signal 54 becomes, for example, "0" level. As a result, the write circuit 29 and the selector 35 become inactive and do nothing, but the write circuit 32 and the selector 36 become active by the inverter 30 and the address generation circuit 27
The value of the data bus 51 is written to the control memory as it is at the address specified by (1). When writing is completed, RA
The M address increase clock 50 is output, and the values of the address generation circuit 21 and the address generation circuit 27 are increased by one to prepare for the next data transfer.

This operation is performed for all data of the RMA 11, and the transfer is completed. When the transfer is completed, the transfer enable signal 53 becomes, for example, "0" level, and the control of the selector 35 and the selector 36 is switched, so that the address memory 14
The reading of the control memory 15 can be performed from the display circuit. As a result, the display circuit performs one VRA
By accessing M, outputs can be obtained at both the address memory output 33 and the control memory output 34.

[0017]

As described above, the present invention provides a VRAM
Is divided into an address memory and a control memory to identify data when transferring data from the RAM of the microcomputer, so that a single access to the VRAM can output data of both the address memory and the control memory. A latch for temporarily holding the output of the memory is not required. Moreover, the read time of the VRAM can be shortened by changing the circuit configuration.
Assuming that the reading time is t, in the conventional example, if there is display character control data, it takes 2 · t to read the VRAM. In other words, the read time of the VRAM is halved. Further, the VRAM timing does not need to be intermittently read depending on the presence or absence of the display character control code, so that the timing design of the VRAM of the display circuit is simplified. Therefore, there is a great effect on improving the VRAM reading efficiency of the display circuit.

[Brief description of the drawings]

FIG. 1 is a diagram showing blocks of a microcomputer according to an embodiment of the present invention.

FIG. 2 is a diagram showing blocks of a conventional microcomputer.

FIG. 3 is a diagram showing details of the embodiment shown in FIG. 1;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Data memory (RAM) for microcomputers 2 Data identification circuit 3 Character data memory (VRAM) 4 Address memory 5 Control memory 7 Address latch 8 Control latch 11 Data memory for microcomputer (RA
M) 12 data identification circuit 14 address memory 15 control memory 21 address generation circuit 22 decoder 23 read circuit 24 address generation circuit 25 decoder 26 decoder 27 address generation circuit 28 read circuit 29 write circuit 30 inverter 31 read circuit 32 write circuit 33 address memory Output 34 Control memory output 35 Selector 36 Selector 50 RAM address increase clock 51 Data bus 52 Address memory increase clock 53 Transfer enable signal 54 Write enable signal 55 Control memory increase clock

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G09G 5/00-5/40 G06F 3/14-3/153 340 G06F 15/76-15/78

Claims (1)

(57) [Claims] 1. A microcomputer data memory for storing display character data including display character address data and display character control data, and determining whether the display character data is the display character address data or the display character control data. A data identification circuit, and a first memory for transferring and storing the display character data from the data memory when the display character data is display character address data.
And a second dedicated memory for transferring and storing the display character data from the data memory when the display character data is display character control data. To the data identification circuit, the data identification circuit determines whether the display character data is the display character address data or the display character control data, and if the display character data is display character address data, Display preparation for transferring character data from the data memory to the first dedicated memory, and transferring the display character data from the data memory to the second dedicated memory when the display character data is display character control data. The operation is performed for all data stored in the data memory. By performed, the first dedicated Notes
And reading of the second dedicated memory from the display circuit
A microcomputer characterized by what it can do.