JPH023853A - Interface method for cpu - Google Patents

Abstract

PURPOSE:To permit CPU to write data at its own timing by preventing a control from making the read request of data to CPU while CPU executes the write action of data. CONSTITUTION:The control circuit 2, to which CPU 1 writes data while the control circuit 2 outputs the read request signal of data to CPU 1, cancels the read request 12 signal and re-outputs the read request signal 18 when the writing of data terminates. When the read request signal 29 of data is generated in the control circuit 2 while the CPU 1 writes data, the control circuit 2 outputs the read request signal 22 of data when the writing of data terminates. Even if there is or not the read request from the control circuit to CPU, CPU can write data at its own timing and the processing of CPU can be simplified.

Description

[Detailed Description of the Invention] (Industrial Application Field) Fig. 4 is a block circuit diagram showing the connection between a conventional CPU and a control circuit, and Fig. 5 is a diagram showing a timing chart of each part in Fig. 4. It is. The control circuit 2 that controls communication between CPtJl and the outside is a read/write signal line (R/
W)3. Data read request signal line (R-REQ) 4
．． 5 read/write pulse lines (RWP) and 8 data lines (D.

~D, )6. Now, when writing data to the control circuit 2, the CPU 1 outputs the "r low" signal 27 shown in FIG. 5(a) to the read/write signal line 3 to indicate that the data is being written. At this time, the control circuit 2 outputs a "low" output 28 (see FIG. 5) to the data read request signal line 4 to the CPUI to request data read.

When the read request signal line 4 becomes a "low" level, the CPU releases the "low" output of the read/write signal line 3 and sets the data read state as a "high" output 29 in FIG. 5(a). Thereafter, the CPU 1 uses the data read/write timing pulse 3 shown in the fifth [ff(e)].
0 to the read/write pulse line 5, and the control circuit 2 outputs the signal to the data line 6 in synchronization with this pulse line 5 as shown in FIG.
) is output. The CPU reads this output data 31, and when the read is completed, the control circuit 2 outputs the read request signal to the "high" level 32 in FIG. 5(b) to notify the CPU that there is no data read request. , then the CPU again switches to the control circuit 2.
In order to write data to the memory card, the output of the read/write signal line 3 is set to a "low" level 33.

(Problem M to be solved by the invention) However, in the conventional CPU interface method, if a data read request signal is frequently generated, the CPU
U causes problems in data writing, and there is a problem in that data cannot be freely read or written at the timing of the CPU.

The present invention has been made in view of the above circumstances, and is
It is an object of the present invention to provide a CPU interface method that simplifies processing in the U and allows data to be read/written at the CPU's free timing.

(Means for Solving the Problems) In order to achieve the above object, according to the present invention, data is read from the control circuit to the CPU between the CPU and the control circuit that controls communication with the outside, and the data is read out from the control circuit to the CPU. In the CPU interface method for writing data to the control circuit, when the CPU writes data to the control circuit while the control circuit is outputting a data read request signal to the CPU, the control circuit outputs the read request signal. and re-outputs the read request signal at the end of data writing, and when the data read request signal is generated in the control circuit while the CPU is writing data to the control circuit, the control circuit outputs the data. A CP that outputs the data read request signal at the end of writing.
A U interface method is provided.

(Function) Regardless of whether or not a data read request signal is output from the control circuit to the CPU, while the CPU is performing a data write operation, the control circuit does not request the CPU to read data; As a result, the CPU can write data at its own timing.

(Example) Hereinafter, an example of the present invention will be described in detail based on the accompanying drawings.

FIG. 1 is a block circuit diagram showing the connection between a CPU and a control circuit for explaining the CPtJ interface method of the present invention. The connection between the CPUI and the control circuit 2 is the same as that shown in FIG. First, when a read request signal is input to the control circuit 2 via the data read request signal line 8 to the D terminal of the flip-flop 7 of the control circuit 2, the flip-flop 7 is synchronized with the clock signal of the clock signal line 9. is set, and the control circuit 2 outputs the "low" output 12 shown in FIG. 2(b) to the data read request signal line 4 to the CPUI.
Requests PU1 to read data.

At this time, in order to write data to the control surface Wi2, the CPUI sets the read/write signal line 3, which indicates the presence or absence of data writing, to the "low" output 13 in FIG. 2(a).
Indicating data writing, at this time, the 7-liplock 7 of the control circuit 2 is reset, and the control circuit 2 sets the data read request signal line 4 to the "high" output 14 in FIG. 2(b), requesting the data read. will be temporarily suspended.

The CPU 1 reads the data shown in Figure 2 (,c).
A write timing pulse 15 is output to the read/write pulse line 5, and data 16 to be written is output to the data line 6 in synchronization with this timing pulse 15.

When the CPUI finishes writing the data, the read/write signal line 3 is set to the "high" output 1 shown in FIG. 2(a).
7 to indicate that no data is written to the control circuit 2. At this time, the reset of the flip-flop 7 is released, so the read request signal line 8 of the flip-flop 7 is set again in synchronization with the clock signal. Ru. The control circuit 2 connects the data read request signal line 4 again to the line shown in FIG.
b) "Set low J output to 18 and request data read from cpUl.

On the other hand, in order to write data to the control circuit 2, the CPUI sets the read/write signal line 3 to the "low" output 19 and writes the data, as shown in FIG. 3(a).

Even if the data read request signal 20 shown in FIG. 3(b) is generated in the control circuit 2 while the read/write signal line 3 is at a "low" level, the flip-flop 7 remains reset. sets read request signal line 4 to “high”
This will not notify the CPU that a data read request has occurred. When the writing of data from the CPUI to the control circuit 2 is completed and the CPU 1 sets the read/write signal line 3 to the "high" output 21 as shown in FIG. 3(a), the control circuit 2 releases the reset of the flip-flop. Then, in synchronization with the clock signal, the read request signal line 4 is set to a "low" output 22 (see FIG. 3), and a data read request is transmitted to the CPUI for the first time. in this way,
The CPUI can write data at its own timing.

(Effects of the Invention) As explained above, according to the present invention, communication between a CPU and a control circuit that controls communication with the outside is performed from the control circuit to the CPU.
In the CPU interface method of reading data to a U and writing data from the CPU to the control circuit, when the CPU writes data to the control circuit while the control circuit is outputting a data read request signal to the CPU, the CPU writes data to the control circuit. The control circuit cancels the read request signal and re-outputs the read request signal at the end of data writing, and a data read request signal is generated in the control circuit while the CPU is writing data to the control circuit. Then, the control circuit outputs the data read request signal at the end of data writing, thereby
Regardless of whether or not there is a request to read data from the control circuit to the CPU, the CPU can write data by its own timing, which has the effect of simplifying the processing of the CPU.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing the connection between the CPU and the control circuit for explaining the CPU interface method of the present invention, FIGS. 2 and 3 are timing charts of each part of FIG. 1, and FIG. FIG. 5 is a block diagram showing the connection between a CPU and a control circuit for explaining a conventional CPU interface method, and FIG. 5 is a timing chart of each part in FIG. DESCRIPTION OF SYMBOLS 1... CPU, 2... Control circuit, 3... Read/write signal line, 4... Data read request signal line, 5... Read/write pulse line, 6... Data line , 7...Flip-flop, 8...Data read request signal line, 9...Clock signal line. Figure 1 Figure 2

Claims (1)

[Claims] A CPU interface method in which data is read from the control circuit to the CPU and data is written from the CPU to the control circuit between the CPU and a control circuit that controls communication with the outside, wherein the control circuit reads data to the CPU. When the CPU writes data to the control circuit while outputting a request signal, the control circuit cancels the read request signal, re-outputs the read request signal at the end of data writing, and the CPU writes data to the control circuit. A CPC interface method, characterized in that when a data read request signal is generated in the control circuit while data is being written to the control circuit, the control circuit outputs the data read request signal at the end of data writing.