JP3028998B2 - DMA transfer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for transferring data between a personal computer and peripheral devices.

[0002]

2. Description of the Related Art Conventionally, when data is transferred in a DMA mode between a memory on a personal computer and a peripheral device, the data bus line of the CPU on the personal computer and the data bus line of the CPU on the peripheral device are shared. And the DMA controller temporarily suspends the CPU to directly transfer data between the peripheral device and the memory. Since such a DMA transfer is directly transferred from the input / output device to the memory without passing through the main CPU, the DMA controller outputs a BSRQ signal requesting the main CPU to use the bus line. Disconnect the bus line from the main CPU and temporarily disconnect the main CPU
During this period, a DMA controller outputs a timing signal for writing data to the memory or reading data from the memory from the DMA controller to perform DMA transfer.
The main CPU only activates the start of input / output, and all DMA controllers and sub CPUs automatically execute the transfer until the data transfer of one block is completed. However, in the above-mentioned DMA transfer, while the DMA mode is set, the main CPU is in the sleep mode, and during that time, the main CPU cannot perform processing. For example, there are input / output devices that perform high-speed processing. In such a case, there is a disadvantage that inconvenience occurs.

[0003]

As described above, in the conventional DMA transfer mode, since the main CPU is in a halt state for a long time during that period, there are input / output devices that perform high-speed processing. In such a case, there is a problem that the processing cannot be performed in time. It is an object of the present invention to solve the above-described problem and to provide a data transfer method using a single transfer method in which a main CPU does not pause for a long time.

[0004]

According to the present invention, in order to solve the above-mentioned problems, the DMA controller and a bus line of a CPU of the peripheral device are connected to each other, and a memory of the peripheral device and a bus of the peripheral device are connected to each other. The bus lines on the CPU side are connected to each other. The common bus line between the personal computer and the peripheral device is mutually connected via a connector, and the memory on the personal computer is mutually connected with the memory on the peripheral device via the register. The write control signal of the DMA controller is connected to the clock terminal of the second flip-flop, and the write terminal of the register is connected to the CPU 8 write terminal of the peripheral device. One of the output terminals of the second flip-flop is connected to one input of a first AND gate, the other of the output terminals is connected to a write flag terminal (WFLG) of the CPU on the peripheral device side, and the output terminal of the first AND gate is The other input is connected to the output terminal of the HLDREQ signal of the DMA controller, and the clear terminal of the second flip-flop is connected to the write terminal of the CPU on the peripheral device side. One input of the second AND gate is connected to the first
It is connected to one input of an AND gate and the output terminal of the HLDREQ signal of the DMA controller. One input terminal of the OR gate is connected to the output of the first AND gate, and the other input terminal of the OR gate is connected to the second AND gate.
Connected to the output of the gate, the write terminal of the CPU on the peripheral device side is connected to the clear terminal of the second flip-flop, and the clock terminal of the first flip-flop is connected to the DM terminal.
An output terminal of a read control signal of the A controller is connected, and a clear terminal of the first flip-flop is connected to an output terminal of a read signal of the CPU on the peripheral device side. The output terminal of the first flip-flop is connected to the second A
Connect to the input terminal of ND gate and C
It is connected to the read flag terminal (RFLG) of the PU, and the output of this second AND gate is connected to the input of the OR gate. The output of the OR gate is transmitted to the CP of the personal computer through the output terminal of the peripheral device card and the input terminal of the personal computer.
It is configured to connect to the U bus request signal (BUSREQ) terminal.

[0005]

With the above construction, the DM according to the present invention is provided.
In the A transfer circuit, in a single transfer from the input / output device to the personal computer, the CPU of the peripheral device polls the DMA controller to write a flag (WF).
LG) is always monitored, and the DMA controller sends the first data write control signal (IOWC).
And outputs a hold request signal (HLDREQ). One of the (IOWC) signals is input to the clock terminal of the second flip-flop.
Since the write signal (* WFLAG) is not yet output, the data terminal of the second flip-flop is
It remains at the “L” level. Therefore, the output of the first AND gate remains at the "L" level and is not input as a bus request signal of the CPU of the personal computer, but is masked, and the CPU of the personal computer is made operable during this time. . During this mask period, C on the peripheral device side
The PU outputs the first byte of data to the register and outputs a write signal (* WFLAG).
The data of the byte is written. In addition, (* WF
The LAG) signal causes the clear terminal of the second flip-flop to go to the "H" level and set to an operable state. Following the above, the second data write signal (IOWC) signal from the DMA controller and the HLDRE
A Q signal is output from the DMA controller. The second
Since the clear terminal of the flip-flop is set to the "H" level and set to an operable state, the HLDREQ signal is input as a bus request signal of the CPU of the personal computer, whereby the CPU of the personal computer is put into a halt state. During this time, the DMA controller writes the first byte of data written in the register to the memory of the personal computer, releases the output of the CPU (* WFLAG) of the peripheral device, and re-executes the bus request. The output of the signal is masked, and the CPU of the personal computer is returned to the operating state.
It requests the PU to perform a second data write operation, and thereafter repeats the same cycle as the first write,
Transfer a predetermined number of bytes of data. Next, the operation of single transfer of data from the personal computer to the peripheral device will be described. When the CPU of the personal computer wants to transfer data to the peripheral device, it outputs a write signal to the DMA controller. This signal allows the DMA
A controller outputs a read control signal (IORC) and a hold request signal (HLDREQ), inputs the read control signal (IORC) to a clock terminal of a first flip-flop, and latches the data for a predetermined period by the first flip-flop. The CPU on the side is put into a sleep state. During this pause, the CPU 8 of the peripheral device reads the data of the register written from the personal computer and writes the data in the memory of the peripheral device. As a result, the CPU of the peripheral device reads the signal (* R
FLG), releases the HOLDREQ signal latched by the first flip-flop, and returns the CPU of the personal computer to the operating state. Thereafter, the above cycle is repeated, and data of a predetermined number of bytes is transferred from the memory of the personal computer to the peripheral device side.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a DMA transfer circuit according to the present invention will be described below in detail with reference to the drawings. In FIG. 1, 1 is DM
The write control signal (IOWC signal) of the A controller 33 is connected to the clock terminal 11 of the second flip-flop 3. 2 is a write terminal (IOW) of the register 18.
C), the write terminal (* WF) of the CPU 8 on the peripheral device side.
LG) 17 and a register 18
And outputs a signal requesting data writing. Reference numeral 3 denotes a second flip-flop, which connects the output terminal 4 to one input 6 of the first AND gate 5. 7 is the first AND
The other input of the gate 5, the DMA controller 33
To the output terminal 10 of the HLDREQ signal. 12
Is a clear terminal of the second flip-flop, and the CP
It is connected to the write terminal (* WFLG) 17 of U8.
Reference numeral 13 denotes a second AND gate, one input of which is connected to the input 7 of the first AND gate 5 and the output terminal 10 of the DMA controller 33 for the HLDREQ signal. 15 is one input terminal of an OR gate 26, which is connected to the output of the first AND gate 5, 26 is the OR gate, and the other input terminal 16 of this gate is the second A
Connected to output 25 of ND gate 13. Gate 2
The output 27 of 6 is connected to the HLDREQ signal terminal 30 of the CPU 40 of the personal computer 38 via the output terminal 28 of the peripheral device card and the input terminal 29 of the personal computer. 1
7 is a write terminal (* WFL) of the CPU 8 on the peripheral device side.
G), the clear terminal 12 of the second flip-flop 3
To control the operation of the second flip-flop 3. Reference numeral 18 denotes a register, which functions as a bus buffer, and relays data writing and reading between the personal computer and the CPU of the peripheral device. 19 is a first flip-flop,
The clock terminal 20 is connected to the DMA controller 33
The clear terminal 22 is connected to the output terminal 32 of the read signal (* RFLG) of the CPU 8 on the peripheral device side, and the clear terminal 22 is connected to the output terminal 31 of the read control signal (IORC).
This output terminal 32 is connected to the input terminal of the read control signal (IORC) of the register 18. The output terminal 22 of the first flip-flop is connected to the second AND gate 13
, And to the read flag terminal 23 (RFLG) of the CPU on the personal computer side. Both the data input terminal and the preset terminal are always fixed at “H” level.

Next, the operation timing of the DMA transfer circuit according to the present invention will be described with reference to signal waveforms in FIG. In the figure, in the case of a single transfer from the input / output device to the personal computer, the DMA controller outputs a data write control signal (IOWC) at the rising edge 29 of the signal waveform and a hold request signal (HLDREQ).
At the rising edge 26 of the signal waveform 22. At this time, since the clear terminal of the second flip-flop is at the “H” level, the second flip-flop has the second flip-flop as shown in the signal waveform 24.
The signal waveform at the output terminal Q (4) of the flip-flop is 27
Stand up at. As a result, the output of the AND gate connected to the output terminal 4 of the second flip-flop rises, the signal waveform 25 rises at the BUSREQ terminal of the CPU on the personal computer side, and the CPU surrenders the bus line. Next, when the CPU of the peripheral device finishes writing to the register (* WFLAG) and causes the signal waveform 23 to fall at 30, the clear terminal of the second flip-flop falls, and its output is cleared. 2
The output of the AND gate connected to the output terminal 4 of the flip-flop falls, which causes the BUSRE of the CPU to fall.
The Q terminal falls at 32, whereby the CPU of the personal computer occupies the bus line. Next, the hold request signal (HLDREQ) rises at 33, and the signal waveform at the BUSREQ terminal of the CPU on the personal computer rises at 34.
U surrenders the bus line and the next data is transferred. Thereafter, the above cycle is repeated every time data is written.

Next, the operation of single transfer of data from the personal computer to the peripheral device will be described. When the CPU of the personal computer wants to transfer data to the peripheral device, it outputs a write signal to the DMA controller. With this signal, the DMA controller causes the hold request signal (HL
DREQ) at 51 and the CPU on the peripheral device causes the read signal (* RFLG) 43 to fall at 52. As a result, the output waveform Q (22) 44 of the second flip-flop rises at 53, the output of the second AND gate connected to the output terminal of the second flip-flop rises, and the BUSRE of the CPU on the personal computer side rises.
The signal waveform 45 at the Q terminal rises at 54, whereby the CPU on the personal computer side surrenders the bus line. When the CPU of the peripheral device finishes reading from the register,
The DMA controller lowers the hold request signal (HLDREQ) at 55, thereby causing the second A
The output of the ND gate falls, whereby the BUSREQ terminal of the personal computer CPU falls at 57, and the personal computer CPU occupies the bus line. Thereafter, the above cycle is repeated every time data is read.

[0009]

As described above, according to the present invention, D
According to the MA transfer circuit, in the single transfer mode, the main CPU does not stop completely.
Even when there is an input / output device that performs high-speed processing, the processing of the main CPU can be completed in time, and the processing speed of the personal computer is improved.

[Brief description of the drawings]

FIG. 1 is a diagram of a DMA transfer circuit according to the present invention.

FIG. 2 is a waveform diagram of a DMA transfer circuit according to the present invention.

[Explanation of symbols]

 Reference Signs List 1 IOWC signal 2 terminal 3 second flip-flop 4 terminal 5 gate 6 input 7 input 8 CPU 9 terminal 10 output terminal 11 clock terminal 12 clear terminal 13 gate 14 input 15 input 16 input terminal 17 write terminal 18 register 19 first flip-flop Reference Signs List 20 clock terminal 21 clear terminal 22 data terminal 23 read flag terminal (RFLG) 24 input 25 output 26 OR gate 27 output 28 output terminal 29 input terminal 30 BUSREQ input terminal 31 IORC output terminal 32 * RFLG 33 DMA controller 34 peripheral device side Memory 35 Bus line 36 Memory 37 Bus line 38 PC side block 39 Bus line 40 CPU 41 Write signal terminal

Claims (1)

(57) [Claims] An apparatus for performing data transfer between a memory on a personal computer and a peripheral device.
A register provided between the data bus line of the PU and the data bus line of the CPU on the peripheral device side, and a write control signal of a DMA controller provided for the peripheral device are latched. C
A second flip-flop for controlling a write timing from a PU to the register, and an AND between the latched output and an HLDREQ signal output of the DMA controller
A first AND gate, a write single transfer circuit for controlling a bus request signal to the CPU of the personal computer by an output of the gate, and a read control signal of the DMA controller connected to a clock terminal of a first flip-flop. A first flip-flop for latching and controlling a read timing from the register to the peripheral device side CPU based on the latched output; and a latched output and an HLDREQ of the DMA controller.
A DMA transfer circuit comprising: a second AND gate for performing an AND operation with a signal output; and a read single transfer circuit for controlling a bus request signal to a CPU on a personal computer side by an output of the gate.