KR910008420B1 - Interface circuit between cpu and peripheral i/o devices - Google Patents

Abstract

The feature is compatibility to interface between CPU (2a) and peripherial I/O device (2b) having different timing sequence and bus and control signal characteristics. Interfacing scheme is implemented with shift register (2c), memory control signal generator (2d), buffer circuit (2e), 'NAND' gate (2j) and inverter (2k). (2c) decides bus enabling period and memory control signal generating point synchronizing with system clock of CPU. (2d) is associated with the shift register and flip-flop (2f) and provides control signal according to the characteristics of peripheral device (2a) when DMA operation. And the buffer transfers control and address signals to control DMA operating signal. So it can be used in interfacing CPU of DC adaptor and packet controller for PC networking.

Description

Interface circuit between central processing unit and peripheral I / O

1 is a general interface block diagram.

3 is a block diagram of the present invention.

3 is a timing diagram according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

1a: central processing unit 1b: peripheral I / O

1c: memory 2a: peripheral I / O

2b: CPU 2c: shift register

2d: memory control signal generating circuit 2e: buffer

2f: flip-flop 2g: memory

2h: AND gate 2i: OR gate

2j: NAND gate 2k: Inverter

BUSACK: Bus use permission signal BUSREQ: Bus use request signal

DRQ: Bus use request signal for DMA operation

DACK: Bus permission signal for DMA operation

0: clock

The present invention relates to an interface circuit between two devices for direct memory access (DMA) operation in the configuration of different CPUs and peripheral I / O devices.

Recently, there are many peripheral I / O devices with special functions. These devices have internal DMA control circuits to directly access memory and process data.

In general, the central processing unit and the DMA control unit are compatible with each other. In the peripheral input / output operation timing, bus, and control signal with the DMA, the central processing unit has different characteristics from the central processing unit. Therefore, when the central processing unit and the peripheral I / O devices are in contact with each other, they have no choice but to implement devices having the same characteristics.

An object of the present invention is to solve the above problems and to provide a connection between two devices having different operation timings, buses, and control signal characteristics.

The present invention provides a peripheral input / output device connected to a control and address signal for achieving the above object, a DMA control circuit, and a NAND gate and the NAND gate connected to a DRQ (lead and write) signal of the peripheral input / output device. An AND gate connected to a DACK signal of a peripheral input / output device, a central processing unit connected to an output, a control and an address signal of the AND gate to extract and execute a command, a BUSACK signal and a shift register of the central processing unit, The connected OR gate, the inverter connected to the BUSACK signal of the central processing unit, and the output of the inverter and the clock signal of the central processing unit are connected to determine a bus usage period and determine a time point for generating a memory control signal. A shift register circuit, a DRQ signal of the peripheral I / O device, and an output of the inverter. A flip-flop for distinguishing a DMA operation mode, a memory control signal generation circuit connected to an output of the shift register and the flip-flop to generate a memory control signal according to the characteristics of the peripheral input / output device during a DMA operation, the shift register and the memory It is connected to a control signal generating circuit and used to control the output of the DMA operation signal.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a block diagram of a conventional interface, which comprises a central processing unit 1a, a peripheral I / O device 1b and a memory 1c incorporating a DMA control circuit, and FIG. 2 is a block diagram of the present invention. , Peripheral I / O device 2a with built-in DMA control circuit, central processing unit 2b, shift register 2c, memory control signal generation circuit 2d, buffer circuit 2e, NAND gate 2j, inverter ( 2k).

In FIG. 1, the peripheral I / O device 1b requests a bus usage right to the central processing unit 1a when accessing the memory 1c for data processing and performing read / write operations. This bus use request signal DRQ signal is directly transmitted to the bus use request signal BUSREQ signal of the central processing unit 1a. After detecting this signal, the central processing unit 1a outputs a bus permission signal (BUSACK signal) and passes it directly to the bus permission signal (DACK signal) of the peripheral I / O device 1b. The memory 1c is accessed through a control signal and an address signal between the device 1a and the peripheral input / output device 1b.

In FIG. 2, when the peripheral input / output device 2a directly accesses the memory 2g for data processing without the intervention of the central processing unit 2b and performs a read / write operation, the central processing unit 2b Ask for a bus pass. The bus use request signal DRQ signal (FIG. 3) is connected to the bus use request signal (BUSREQ signal) (see FIG. 3) of the central processing unit 2b via the NAND gate 2j and the AND gate 2h. Delivered.

The central processing unit 2b outputs a bus use permission signal (BUSACK signal) (FIG. 3) after a predetermined time has elapsed after detecting this signal. When this response signal is output, the bus permission signal (DACK signal) (FIG. 3) is output to the peripheral I / O device 2a through the OR gate 2i. From this point on, the peripheral I / O device 2a has the bus right. The memory 2g is accessed.

From this signal output, the operation of the shift register 2c is started, and the bus is acquired for a specific time. This shift register 2c operates in synchronization with the system clock (FIG. 3) of the central processing unit 2b. This specific time adjusts the number of bits of the shift register 2c so that the peripheral input / output device 2a accesses the memory 2g to suit the time required for read / write.

The OR gate 2i serves to forcibly terminate the bus acquisition period of the peripheral input / output device 2a when the most significant bit of the shift register 2c is output. During the bus acquisition time, the memory control signal is generated from the memory control signal generation circuit 2d according to the type and characteristic of the memory.

In the memory read operation of the memory control signal generation circuit 2d, the shift register 2c is taken into account in consideration of the timing of the address output time of the peripheral I / O device 2a, the data output time of the memory 2g, and the data fetch time. Each bit output is used to generate signals necessary for memory control such as memory enable and read enable, and transfer them to the buffer 2e. During memory write operation, the memory address access time and the data output timing of the peripheral input / output device 2a are adjusted. In consideration of this, the bit output of the shift register 2c is used to generate a memory enable signal, a write enable signal, and a signal necessary for memory control and transfer the generated signal to the buffer 2e.

The buffer 2e is used to control the output of the DNA operation signal. The buffer 2e receives signals from the memory control signal generation circuit 2d and the shift register 2c and transfers control and address signals.

The flip-flop 2f receives the DRQ (lead) signal of the peripheral input / output device 2a as a set terminal and receives the inverter signal of the BUSACK signal of the central processing unit 2b as a reset terminal to distinguish the read / write operation mode of the DMA. In order to perform the toggle function, the read / write signal can be selected by the memory control signal generation circuit 2d.

The present invention is configured as described above can be applied when the network connection peripheral device (dedicated IC) to the CPU for the network connection in the information communication field, as an embodiment, the central processing unit of the PC adapter hardware in the PC communication network configuration It can be applied to interface of packet controller.

Claims (4)

A peripheral I / O device 2a connected to a control and address signal and having a built-in direct memory access (DMA) control signal, and a NAND gate 2j connected to a DRQ (lead / write) signal of the main input / output device 2a. ), An AND gate 2h connected to the DACK signal of the NAND gate 2j and the peripheral I / O device 2a, and an output and control and address signal of the AND gate 2h to extract an instruction. A central processing unit 2b for execution, an OR gate 2i connected to the BUSACK signal and the shift register 2c of the central processing unit 2b, and a BUSACK signal of the central processing unit 2b. A shift register circuit 2c connected to the inverter 2k and the output of the inverter 2k and the clock signal of the central processing unit 2b to determine the bus usage period and to determine a time point at which a memory control signal is generated. ) And the DRQ (lead) of the peripheral I / O device 2a A flip-flop 2f connected to an output of a call and an inverter 2k to distinguish a DMA operation mode, and a peripheral input / output device 2a connected to an output of the shift register 2c and a flip-flop 2f during a DMA operation. A memory control signal generation circuit 2d for generating a memory control signal in accordance with the characteristics of the circuit; and the shift register 2c and the memory control signal generation circuit 2d for controlling the output of the DMA operation signal. An interface circuit comprising a buffer circuit 2e for transferring control and address signals. The interface circuit according to claim 1, further comprising a memory (2g) coupled to said control and address signal. The interface circuit according to claim 1, wherein said memory control signal generating circuit (2d) enables the output of a memory control signal for starting a DMA operation by using the first output of said shift register (2c). 2. Interface circuit according to claim 1, characterized in that the flip-flop (2f) is toggled and operated in accordance with the DMA read / write mode of the peripheral input / output device (2a).

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