JPH0519918A - Io bus control system - Google Patents

Abstract

PURPOSE:To improve the processing speed of the system and to improve the versatility of the system. CONSTITUTION:This system is equipped with selecting means 7 and 17 to select an input/output equipment for performing access to an IO bus 23 among plural input/output equipments to perform access to the IO bus 23 according to address information transmitted through a system bus 3 and access time setting registers 11a-11n to latch the access time of the input/output equipment selected by these selecting means 7 and 17 for performing access to the IO bus 23. Further, this is equipped with access time counters 13a-13n to execute counting-up until the latched access time, OR circuit 15 to turn the access value to a true value at the access time, and control means 17 to start the access from the input/ output equipment selected by the selecting means 7 and 17 to the IO bus 23 and to stop the access from the relevant selected input/output equipment to the IO bus 23 after the OR circuit 15 is turned to the true value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a system bus and an IO.
Of the IO bus control systems including a bus and a plurality of input / output devices that access the IO bus, each of the plurality of input / output devices can be connected to the IO bus without decreasing the processing speed of the system. The present invention relates to an IO bus control system that determines an access time to access.

[0002]

2. Description of the Related Art Generally, in a computer system, a device having a DMA function such as a main memory is connected to a system bus capable of high-speed transfer, and serial IO and IO such as ROM are connected to a low-speed IO bus via an IO controller. It is connected. Since the above-mentioned many IOs have different access times, there are the following methods for controlling the system bus and the IO bus.

The first method is a method of matching the access time of the slowest IO among the IOs used in the system.

The second method is provided with a control unit in which each IO connected to the IO bus determines an access time.
This is a method of accessing the IO bus.

The third method is to start access.
A request signal is output from the IO controller to the IO, and when the access is completed, the handshake of returning a response signal from the IO to the IO controller is used. In each of the above methods, there is a possibility that a problem such as a delay in the processing speed of the system may occur.

[0006]

However, the first method of the conventional IO bus control systems matches the access time of the slowest IO among the IOs, which causes a decrease in the processing speed of the entire system. There was a problem to do.

In the second method, when the IO elements are the same and the access times are different, for example, when the elements having 100 nsec are used, the elements having the access time of, for example, 70 nsec cannot be used, which hinders improvement of system versatility. was there.

In the third method, the processing speed of the system is reduced by the time required for the request or response between the IO controller and the IO, and each IO requires a handshake logic. There was a problem that caused complication.

The present invention has been made in order to solve such a conventional problem, and an object thereof is to improve the processing speed of the system and the versatility of the system, and to improve the versatility of each IO mechanism. By preventing complication,
It is intended to improve the system performance and to provide an IO bus control system with excellent quality.

[0010]

To achieve the above object, the present invention accesses the IO bus among a plurality of input / output devices that access the IO bus according to address information transmitted via a system bus. Selection means for selecting an input / output device, a register for latching an access time for accessing the IO bus of the input / output device selected by the selection means, and an access time latched by the register and then latched by the register A counter that counts up to, a logical sum circuit that takes the logical sum of this counter and makes it a true value when the count value of the counter reaches the access time, and the input / output selected by the selecting means after being latched in the register I by device
And a control unit for starting access to the O bus and stopping access to the IO bus by the selected input / output device after the OR circuit becomes a true value.

[0011]

With the above arrangement, the input / output device accessing the IO bus is selected from among the plurality of input / output devices accessing the IO bus according to the address information transmitted via the system bus. The access time for accessing the IO bus by the selected input / output device is latched in the register. After being latched in the register, the counter counts up to the access time latched in the register. When the logical sum of this counter is calculated and the count value of the counter reaches the access time, the logical sum circuit becomes the true value. Since the IO bus access by the selected input / output device is started after being latched in the register, and the IO bus access by the selected input / output device is stopped after the OR circuit becomes the true value. ,
The processing speed of the system can be improved and the versatility of the system can be improved.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the control of an embodiment according to the IO bus control system of the present invention.

In the figure, a CPU 1 for controlling the entire IO bus control system of the present invention is connected to a system bus 3 capable of high-speed transfer and outputs various data and the like. The memory 3 stores programs, data and the like related to the operation of the CPU 1 at a predetermined address.

The address decoder 7 has an address information input from the CPU 1 via the system bus 3 for an I / O bus, which will be described later, or an access time setting register 11a.
It is determined whether it is for 11n. The address decoder 7 is
Sel1 of the IO sequencer 17, which will be described later, via the signal line S _1.
When the address information is for the I / O bus, the signal line S _{1 is set} to a true value by connecting to the terminal. Also, the address decoder 7
Is connected to the sel0 terminal of the IO sequencer 17 via the signal line S _2, and sets the signal line S ₂ to the true value when the address information is for the access time setting registers 11a to 11n.

Access time setting registers 11a-11
n is provided corresponding to IO.0 to IO.N to be described later, and the access time setting register 11a is IO.0.
Access time of the access time setting register 11
n latches the access times of IO and N respectively. The access time setting registers 11a-1
1n is the load0 terminal to lo of the IO sequencer 17, which will be described later.
The access time setting register 11 is connected by the address decoder 7 to the adn terminal via the signal lines lo to ln.
If it is determined to be for a to 11n, the load terminal becomes a true value and the data transmitted from the system bus 3 is latched.

Access time counters 13a to 13n
Correspond to the access time setting registers 11a to 11n on a one-to-one basis, and load of the IO sequencer 17, which will be described later.
0 to loadn terminals are connected via signal lines e0 to en. The access counters 13a to 13n load / en the IO sequencer 17 when the address information is for the IO bus.
At the same time when the terminal becomes a true value, counting up is started and the count value becomes the access time setting registers 11a to 1
Carry occurs when the value stored in 1n is reached. The address time setting registers 11a to 11n
The value stored in is, for example, 4-bit “1111” and is a value that determines the access time of IO.0 to IO.N described later, and is determined by the system specifications and the like.

The input terminal of the OR circuit 15 is connected to the access time counters 13a to 13n, and the output terminal is IO.
It is connected to the ready terminal of the sequencer 17. The logical sum circuit 15 takes the logical sum of the access counters 13a to 13n connected to the input terminals and becomes a true value when a carry occurs in the access counters 13a to 13n, and the ready terminal of the IO sequencer 17 becomes a true value. Become.

Chip select terminal cos of IO sequencer 17
.About.csn are connected to IO.0 to IO.N, respectively, and the read terminal (IOR) or write terminal (IOW) of the IO bus 23 is connected to IO.0 to IO.N, respectively. Further, the IO sequencer 17 is connected to the address bus 19 and the data bus 21 of the IO bus 23.

In the IO sequencer 17, the signal line S ₁ is set to a true value by the address decoder 7, and at the same time, the lower bits of the address information transmitted to the adr terminal via the signal line a are selected from the chip selection terminals cso to csn. Select. IO depending on the IO connected to the selected chip select terminal
The bus 23 is accessed. Further, the IO sequencer 17 sets the IOR terminal indicating the data read operation or the IOW terminal for writing the data to the true value.

IO • 0 to IO • N are connected to the IO bus 23, the sel1 terminal of the IO sequencer 17 becomes a true value, and reading or writing of data is started in the next cycle.
When the ready terminal of the sequencer 17 becomes the true value, the cso to csn terminals are set to the true value in the next cycle, thereby ending the access to the IO bus 23.

Next, the operation of this embodiment will be described with reference to the time chart of FIG. Note that FIG. 2 has negative logic.

First, the case where the access time is set in the access time setting registers 11a to 11n after the system is activated will be described.

The CPU 1 transmits address information and data to the system interface 9 via the system bus 3. When the address information is output to the address decoder 7 via the system bus interface 9, the address decoder 7 outputs the signal line S when the address of the address information indicates the access time setting registers 11a to 11n.
Make ₂ a true value. When the signal line S ₂ has a true value, the IO sequencer 17 sets the latch signal line 10 to a true value and the above data is latched in the access time setting register 11a.

Next, the above access time setting register 1
The operation of accessing the IO bus 23 by the data latched in 1a will be described.

When address information is input from the CPU 1 via the system bus interface 9, the address decoder 7 sets the signal line S ₁ to a true value when the address of the address information indicates that the address is for the IO bus 23, and the IO sequencer at T _1. The sel1 terminal of 17 becomes negative logic. If the sel1 pin becomes negative logic, the IO sequencer 17 will make the chip select pin cs at T _2.
Set o to negative logic and load / en0 pin to negative logic. When the chip select terminal cso becomes negative logic, the IO sequencer 17 sets the IOW for writing data at T ₃ to negative logic and starts writing the data of the IO bus 23 by IO · 0.

The data latched in the access time setting register 11a is copied to the access time counter 13a by the negative logic of the load / en0 terminal. When the data is copied, the access time counter 13a starts counting up and the count value is the copied value,
For example, it occurs when "1111" is reached. OR circuit 1
5 becomes a true value due to the occurrence of a carry of the access time counter 13a, and the IO sequencer 1 operates between T ₄ and T _s.
The ready terminal of 7 becomes negative logic. When the ready terminal becomes negative logic, the IO sequencer 17 ends the transfer of the IO bus 23 by setting the IOW terminal to a false value at T _{6 and the} cs terminal to a false value at T _{7 of} the next cycle.

[0028] Thus, by setting the access time of the IO · 0 to T ₃ through T _6, enables IO data transfer, the access time becomes possible settings for each IO, universal system You can improve the property.

In the present embodiment, the write operation of IO · 0 has been described, but the read operation (IOR) and the operation of other IO are similar.

Further, in this embodiment, by changing the count values of the access time counters 13a to 13n, I
The O can be freely selected, and the complexity of the system mechanism can be prevented.

[0031]

As described above, according to the present invention, the IO
The IO bus is accessed by the IO during the access time by providing a counter that counts the access time of the system. Therefore, the processing speed of the system is improved, the versatility of the system is improved, and the mechanism of the input / output device is improved. By preventing complication, system performance can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing control of an embodiment according to an IO bus control system of the present invention.

FIG. 2 is a time chart showing the operation of the present invention.

[Explanation of symbols]

 1 CPU 3 System Bus 7 Address Decoder 11a to 11n Access Time Setting Register 13a, 13n Access Time Counter 15 OR Circuit 17 IO Sequencer 23 IO Bus

Claims (1)

What is claimed is: 1. An IO comprising a system bus, an IO bus, and a plurality of input / output devices for accessing the IO bus.
In the bus control system, selecting means for selecting an input / output device that accesses the IO bus among the plurality of input / output devices based on address information transmitted via the system bus, and input device selected by the selecting means. A register that latches the access time to access the IO bus of the output device, a counter that counts up to the access time that is latched in this register and then latched in that register, and the OR of this counter A logical sum circuit for setting a value to a true value when the access time is reached, and a logical sum circuit for starting the access of the IO bus by the input / output device selected by the selecting means after being latched in the register so that the logical sum circuit outputs a true value. After that, the access to the IO bus by the selected input / output device is stopped. IO bus control system comprising: the control means, the that.