JPH04323755A - Dma device - Google Patents

Abstract

PURPOSE:To assure the transfer of data within a decided time and at the same time to optionally set the time by providing a DMA monitoring timer to monitor the DMA transfer. CONSTITUTION:A microprocessor 1 is provided together with the memory devices 5 and 4, a DMA controller 2 which perform the transfer of data between both devices 3 and 4 via a data bus 6 in the timing when both an address bus 5 and the bus 6 are not used by the microprocessor 1, and a monitoring timer 7 which monitors the DMA transfer. In such a constitution, it is possible to always transfer the data within a decided time by setting the value of the timer 7 and then giving a request to the microprocessor 1 to set the buses free if these buses are not kept free for a decided time or longer.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA transfer device which is a hardware data transfer device between memories in a device including a microprocessor and a plurality of memory devices.

0002

2. Description of the Related Art FIG. 3 shows a conventional DMA device. In Figure 3, 1 is a microprocessor and 2 is a D
MA controller, 3 is a memory device A, 4 is a memory device B, 5 is an address bus, and 6 is a data bus.

The operation of the conventional DMA device configured as described above will be explained below.

Transferring data from memory device A to memory device B
Consider the case of MA transfer. As an initial setting, the source address of memory device A, which is source data, and the destination address of memory device B, which is the receiving side, are specified. Next, a DMA request signal (hereinafter referred to as DMAREQ) is input to the DMA controller. The microprocessor outputs BUSFREE, which is a signal indicating that the bus is free, at a timing when the microprocessor does not use either the address bus 5 or the data bus 6. 1st BUSFREE after DMAREQ is input
During the signal period, data in memory device A 3 is transferred to DMA controller 2 using data bus 6 . Next, during the second BUSFREE signal period, the DMA
The data transferred to the controller 2 is transferred to the memory device B 4 using the data bus 6. That is, in 2 cycles of BUSFREE, data 3 in memory device A can be directly transferred to 4 in memory device B without going through the microprocessor. At this time, the first cycle (transfer cycle from memory device A, 3, to the DMA controller) is called a read cycle, and the second cycle (transfer cycle, from the DMA controller to memory device B, 4) is called a write cycle. I'll call you. FIG. 4 shows a timing chart of a conventional DMA device. In FIG. 4, μP is an abbreviation for microprocessor.

[0005]

[Problems to be Solved by the Invention] However, in the above conventional configuration, the BUSFRE from the microprocessor
Since the method only unilaterally waits for the E signal, there is a problem in that it cannot be guaranteed that data will be transferred within a predetermined time.

The present invention solves the above-mentioned conventional problems, and aims to provide a DMA device that can guarantee that data is transferred within a predetermined time.

[0007]

Means for Solving the Problems To achieve this object, the DMA device of the present invention includes a microprocessor, a plurality of memory devices, and a DMA device that connects the memories at a timing when the microprocessor does not use an address bus and a data bus. DMA for performing data transfer using the data bus
It consists of a controller and a monitoring timer that monitors DMA transfer.

[0008]

[Operation] By setting the value of the DMA monitoring timer, if the bus is not free for a predetermined period of time, the microprocessor is requested to free the bus within a predetermined period of time. It can be guaranteed that data will always be transferred.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows D in one embodiment of the present invention.
FIG. 2 is a block diagram of the MA device and its operation waveform diagram.

In FIG. 1, 1 is a microprocessor;
2 is a DMA controller, 3 is a memory device A, 4 is a memory device B, 5 is an address bus, 6 is a data bus, 7 is a D
MA monitoring timer 8 is an AND gate.

The operation of the DMA device configured as described above will be explained below. First, the source address of memory device A and the destination address of memory device B are initialized for the DMA monitoring timer. D.M.A.
REQ is input to the DMA controller 2. A signal DMABUSY indicating that DMA transfer is in progress is input to AND gate 8. The AND gate 8 allows input of the microprocessor's system clock to the DMA monitoring timer 7 using the DMABUSY signal. At the timing when the microprocessor is using the address bus or data bus, BUSFREE is at "L" level and the DMA monitoring timer is not reset. Therefore, the DMA monitoring timer starts counting the system clock. The subsequent operations are divided into the following three types depending on the timing of the output BUSREQ of the DMA monitoring timer. (1) BUSFRE before BUSREQ is output
E was output twice. (2) BU after read cycle and before write cycle
SREQ was output. (3) BUSREQ was output before the read cycle.

In case (1), there are two BUSFREEs before the DMA monitoring timer outputs an output, so both the read cycle and write cycle are completed as in the conventional example.
Data in memory device A is transferred to memory device B.

In case (2), up to the read cycle, D
The MA monitoring timer is executed without outputting any output, but the DMA monitoring timer outputs an output before the write cycle is executed. The BUSREQ signal is input to the microprocessor. When this signal is input, the microprocessor outputs the BUSFREE signal only once. Upon receiving this BUSFREE signal, the DMA controller:
Execute a DMA write cycle. Therefore, memory device A
data is transferred to memory device B.

In case (3), as shown in FIG. 2, before the read cycle (first BUSFREE), the DMA
A BUSREQ signal is output from the monitoring timer. B.U.
The SREQ signal is input to the microprocessor and the BUS
The FREE signal is output twice consecutively. The first cycle is a read cycle, and the second cycle is a write cycle. Therefore, data in memory device A is transferred to memory device B.

As described above, according to this embodiment, the DMA
By providing a monitoring timer, it is possible to ensure that data is transferred within a predetermined time.

[0016]

[Effects of the Invention] By providing a DMA monitoring timer, the present invention can ensure that data is transferred within a predetermined time.Furthermore, by using a timer, the predetermined time can be freely set. This makes it possible to realize a DMA device.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a DMA device in an embodiment of the present invention.

[Figure 2] Timing chart during operation of the device

[Figure 3]
Block diagram of conventional DMA device

[Figure 4] Timing chart during operation of the device

[Explanation of symbols]

1. Microprocessor 2 DMA controller 3 Memory device A 4 Memory device B 5 Address bus 6 Data bus 7 DMA monitoring timer 8 And gate

Claims (1)

[Claims] 1. A microprocessor, a plurality of memory devices, a DMA controller that performs data transfer between the memories using the data bus at a timing when the microprocessor does not use an address bus and a data bus, and a DMA controller that performs data transfer between the memories using the data bus. A DMA device characterized by comprising a monitoring timer for monitoring.