JPH0142017B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a multiprocessor contention control method in which a plurality of processors use one shared bus to access devices connected to the shared bus. In particular, the present invention relates to a multiprocessor contention control method that allows a high-priority processor to acquire the bus even after a low-priority processor has approved the bus acquisition until a device accesses it.

If one processor does not have enough processing power, a multiprocessor configuration using multiple processors is used.

In such a multiprocessor configuration,
Since a plurality of processors are connected to one shared bus, it is necessary to determine which processor will use the shared bus and perform competition control.

[Conventional technology]

FIG. 4 is a block diagram for explaining the contention control of a conventional multiprocessor.
The processors 1 and 2 and the memory control section 7 are connected to the memory 8 via drivers 3 and 4, respectively, and a competition control section 5 is provided for determining whether the processors 1 and 2 can acquire the bus. The drivers 3 and 4 include address gates and data gates for connecting the processors 1 and 2 to the shared bus 6, and are controlled by the address gate control signals (bus acquisition approval signals) GATA and GATB of the contention control unit 5. Address gates 3 and 4 open, processors 1 and 2 send address and control signals to the shared bus 6, and the memory 8
configured to be accessible. The data gates of the drivers 3 and 4 are opened by a data gate control signal (not shown) synchronized with an address gate control signal from the competition control section 5.

FIG. 5 is a detailed block diagram of the contention control section 5 having the structure shown in FIG. AND gate 52 and flip-flop 5 for generating gate signal GATB
It is composed of 3.

Conventional multiprocessor contention control will be explained with reference to FIG.

The processors 1 and 2 request the contention control unit 5 to acquire the bus in order to use the shared bus 6.
Issue REQA, REQB. The contention control unit 5 approves bus acquisition to the processor to which the request has been issued at the time of conflict determination, and if requests have been issued from both processors at the time of conflict determination, it authorizes the processor with a higher priority to acquire the bus. For example, in the example shown in FIG. 5, processor 1 is set to have a high priority and processor 2 is set to a low priority, and the AND gate 50 for processor 1 responds to processor 1's bus acquisition request.
REQA is used when processor 2's bus acquisition request REQB is not issued, that is, it is the inversion of REQB *
When REQB is "1" and bus acquisition approval GATB for processor 2 is not issued, an output is generated, and flip-flop 51 is set to issue bus acquisition approval GATA for processor 1. and gate 5
2 outputs the processor 2's bus acquisition request REQB when the processor 1's bus acquisition approval GATA is not issued, and sets the flip-flop 53 to issue the processor 2's bus acquisition approval. In the example shown in FIG. 6, only the bus acquisition request REQA of processor 1 is issued at time t ₁ of conflict determination, so processor 1 is approved to acquire the bus, and the bus acquisition approval signal GATA is sent to driver 3.
and opens the address gate of driver 3.
As a result, the address and control signals are given to the shared bus 6 from the processor 1, and after receiving the bus acquisition approval signal GATA, the memory control unit 7 transfers the address and control signals to the shared bus 6.
Wait one clock until the address etc. are confirmed above,
*RAS (load address strobe) in memory 8
Outputs a signal to give the row address of memory 8 and *CAS (column address strobe)
It outputs a signal to give the column address of the memory 8. This causes the specified row of memory 8,
Column address locations are accessed to read and write data.

Then, a response signal indicating the end of the memory cycle is issued from the memory control section 7, and both flip-flops 51 and 53 of the contention control section 5 are reset.
The bus acquisition approval signal GATA falls, the gate of driver 3 is closed, and the next competition determination begins.

[Problem that the invention seeks to solve]

In such conventional contention control, as shown in Figure 6, after the contention determination is made at time _t2 , a bus acquisition approval signal is generated at time _t3 , the gate of the driver is opened, and the address is placed on the bus. After confirmation, start accessing devices such as memory with _t4 (*RAS, *
CAS). Therefore, even if a bus acquisition request REQB is issued from processor 2 with a higher priority between times t ₃ and t ₄ after conflict determination, 1 (memory)
You will have to wait for a cycle. In other words, even though memory access has not actually started, if a request is not issued at the time of conflict determination, even a processor with a high priority will not be able to obtain bus acquisition approval preferentially, and this There was a problem with forcing the processor into a wait state.

[Means for solving problems]

The present invention provides a multiprocessor contention system that allows a high-priority processor to acquire the bus even after a low-priority processor has opened a driver gate and granted bus acquisition, but before starting access to the device. To provide a control method.

Therefore, the present invention provides a shared bus, a plurality of processors each connected to the shared bus via a driver, and a provisional acquisition signal for the shared bus upon receiving a bus acquisition request from the plurality of processors and determining a conflict. and a second contention control unit that receives a contention determination output of the first contention control unit and a provisional acquisition signal and issues an access activation signal. , after a provisional acquisition signal is generated from the first contention control unit to a processor with a lower priority, the first contention control unit generates a provisional acquisition signal in response to the provisional acquisition signal on the condition that no bus acquisition request is issued from a processor with a higher priority. It is characterized in that the contention control unit No. 2 issues the access activation signal.

[Effect]

In the present invention, the contention control unit is divided into a first contention control unit and a second contention control unit, and the first contention control unit performs contention determination and outputs a provisional approval signal for opening the driver gate, The second contention control section generates an access activation signal to the device based on the contention judgment output and the provisional approval signal, and after the provisional approval signal is generated for the low priority processor, the contention judgment output is sent to the high priority processor. If the change occurs before the access activation signal is generated, an access activation (bus acquisition approval) signal based on this provisional approval signal is not issued, but on the contrary, bus acquisition approval is given to the processor with a higher priority.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a detailed circuit diagram of the competition control section configured in FIG. 1.
In the figure, the same parts as those shown in FIG.
REQB and access activation signal ACKA, which will be described later.
Upon receiving ACKB, it performs conflict judgment according to the determined priority order, and outputs conflict judgment outputs RA and RB and bus acquisition provisional approval signals GATA and GATB that open the driver gate accordingly.
As shown in FIG. 2A, in response to the bus acquisition request REQA from processor 1, processor 2, which has a higher priority,
There is no bus acquisition request REQB (*REQB="1")
When the access activation signal ACKB of the processor 2 is not issued (*ACKB="1"), the AND gate 50a generates the contention determination output RA of the processor 1, and in response to the bus acquisition request REQB of the processor 2, Access activation signal ACKA
AND gate 51a that issues the conflict judgment output RB of the processor 2 when the is not issued (*ACKA="1"), and the conflict judgment output RA of the processor 1.
Processor 1's provisional approval signal is set by
Emit GATA and conflict judgment output RB of processor 2
and a flip-flop 52a which is reset by the processor 2 and generates a provisional approval signal GATB for the processor 2. 5b is a second conflict control section, which outputs the conflict determination output RA of the first conflict control section 5a;
The access activation signals ACKA and ACKB are generated by RB and the provisional approval signals GATA and GATB, and the memory control unit 7 is activated, and as shown in FIG. The AND gate 50b which takes an AND with the signal GATA and the output of the AND gate 50 are set to issue an access activation signal (bus acquisition approval signal for the processor 1) ACKA, and by the response signal from the memory controller 7. The flip-flop 52b is reset and drops the access activation signal ACKA, and the contention judgment output is sent to the processor 2.
AND gate 51b which ANDs RB and provisional acknowledgment signal GATB, and is set by the output of AND gate 51b to issue an access activation signal (bus acquisition acknowledgment signal for processor 2) ACKB;
The flip-flop 53b is reset by a response signal from the memory control section 7 and drops the access activation signal ACKB.

Next, the operation of the embodiment configuration shown in FIGS. 1 and 2 will be explained using the time chart shown in FIG. 3.

When processors 1 and 2 need to acquire a bus, they issue bus acquisition requests REQA and REQB to the first contention control unit 5a.

For example, at time _T1 in FIG. 6, when a bus acquisition request REQB is issued only from the processor 2, the first competition control unit 5a
A conflict determination output RB is generated from the flip-flop 1a, and a provisional approval signal GATB is generated from the flip-flop 52a.

This provisional approval signal GATB allows driver 4 to
The address and control signals for access are sent from the processor 2 to the shared bus 6.

This conflict judgment output RB and provisional approval signal GATB
is input to the second contention control section 5b, sets the flip-flop 53b via the AND gate 51b, and issues the access activation signal ACKB.
As a result, processor 2's bus acquisition request is
REQB is granted, processor 2 drops the bus acquisition request REQB, and therefore the contention determination output RB also drops.

The memory control unit 7 receives this access activation signal.
Upon receiving ACKB, it immediately decodes the address on bus 6 and starts memory 8*
By giving the RAS signal to the memory 8, the row address of the memory 8 is given to the memory 8. Furthermore, the memory control unit 7 provides a column address of the memory 8 by providing a *CAS signal to the memory 8. As a result, the memory 8 is accessed, the read data is output onto the bus 6 while being read, and furthermore, the memory control section 7 issues a response signal indicating the end of one memory access.

This response signal causes the second competition control section 5b to
The flip-flop 53b is reset and the access activation signal ACKB falls.

On the other hand, when processor 1 issues a bus acquisition request REQA after determining the step conflict,
At time t ₂ after the release of the access activation signal ACKB,
On the condition that the bus acquisition request REQB of the processor 2 is not issued, the AND gate 50a of the first contention control section 5a issues a contention determination output RA, and the flip-flop 52a is set at the next clock (time _t3 ). , the temporary approval signal GATB is turned off and the temporary approval signal GATA is generated. This opens the gate of the driver 3, allowing the processor 1 to send addresses and the like to the shared bus 6.

In this state, a bus acquisition request is made from processor 2.
If REQB is not issued, step...
Similarly, memory access by processor 1 is executed.

However, as shown in FIG. 3, if the bus acquisition request REQB is generated from the processor 2 before the access activation signal ACKA to the processor 1 is issued, the AND gate 50a is closed in the first contention control section 5a and the contention determination output RA is output. Instead, the AND gate 51a opens and outputs a conflict determination.
RB is generated, and at time _t4 , the flip-flop 52a is inverted, the temporary approval signal GATA is turned off, and the temporary approval signal GATB is turned on.

As a result, the provisionally approved access by processor 1 is suspended, and conversely, access by processor 2 is executed in the same manner as in step .

In this way, even if provisional approval is given to a lower priority processor and the driver gate is opened, if there is a bus acquisition request from a higher priority processor before the access activation signal is generated, the bus acquisition approval will be granted to the processor with a higher priority. are given priority for use.

On the other hand, processor 1's bus acquisition request REQA
Since the access activation signal ACKB has not been issued for this, it continues without dropping, and at time _t5 after the access activation signal ACKB is released, the processor 2 requests to acquire the bus.
It will be accepted and access will be granted on the condition that no REQB has been issued.

In this way, one of the provisional approval signals GATA and GATB is always output from the first competition control unit 5a, and continues to be output even after one cycle is completed until the bus acquisition approval is transferred from one processor to the other processor. be done. By utilizing this fact, the continuous access time of the processor can be shortened.

That is, when the processor 1 issues the bus acquisition request REQA again at time _t8 after the cycle of the processor 1 ends in step, the first contention control unit 5
The flip-flop 52a of a is a temporary approval signal.
Continue to output GATA and AND gate 50
A conflict determination output RA is issued from a.

As a result, on condition that the contention judgment output RA does not fall, that is, the bus acquisition request REQB of processor 2 is not issued, the access activation signal is
ACKA is issued, bus acquisition approval is given as with STEP, and access is permitted.

Therefore, since the gate of driver 3 is open at the time of conflict determination during continuous access, access activation can be executed in one clock from the time of conflict determination without requiring the time required to determine the address due to the time required to open and close the gate. The cycle can be shortened by one clock. The same applies to continuous access by processor 2.

In the above embodiment, memory access was explained as an example, but the same applies to the case of access of other devices, and although the case of two processors was explained, there may be three or more processors. .

Although the present invention has been described above using one embodiment, the present invention can be modified in various ways according to the gist of the present invention, and these are not excluded from the present invention.

〔Effect of the invention〕

As described above, according to the present invention, a shared bus, a plurality of processors each connected to the shared bus via a driver, and a bus acquisition request from the plurality of processors are received, a conflict is determined, and the shared bus is a first contention control unit that issues a bus temporary acquisition signal and opens the gate of the driver; and a second contention control unit that receives the contention determination output of the first contention control unit and the temporary acquisition signal and issues an access activation signal. after the provisional acquisition signal is generated from the first contention control unit to the processor with a lower priority, the provisional acquisition signal is transmitted to the processor on the condition that no bus acquisition request is issued from the processor with a higher priority. The second contention control unit is characterized in that the second contention control unit issues the access activation signal in response to the request, so that a bus acquisition request from a high priority processor is granted bus acquisition approval to a low priority processor and accesses the device. This has the effect of reducing the waiting time of the high-priority processor, increasing the processing efficiency of the high-priority processor, and improving the performance of the entire system. In addition, the configuration is simple and can be realized with less additional hardware, making it useful in practice.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a detailed circuit diagram of the contention control section configured in FIG. 1, FIG. 3 is an explanatory diagram of the operation of the configuration in FIG. FIG. 5 is a detailed circuit diagram of the configuration shown in FIG. 4, and FIG. 6 is an explanatory diagram of the conventional operation. In the figure, 1, 2...processor, 3, 4...driver, 5a...first competition control section, 5b...second
6...shared bus, 7...memory control unit, 8...memory.

Claims (1)

[Claims] 1 A shared bus, a plurality of processors each connected to the shared bus via a driver, and a bus acquisition request from the plurality of processors, a conflict determination, a provisional acquisition signal for the shared bus, and a provisional acquisition signal for the shared bus. a first contention control unit that opens a gate; and a second contention control unit that receives a contention determination output of the first contention control unit and a provisional acquisition signal and issues an access activation signal;
After a provisional acquisition signal is generated from the first contention control unit to a processor with a low priority, the second contention control unit generates a provisional acquisition signal in response to the provisional acquisition signal on the condition that no bus acquisition request is issued from a processor with a high priority. 1. A contention control method for a multiprocessor, characterized in that a contention control unit of the processor issues the access activation signal.