JPS599744A - High speed dma (direct memory access) transfer starting circuit - Google Patents

Abstract

PURPOSE:To shorten a DMA transfer starting and operating time, by providing a preset memory in which a transfer starting register data is written, and operating each register by only a DMA start data, in a DMA transfer starting circuit. CONSTITUTION:Several kinds of DMA transfer start data are written in advance in a preset memory 24, and when a computer outputs only a DMA start data, a pair of data, a DA data, a DC data and other data which are written already in the preset memory are read out successively by a data of an SUB F/F 17 in said DMA start data and a data of an address counter 23, and are set to a corresponding register, a DA register 14, a DC register 15 and other register 16. In this way, a preset operation of a pair of DMA transfer start registers is executed without exchanging communication with the computer, therefore, the time required becomes <=1/10 comparing with that of a conventional method, and the operation can be executed at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention utilizes DMA (Direct Memory Acc), which is one of the known computer input/output control methods.
The present invention relates to a high-speed DMA transfer activation circuit that can shorten the program operation time at the time of transfer activation of the eg8) method.

FIG. 1 is a side view of a computer system configuration showing the relationship between an external device and a computer main body (hereinafter referred to as a computer) in which the present invention is implemented. In the figure, 1 is a computer, 2 is its input/output section, 6 is an external device connected to the input/output section 2, and 4 to 1
0 belongs to the external device, 4 is the device controller, and 5 to 7 are its components, of which 5 is the D
MA transfer circuit, 6 is a high-speed DMA transfer activation circuit, 7 is a data highway input/output section, 8 is a data highway, 9 (
9-1 to 9-n) are data highway input/output units, 1o(
io-i to 1O-n) are devices such as external or peripheral (input/output) devices such as magnetic disks, and devices such as monitors (Ml, monitors, etc.) that are connected to a data highway that can extend several kilometers.

Now, in order for the computer to start DMA transfer to the external device 6, it first runs a program. As a result, if data is set in the DMA start register in the DMA transfer circuit 5, the software transfers the data at high speed. (a system that repeats the process of importing data, a program analyzing data, and outputting control data to an external device), etc.
Since there is a restriction that data transfer must be performed within a certain processing time, it is an important issue to shorten the program operation time when starting DMA transfer. An object of the present invention is to provide a circuit that can shorten the program operation time and increase the speed of data transmission. The present invention will be explained in detail below.

Conventionally, when starting DMA transfer, external device 11
1111 When data is set in the address register that outputs the memory address signal of the computer and the word counter for the number of transferred words, and the DMA start data is written to the first device, the hardware operates and executes the data transfer. . In the case of FIG. 1, there are n data highway input/output sections 9 and n external devices 10, so in this case, the computer reads data from the device 10-1, and then reads the data from the devices 10-2 and 10-. 5,...1
Data is collected one after another from 0 to n, and a computer program analyzes these data and outputs the results to each device. Therefore, the program operation time T when starting the DMA transfer
As shown in FIG. 4A, there is a time period for sequentially transmitting data to address registers, word counters, and other registers, and DMA start data, with computer program operation times Ta, Tb, To, and Td in between. If the number of transferred words is small and the DMA transfer time TD is short, T1 may be longer than this, so it is desirable to make the program operation time T1 as short as possible.

The present invention reduces the data transfer time between the computer 1 and the device connected to the data highway 8 in FIG.
As shown in Figure A, compared to the conventional case, that is, the program operation time Tb, To, and TeL are omitted and significantly shortened, making it possible to speed up data transmission.
The present invention will be explained in detail with reference to FIG. 1 and FIG. 2 (a circuit diagram of the external device controller shown in FIG. 1, which is the main part of the present invention).

FIG. 2 is a circuit configuration diagram of an external device controller according to the present invention, and the data/way input/output section 7 shown in FIG. 1 is omitted. 11 to 16 and 19 in FIG. 2 correspond to the conventional DMA transfer circuit 5, and 17, 20 to 26 correspond to the high-speed DMA transfer starting circuit 6 provided according to the present invention, and this corresponds to the DMA transfer circuit 5. It is connected with OR gate 18. 11 in the figure is a data bus gate, which is a bidirectional gate that controls the connection between the data bus of the computer input/output section 2 and the internal bus ■ in the external device controller.
For example, if the input/output bus of the computer is 16 bits, 16 bidirectional gates are required. This gate is controlled by the data transfer direction. Reference numeral 12 denotes an address bus gate, which is connected to the memory address bus of the computer and accesses the memory of the computer designated by this address information during DMA transfer. Reference numeral 13 denotes a control bus skate, which is connected to the control bus of the computer, and signals from this bus are outputted according to input/output instructions from the computer program. This control bus data signal ■ is decoded by the control decoder 19 and sent to the DA register 14 through the OR gate 18.
, This is a signal for setting activation data in the DC register 15 and other registers 16. 14 is a DA (data address) register, and when attempting to start a DMA transfer, D
Set the memory address to be accessed by computer 1 in the A register. During DMA transfer, the DA register 14 counts up by +1 for each data and outputs the address information to the computer 1. 15 is Do(
The data count) register sets the number of words that the computer 1 attempts to transfer when attempting to start a DMA transfer. During a DMA transfer, the DC register is down by 1 for each C register (-1) and the DC register is 15.
DMA transfer ends when becomes zero. Reference numeral 16 denotes a register which can be freely defined by the computer system, but its contents and operations are not related to the present invention, so a description thereof will be omitted.

17 is SUB F/F (sub flip flip), D
When 5UBF/F is set by one bit of the DMA start data of the computer 1 at the start of MA transfer, data is sequentially read from the preset memory 24 and reset when the DMA transfer ends. 18 is an OR gate which outputs the logical sum of the timing pulses of the control decoder 19 and the address decoder 20. This gate allows the register setting by the input/output command of the conventional program and the preset operation of the method according to the present invention to be used in common.

Reference numeral 19 is a control encoder that inputs the computer's control data. 20 is an address decoder which decodes using the output of the address counter 25 when the preset memory 24 is in operation and sends out a set pulse. 21 is an ant gate, and 22 is a clock pulse oscillator.

25 is an address counter, and when DMA transfer is started, SUB F/F1 is set by the computer's DMA start data.
This is an up counter that is set at the same timing as 7, and the set data determines which pair of n pairs of register data in the pre-7 bit memory 24 is selected. The double line BUS in the figure is called an internal bus.
Further, LD shown at the inputs of registers and counters 14, 15, 16° 17.23 means load (Load), and these are used as preset inputs for setting data on the internal bus. Next, 24 is a preset memory, in which multiple pairs of register data for starting DMA transfer are written, and when starting DMA transfer, address counter 23 is written.
The register data pair designated by the DMA activation data given to is selected, and the DA data, DC data, and other data in the pair are read out in order and set in the corresponding register. 25 is an inverter gate, and 26 is an AND gate.

Next, we will explain the overall operation of the circuit in Figure 2 using Figure 3 (time chart of the waveforms of each part in Figure 2, where ■ to ■ on the left end of Figure 6 correspond to the positions in Figure 2). explain.

In the present invention, several types of DMA transfer starting data are written in advance in the preset memory 24, and when the computer 1 performs a DMA transfer, only the designated DMA starting data is output. In that case, the circuit of the present invention includes the UBF/F 17 data in the DMA activation meter and the address counter 26.
D that has already been written in the preset memory with the data of
One pair of register data for MA transfer is selected and read and set in corresponding registers one after another. 1st edition - 1st edition - First, the S
The DMA activation data and control data (2), which are address information of the UB F/F 17 and the address counter 26, are output from the computer.

■ Control data of control 7” Corp'
When the decoder 19 decodes, the decoder 19 outputs a pulse (2) corresponding to one period of the clock pulse (2) from the oscillator 22. At the rising edge of this pulse (2), the DMA activation data (2) is set in the SUB F/F 17 and the address counter 25. At this time, the address counter 23 enters the state α shown by (2) in FIG. α is the f + -res information of the Grisenode memory in the DMA activation data, and is incremented by 1 one after another at the falling edge of the pulse ■. On the other hand, SUB F/F 17 is shown in Figure 6■
°1゛ as shown.

(or H level) ■ノ;rus is °“0°
“A pulse ■ is generated from the AND gate 26 under the condition that
The data is output to the internal bus BTJS.

At the end, we will explain how to create a write pulse for DA data.

When the input ■ of the preset memory 24 becomes 1'', a pulse ■ is generated from the clock pulse ■ by the ant game 1 21 as shown in FIG. 5, and the DA register 14 of FIG.
, the DA register 14 enters the state shown in FIG. 5 [stock]. On the other hand, the address counter 25 is incremented by +1 with the fall of the pulse (2), and enters the state of α+1 shown in (2) in FIG. Similar to the DA register 14, the DC register 15 is also set from this α+1.

Subsequently, the other registers 16 are set in the same manner, and are brought to the state of α+2 (not shown in ①). Further, in the example of FIG. 6, when the address counter 23 reaches the state of α+5 (■), a pulse 0 is generated from the address counter 20 and the SUB F
/F 17 is reset to 0゛.

When this happens, the presetting operation of the DMA transfer start register pair is completed, and data transfer will be performed from now on.

FIG. 4B shows the structure of the time T2 required for the DMA transfer activation operation shortened by the above operation, and this diagram is the same as ① in FIG. 5. When the first DMA start data is given from the computer, DA data, DC data, etc. are automatically generated in sequence as described above, and there is no signal exchange with the computer during this time, so the time required for the DMA transfer start operation is T2. Time required for conventional method T1
A speed increase of 1/10 or less is achieved compared to the above. Note that TD in FIG. 4 indicates the time during DMA transfer.

In addition, since the data set in the DA register 14'' and the DC register 15 in FIG. Congested DMA transfer register data pairs can be used repeatedly.

This is one of the features of the invention.

[Brief explanation of the drawing]

FIG. 1 is an inverted computer system configuration showing the relationship between an external device and a computer in which the present invention is implemented, FIG. 2 is an inverted circuit configuration of an external device controller in which the present invention is implemented, and FIG. Time chart of waveforms of each part, 4th
The figure is a time chart comparing the conventional method and the method using the present invention regarding DMA transfer activation time. 1... Computer, 2... Input/output section, 6
...external device, 4...external device controller,
5...DMA transfer circuit, 6...High speed DMA
Transfer starting circuit, 7.9...Data highway input/output unit, 8...Data highway, 10...(Peripheral) device, 11...Data basket), 12...Address bus 'y' -1-113...Control bass skate, 14...DA register, 15...Dc
Register, 16...Other registers, 17...
・SUB F/F. 18...Or gate, 19...Control Tecoder, 20...Atre Tecoder, 21.
26...and gate, 22...oscillator,
23... Address counter, 24... Preset memory, 25... Inverter gate. Patent applicant: Kokusai Denki Co., Ltd. Agent: Manabu Ohba and 1 other person

Claims (1)

[Claims] It is equipped with an address counter, a clock oscillator, an address counter, a sub-flip-flop that controls the operation of setting data in each register, a preset memory in which multiple pairs of register data for starting DMA transfer are written, and multiple gates, and these can be accessed from the computer. D
A high-speed DMA transfer activation circuit characterized by being able to perform MA transfer at high speed.