GB2181578A - Clock delay for microprocessor - Google Patents

Abstract

The present invention is for increasing the performance of a microprocessor CPU coupled on a bus to a plurality of data processing devices. The invention includes a finite state machine coupled between a clock generator and the CPU for generating the CPU clock and extending predetermined clock cycles (as at 4) for a predetermined fraction of a cycle. Logical operations in the CPU are held in await condition for the time the clock signal is extended. The induced delay of the predetermined clock signals occurs only during operations involving signal transmissions between a data processing device and the CPU over the bus. For internal CPU operations not involving bus access, the CPU is driven at its maximum permitted rate. Accordingly, the performance of the CPU is increased since the CPU need not be maintained for complete CPU clock cycles in a waiting state until the slower data processing device which it is accessing over the bus completes operation. <IMAGE>

Description

SPECIFICATION Clock delay for microprocessor BACKGROUND OF THE INVENTION 1. Fieldoftheinvention: The present invention relates to performance optimization systems for microprocessors, and more particularly, to systems for improving the efficiency of a microprocessorcoupledtoa plurality of data processing devices on a bus.

2. Artbackground: It is typical in many data processing systems to couple a microprocessor to a plurality of data processing devices, such as for example, printers, RAM memories, magnetic disks and the like, along a system bus. As is well known, the microprocessor includes digital circuitry which completes logical operations in accordance with clock signals provided bya clock generator. The clock generator may comprise a crystal based oscillator disposed either on the microprocessor chip itself, or external to the chip. The clock generator provides cyclic repetitive digital signals of a fixed frequency to the microprocessor.

All microprocessor operations are synchronous with the clock generator signals which are applied.

Although microprocessor operations are controlled by the frequency of the clock signals, the ac quisitiontimeforcommunicatingwithotherdata processing devices coupled to the common bus is a function of the speed of the particular device. For example, although the microprocessor may operate at maximum speed (for example 33.3 MHz) as driven by the clock, other devices, such as random access memory(RAM)generallycannotoperateatthe speed of the microprocessor. In the event the microprocessor issues a read command to obtain data stored in a RAM coupled to the bus, the processor must generally wait until valid data is applied to bus data lines by the RAM to permit the data transfer operation to be completed.During this wait period, the microprocessor must interrupt its operations during the clock cycles required for the RAM to apply valid data to the bus. Other data processing devices, such as magnetic disks and the like, also requirethemicro- processor to delay processing operations until the data transfer is complete.

As will be described, the present invention provides methods and apparatus for increasing the performance of a microprocessor coupled to slower data processing devices. Afractional increment of a predefined time may be added to particular clock cycles, to delay subsequent cycles sufficiently long to permit a slower device to complete the requested operation. At present processor speeds, the time savings of the fractional increment provided by the present invention is significant compared to waiting the standard full clock cycle.

Summary of the invention The present invention provides apparatus and methods for increasing the performance of a microprocessor (CPU) employed in a data processing system coupled on a bus to a plurality of data processing devices. The invention includes a finite state machine coupled between the clock source and the CPU for generating the CPU clock and extending predetermined clock cycles for a predetermined fractional increment. Logical operations employed by digital circuitry in the CPU are held in a wait condition for the time the clock signal is extended. The induced delay of the predetermined clock signals occur only during operations involving signal transmissions between a data processing device and the CPU overthe bus. For internal CPU operations not involving bus access, the CPU is driven at its maximum permitted rate.Accordingly, the performance of the CPU is increased since the CPU need not be maintained for complete clock cycles in a wait state until the slower data processing device which it is accessing completes its operation.

Brief description of the drawings Figure 7 is a block diagram generally illustrating the architecture of the present invention.

Figure 2(a) is a timing diagram illustrating a typical prior art system wherein data is provided to the CPU immediately after the completion of a clock cycle, thereby delaying the aquisition of data until thefollowing cycle.

Figure 2(b) is a timing diagram illustrating the use of the present invention to increase the length of predetermined clock cycles by fractional increments.

Detailed description of the invention Apparatus and methods for increasing the performance of a central processing unit (CPU) employed in a data processing system coupled to a bus having a plurality of data processing devices is disclosed. In the following description for purposes of explanation, specific numbers, cycle times, memory devices, CPUs, etc. are set forth in order to provide a thorough understanding the of present invention.

However, it will be apparentto one skilled in theart thatthe present invention may be practiced without these specific details. In other instances, well known circuits and devices are shown in block diagram form in order not to obscure the present invention unnecessarily.

Referring to Figure 1 ,the present invention is illust rated in a generalized clockdiagram form. ACPU 10 is coupled to a plurality of data processing devices (DP#A...DP#N) over a bus 12. The data processing devices include, for example RAM 14 (DP*A) as well as other devices such as disk drives, printers, and other data processing resources. A clock source 16 provides a repetitive cyclic digital signal having a predetermined frequency, as is known in the art. In the presently preferred embodiment, clock generator 16 outputs digital signals having a frequency of 33.333 MHz, and is driven by a crystal oscillator.The output of clock source 16 is coupled to a finite state machine 18 which, as will be described, delays predetermined cycles of the system clock signal (line 20) to permit maximum utilization of CPU processing time. Although in the presently preferred embodi ment,thefunctions of the present invention are provided by a finite state machine disposed in a programmable array logic (PAL) device, it will be app reciated byoneskilledintheartthatfinitestate machine (FSM) 18 may comprise a variety of digital circuits which utilize various forms of hardware as well as software. The finite state machine outputs a system clock signal to CPU 10 over a system clock line 20.As illustrated, a bus cycle line 22 is provided between CPU 10 and FSM 18 to permit feedback communication between CPU 10 and FSM 18. Itwill be noted that the embodiment illustrated in Figure 1 is diagrammatical in form, and illustrates those signals unique to the present invention. However, other control signals and lines, such as data lines, address lines and the like are not shown for sim- plicity. Although not described in the Specification these other lines, signals and the like will be apparent to one skilled in the art.

With reference nowto Figures 1 and 2, the operation of the present invention will be described. As previously discussed, clock source 16 outputs a digital clock signal of a predefined frequency that drives finite state machine 18. When CPU 10 is executing logical operations which do not involve data transfers along bus 12, CPU 10 operates at its maximum frequency. The maximum frequency clock is supplied by FSM 18 via clock line 20. As is well known, microprocessors perform logical operations in accordance with full block cycles, such that each sequence of logical operations performed internally occur in accordance with full block cycles such as those illustrated in Figure 2(a).In instances where CPU 10 accesses data processing devices coupled to bus 12 (e.g. in a read or write mode), many ofthose devices operate at different speeds than that of the microprocessor. For example, in the event CPU 10 is instructed to read data stored in RAM 14, the CPU issues a read command over bus 12. Upon receipt of this command as well as valid address information, RAM 14 accesses that portion of its memory and applies the valid data to data lines on bus 12. Thetime required for RAM 1 4to access the data and respond to the read command of CPU 10 is generally much slower than the operating speed of the microprocessor.During the time RAM 14 is completing the read operation, CPU 10 would, in prior art systems, be maintained in a wait state for an integer number of clock cycles until valid data is applied to the data lines of bus 12. Forexample, if a read request is issued by CPU 10 in clock state 0, and valid data is applied just after clock state 7, CPU 10 could not access such valid data until the nextfull clock cycle, since the micro- processor is incapable of waiting fractions of clock periods (see Figure 2(a)).

With reference nowto Figure 2(b), the operation of the present invention is illustrated. In the event CPU 10 is required to communicate with data processing devices coupled to bus 12, a bus cycle indicator signal is applied to bus cycle line 22 and received by FSM 18. In the present embodiment FSM 18 delays the fourth clock state from the beginning of the bus access cycle of the system, a predetermined fractional increment of the cycle time. In the present em bodiment, FSM 18 "stretches" the fourth clock state within the bus access cycle by 100% as illustrated best in Figure 2(b). The stretching of the fourth clock state delays all internal logical operations of the mic roprocessorfor an additional half of a cycle.Thus, although CPU 10 is unable to function based on fractions of clock periods, the effect ofthe present invention is to delay all internal operations of the microprocessorforan additional stretch period to permit slower devices such as RAM 14, to complete the requested data operation and provide valid data on bus 12 by clock state 7. From the perspective of CPU 10, it receives valid data from the data lines of bus 12 atthe completion of the sixth clock state, and thereby obviates the need for CPU 10 to be maintained in a wait state for integral multiples of the clock cycle. For example, in the operations illustrated in Figure 2(a), absent the present invention, CPU 10 would be unable to read valid data u ntil the com pletion of state 8 (beginning of state 9).However, by using the present invention's delay system, valid data is read by CPU 10 at the completion of clock state six in the bus cycle.

It will be appreciated, that although the present invention is illustrated and described with reference to particular clock states to be "stretched" and with regard to particular data processing devices coupled to bus 12, that the present invention may be utilized in any of a number of ways in order to increase the performance of CPU 10. For example, using the present invention clock states may be stretched by any predefined fractional increment of the given cycle, and that any combination or multiple of clock states may be extended as required by the particular application and system configuration.

Using the present invention, system performance is increased by eliminating wasted overhead in CPU "wait condition" clock cycles. As shown in Figures 2(a) and 2(b), the time savings using the present invention may be measured as the difference in clock cycles to complete a full bus cycle. In the present embodiment, a device communicating with the CPU 10 transmits a DSACKsignal prior to ending the bus cycle. Upon sensing the DSACK signal (which must occur on a negative edge), the CPU 10 expects any valid data to be present on the lines one clock cycle later. As shown in the Figures, the present invention permits the completion of the bus cycle sooner, and therefore maximizes system performance.

Accordingly, apparatus and methodsforincreasing the performance of a central processing unit employed in the data processing system coupled on a bus to a plurality of data processing devices is disclosed. As the speed of processors increase, itwill be appreciated that the advantages of the present invention become more pronounced. While the present invention has been particularly described with refer ence to the embodiment illustrated in Figures 1 and 2, it is contemplated that many modifications and materials, cycletimes, and architectures could be made by one of ordinary skill in the art without dep- arting from the spirit and scope of the invention.

Claims (14)

1. An apparatus for increasing the performance of a central processing unit (CPU) employed in a data processing system coupled to a plurality of data processing devices, comprising: clocking means for generating a repetitive cyclic digital signal of a predefined frequency; delay means coupled to said clocking means and said CP for extending predetermined cycles of said cyclic digital signals generated by said clocking means by a predefined fractional increment of said signals, such that the logical operations employed by digital circuitry in said CPU are held in abeyance for the time said signals are extended, said delay means extending said predetermined signals only during operations involving signal transmissions between a data processing device and said CPU; whereby the performance of said CPU is increased.

2. The apparatus of claim 1, wherein said clocking means generates signals at a rate of 33.3 MHz.

3. The apparatus of claim 1,wherein said CPU comprises a Motorola 68020.

4. The apparatus of claim 1, wherein said frac- tional increment comprises 1/2 of a clock cycle generated by said clocking means.

5. The apparatus of claim 4, wherein at least one of said data processing devices comprises a digital memory.

6. The apparatus of claim 5, wherein said CPU and said data processing device are coupled to a bus, andabuscyclegenerallycomprisingeightclock states.

7. In a data processing system, including a central processing unit (CPU) coupled to a plurality of data processing devices, a method of increasing performance of said CPU, comprising the steps of: generating a repetitive cyclic digital signal of a predefined frequency; extending predetermined cycles of said cyclic digital signals by a predefined fractional increment of said signals, such that the logical operations employed by digital circuitry in said CPU are held in abeyance forthe time said signals are extended, said signals being extended only during operations involving signal transmissions between a data processing device and said CPU; providing said cyclicdigital signalsto said CPU; whereby the performance of said CPU is increased.

8. The method of claim 7, wherein said cyclic digital signals are generated at a rate of 16.67 MHz.

9. The method of claim 7,wherein said CPU comprises a Motorola 68020.

10. The method of claim 7, wherein said fractional increment comprises 1/2 of a clock cycle generated by said clocking means.

11. The method of claim 10, wherein at least one of said data processing devices comprises a digital memory.

12. The method of claim 11, wherein said CPU and said data processing devices are coupled to a bus, a bus cycle generally comprising eight clock states.

13. An apparatus for increasing the performance of a central processing unit (CPU) substantially as hereinbefore described with reference to the accompanying drawings.

14. A method of increasing performance of said CPU substantially as hereinbefore described with reference to the accompanying drawings.