JPS60112158A - Control circuit of peripheral device - Google Patents

Abstract

PURPOSE:To allow a peripheral device, which is operating in synchronization with a reference signal, to be accessed by a CPU, which is operating at higher speed than the reference signal, without changing the frequency of the reference signal by providing an access timing detection circuit, etc. CONSTITUTION:When a CPU1 accesses to a peripheral device 2, a detection signal 11 is given to an access timing detection circuit 13 through a detection circuit 3. The interior of the detection circuit 13 corresponds to a phase of the detection signal 11 for a reference signal 16, and outputs an access timing detection signal 18 to an action speed control circuit 4. The circuit 4 weights the CPU1 according to the signal 18, so that an E clock 8 is outputted from the CPU1, and due to the E clock 8, a select signal 17 is outputted from the circuit 13. The signal 17 allows secure input/output of an address and data during a specific period of one frequency of the reference signal 16 so that the device 2 will not execute an erroneous operation. By providing the circuit 13, etc., a CPU operating more quickly than the reference signal can access without changing frequency of the reference signal.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a peripheral device control circuit that allows an arithmetic processing unit in a computer system or the like to access a peripheral device that is slower than its operating speed. .

[Background of the invention]

When an arithmetic processing unit accesses a peripheral device whose operating speed is slower than its operating speed, conventional methods have been considered.

Figure 1 shows an example of this.
1 is an arithmetic processing unit (hereinafter referred to as IMMC, abbreviated as CPU), 2 is a peripheral device, 3 is a peripheral device access detection circuit, and 4 is a CPU
5 is a clock and clock signal for operating the CPU, 6 is a data bus, and 7 is an output speed control circuit.
s indicates a bus cycle of c'PU) (a cycle signal; 9 is an enable signal given to a peripheral device (a signal indicating the access period of the peripheral device); 10 is a peripheral device.

11 is a peripheral device access detection signal, and 12 is a speed control signal for ctU. Here, if we consider the Hitachi microcomputer 6so'q as apl, the bus cycle signal 8 is 68.
Corresponds to the E clock signal of o9, and the speed control signal 12 is 6
Corresponds to the MREADY signal to 8o9. In such a configuration, a timing diagram is shown in which the peripheral device 2 operates at 1A, which is the operating speed of the CPU 1 (for example, when the CPU 1 operates at 2 MHz and the peripheral device 2 operates at 1 MHz). In figure b, which is figure 2,
8(a) shows the E clock of 8, FIG. 2(b) shows the enable signal of 9, and FIG. 4(c) shows the chip select signal of 1o. In this method, the access of the peripheral device 2 is detected by the detection circuit 6, and only at that time, the operating speed of the CPU 1 is adjusted to the operating speed of the peripheral device 2, and an enable signal 9 and a chip select signal 10 are given to the peripheral device 2 to prevent the access. It is something to be carried out. However, this method only enables the enable signal 9 when accessing the peripheral equipment 2.
Therefore, peripheral devices (such as those that use the enable signal 9 as a timing signal for the device)
For example, peripheral devices using Hitachi ICHD6821, etc.)
It has the disadvantage that it cannot be applied to

A method as shown in FIG. 6 cannot be considered as a method for solving these drawbacks. That is, the pass cycle signal 8 (6
809, and when accessing the peripheral device 2, the operating speed of the CPU 1 is matched to the operating speed of the peripheral device 2, as in FIG. However, in this case, it is necessary to be able to input a signal with a frequency faster than the operating speed of the peripheral device 2 as an enable signal to be given to the peripheral device 2, but many peripheral devices, such as those using the HD6B21, Since the highest frequency and highest operating speed of the enable signal are pl-, the method of FIG. 3 cannot be used as is. Even if the method of FIG. 3 can be applied, hypothetically, the maximum frequency of the enable signal of a peripheral device is faster than the maximum operating speed of that device.
Since the frequency of the enable signal changes each time the peripheral device is accessed, the enable signal cannot be used in a transmission device that performs time management.

Therefore, in situations where neither the method shown in Figure 1 or Figure 3 can be applied, use peripheral equipment that operates at the same operating speed as the CPU, or adjust the speed of the CPU to match the operating speed of the peripheral equipment. I had no choice but to slow down and use it.

[Purpose of the invention]

An object of the present invention is to eliminate the drawbacks of the prior art and to enable a CPU that operates faster than the reference signal to access a peripheral device that operates in synchronization with a reference signal without changing the frequency of the reference signal. be.

[Summary of the invention]

The main point of the present invention is that the CPU for reference signals to peripheral devices
The purpose of the present invention is to distribute the operating speed of the CPU according to the peripheral device access timing, and to control the address bus between the CPU and the peripheral device.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail based on examples.

FIG. 4 is a professional diagram showing one embodiment of the present invention.

In the figure, parts of the jirl in FIG. 16 is a reference signal to the peripheral device and is a signal given as an enable signal for the peripheral device 2, 17 is a peripheral device (to)
The chip select signal of the peripheral device 2 and the address bus control circuit 14 and data bus control circuit 15 are
It is used as a control signal. 5 and 6, in order to explain one embodiment of the present invention, a microcomputer 6809 manufactured by Hitachi is used as the CPU, and peripheral devices 2
A timing diagram is shown when operating at a speed 0.02 times faster.

FIG. 5 and FIG. 6 show cases in which the access timings for the −7-7 reference signal are different.

In the figure, (a) shows the reference signal/signal of FIG. 4, 16,
(b) is signal 8 and the CPU is 68 D 9, E
(C) shows 17 select signals. FIG. 5 shows that the CPU outputs "L" of the reference signal 16 in (a).
” shows the case where peripheral device 2 is accessed during the period,
After the detection circuit 3 detects the access of the peripheral @2, the access timing detection circuit 15 detects that the access occurs during the rLJ period of the reference signal 16. When an access from a peripheral device occurs during the rLJ period of the reference signal, the speed control circuit 4 inserts a wait of one bus cycle to the CPU. Therefore,
The E-cross and ψ-r from the CPU are as shown in FIG. 5(b). At the same time as and 11, a select signal 17 as shown in (c) is applied to the address bus control circuit 14 and the data bus control circuit 15, and only during the rLJ period of this signal, the CPU 1
In FIG. 6, the CPU controls the r of the reference signal 16 of (a) so that the address bus and data bus of the peripheral device 2 become conductive.
HJ period M 4m This shows the case where peripheral device 2 is accessed. In this case, as in FIG. 5, with a wait of 1 nox cycle, the CPU'1 will access the peripheral device 2 during the "L" period of the reference signal 16 in (a), but the peripheral device In case 2, read/write operations are possible only during the rHJ period of the reference signal 16 in (a), so normal read/write operations cannot be performed in the case of kneading. Therefore, in this case, as shown in FIG. 6(b), the next r of the reference signal 16 is
A wait of 2 cycles is inserted so that read/write is performed during the HJ period.In other words, in this case, the operating speed of the CPU 1 is made slower than the operating speed of the peripheral device 2.Furthermore, at this time , the select signal 17 corresponds to the first falling edge of the reference signal 16 (the sixth edge) when the CPU 1 starts accessing the peripheral device 2, as shown in FIG.
It is necessary to perform rLJ later than point ■ in the figure). this is,
If the select signal 17 is set to "L" at the same time as the CPU 1 accesses the peripheral device 2 (that is, before the 0 point), the peripheral device 2 will read/write during the first "H" period of the reference signal 16. When accessing -
This is to prevent malfunctions due to insufficient time. The data bus 6 and address bus 7 are controlled by the select signal 17 (C) during a specific period of one cycle of the reference signal 16 (see FIG. 5) to prevent the peripheral device 2 from malfunctioning.

This is to ensure that addresses and data are input/output only during the latter half (37'4 period in FIG. 6). This is particularly effective when the address is decoded inside the peripheral W2 and used as a chip select signal for the internal circuit. However, this address bus control circuit 14 and data bus control circuit 15,
In some cases, it may be omitted.

Next, FIG. 7 shows a specific circuit configuration example of the access timing detection circuit 13 that realizes the timing signals shown in FIGS. 5 and 6, and FIG. 8 shows its main timing diagram.

In FIG. 7, the same parts as in FIG. 4 have the same symbols,
19 is a so-called PLL (Phase Lock) which oscillates at twice the frequency of the reference signal 16 in synchronization with the reference signal 16.
d Loop) circuit, 20~25dx-v Citrigger mD free, So7'' flow.

24 and 25 are NAND gates, 26 is an OR gate, 27
is the inverter, 28 is the output signal of the PLL 19, and 28 is the signal with a frequency 1602 times the reference signal.
9 is a signal as shown in FIG. In Figure 8,
Each signal number corresponds to Fig. 7. and,
(a) is a signal that is always output regardless of the operation of the CPU 1; (b) is a signal that is output when the peripheral device 2 is accessed during the rLJ period of the reference signal 16; (C) is a signal that is output when the reference signal 16 is "H". The timing is shown when the peripheral device 2 is accessed at period j=+. When the CPU 1 accesses the peripheral device 2, the detection circuit 3 detects the fidget (for example, decodes the address of the peripheral device 2) and outputs the detection signal 11.
is applied to the access timing detection circuit 13 in FIG. Inside the access timing detection circuit 13,
The 8th tab flop 21, 22 and the NAND gate correspond to the phase of the detection signal 11 with respect to the reference signal 16.
Access timing detection signals 18 having different pulse widths as shown in FIGS. 0)) and (c) are output to the operating speed control circuit 4. The operating speed control circuit 4 applies a weight to the CPU 1 according to the access timing detection signal 18, and
E black/yri 8 as shown in Figures (b) and (c) is C
Output from PU1. Then, using the E clock and the check 8, select as shown in FIG. signal 1
7 is output.

In the example shown in FIG. 7, a PLL circuit is used to obtain a signal with twice the frequency synchronized with the reference signal 16, but other methods may of course be used. In addition, in CPU6809, E black, ν
Since the clock signal 5 is a signal with a frequency four times that of the clock signal 8, the frequency-divided signal of the clock signal and the clock signal by four is used as the signal 2 in Fig. 7.
8 and further use the frequency-divided signal by 2 as the reference signal 16.

5 to 8 show the case where the falling edge of the E clock 8 and the change in the reference signal 16 are in phase, but next we will discuss an example of a case where the phases are not in sync. are shown in FIGS. 9 and 10.

FIG. 9 shows a case where the peripheral device 2 starts accessing in the latter half of the rHJ period in (a), and at this time cPUl is 1.5
Insert pass cycle weight (6809ha 1/4
Waiters can be inserted in cycle units). FIG. 10 shows a case where access by the peripheral device 2 is started in the latter half of the rLJ period in (a), and at this time a wait of 2.5 bus cycles is inserted. This figure 9, 10
What should be noted in the figure is when the CPU 1 reads the peripheral device 2. The read data of peripheral device &1.2 is usually the rf signal of (a) (since it is not output during the J period,
As shown in Figures 9 and 10, E Klofka (a) of (b)
A normal read operation cannot be performed at the falling timing of the rLJ period, but in such a case, it is only necessary to read the data from the data bus control circuit 1sI when reading the peripheral device 2. . However, if the phases are not matched, it goes without saying that it can be handled in the same way as the previous example by adjusting the phases using a PLL circuit or the like.

In the above description, a case has been described in which the operating speed of the CPU 1 is twice the operating speed of the peripheral device 2, but in the present invention, this operating speed may be twice that. For the triple case, the timing is shown in Figures 11, 12, and 13.
As shown in the figure. (a), (b), (c) in the figure are
It shows the same fidgeting signal as in FIGS. 5 and 6. In this case, the peripheral device 2 of the CPU 1 in response to the signal in (a)
There are six cases depending on the access timing. 1st
As shown in FIG. 1, when the access of the peripheral device 2 is started in the first half of the rLJ period in (a), a wait of two bus cycles is applied. As shown in FIG. 12, when the access of the peripheral device 2 is started in the latter half of the "L" period in (a), a waiter of 4 bus cycles is applied.

Furthermore, as shown in FIG. 13, when the access of the peripheral device 2 is started during the rHJ period of (a), a wait of 6 bus cycles is applied.

Although the present invention has been explained based on some embodiments, the main point is that
It is only necessary to control the operating speed of the CPU and, as the case may be, the period of supplying the bus to peripheral devices in accordance with the timing of the CPU's access to the reference signal.

〔Effect of the invention〕

According to the present invention, a peripheral device that operates in synchronization with one reference signal can be accessed by a CPU that operates at a frequency higher than that of the reference signal without changing the reference signal.

[Brief explanation of the drawing]

FIGS. 1 and 6 are a diagram of a peripheral device control circuit according to the prior art, and FIG. 2 is a diagram showing the main timings of the peripheral device control circuit. Figures 5 and 6 are its main timing diagrams, Figure 7 is a diagram showing one example of a specific circuit of the access timing detection circuit, Figure 8 is its main timing diagram, and Figures 9 to 1 are the main timing diagrams.
FIG. 3 is a diagram showing another timing example illustrating the present invention. DESCRIPTION OF SYMBOLS 1... Arithmetic processing unit (CPU), 2... Peripheral device, 5... Peripheral device access detection circuit, 4... Operating speed control circuit, 13... Access timing detection circuit, 14... Address bus control circuit, 15... Data bus control circuit, 16... Difference rate signal to peripheral device. Fig. 7/R Fig. 8 (Ct) /7 Fig. q Fig. 70 (of

Claims (1)

[Scope of Claims] 1. In a peripheral device control circuit in a computer system or the like having an arithmetic processing unit and a peripheral device that operates in synchronization with a reference signal, detecting the peripheral device access timing of the arithmetic processing unit with respect to the reference signal. an access timing detection circuit; and an operation speed control circuit that controls the operation speed of arithmetic processing in accordance with the peripheral device access timing; A peripheral device control circuit whose characteristic is to change the operating speed of a peripheral device. 2. Equipped with an address bus control circuit for the above peripheral device,
2. The peripheral device control circuit according to claim 1, wherein the peripheral device control circuit controls an address supply period to the peripheral device in accordance with peripheral device access alignment with respect to a reference signal of the arithmetic processing unit.