JPS62154045A - Bus arbitration system - Google Patents

Abstract

PURPOSE:To prevent the decrease in response performance even in a real time microprocessor system by having the function in which a main processor executes the bus right acquisition request even while another processor holds the bus right, by the main processor and the another processor. CONSTITUTION:While a main processor 1 executes a memory access and executes the program, when another processor 2 such as DMAC accesses the memory, the another processor asserts an HREQ and requests the bus right to the main processor. The main processor, when it is detected that the HREQ is asserted, asserts a HACK and delivers the bus right to the another processor. At such a time, respective signal pins of an address and address strobes AS and R/W' are made into a high impedance. An external processor, when it detects the low level of the HACK, knows that the main processor give up the bus right, comes to be a bus master and executes the memory access such as a DMA transfer.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a multiprocessor system and its bus arbitration method, and particularly to a bus arbitration method suitable for a system that responds to interrupts in real time. Regarding.

[Background of the invention]

As bus arbitration methods in conventional multiprocessor systems, a first method using two control signals and a second method using three control signals are known.

The first method is used in the Intel 8086 system. (Refer to the Intel 8086 data sheet.) The Intel 8086 processor uses the HOLD signal, which allows an external device to request bus ownership, and the HOLD signal, which allows the 808.6 processor to acknowledge the bus ownership request.
Acknowledgment) There is an M issue.

When an external device asserts HOLD and requests bus ownership, and the 8086 processor asserts HOLDA and passes the bus ownership to an external device, for example another processor, the processor that acquired bus ownership negates the HOLD signal. , the 8086 processor cannot acquire bus rights.

Another example of the tj51 method is Zaoo from Zilog.

It is a processor. (Refer to the Zilog 28000 data sheet) When the zsooo processor's bell is input, the 28000 processor will pass the bus to another processor.

regain rights. While B tJ S RE Q is asserted by another processor, the Z8000 processor has no way to gain control of the bus.

Another example of the first approach is the National Semiconductor N532032 processor.

(Refer to National Semiconductor's N532032 data sheet) In the NS32032 processor, when another processor passes the bus as a signal to request the bus, the processor passes the bus as a signal to another processor, and when HOLD is negated, , N532032 processor has no means to request bus ownership. The second bus arbitration method
A conventional example of this method is the Motorola 5sooo processor. (Hasuda et al. "68000 Microcomputer", Maruzen, P35-P38) In the 68000 processor, BR (Bus Request), BGA c
The three signals (Knowledge) are used for bus arbitration. As shown in Figure 310 (P37) of the above-mentioned document, the 68000 processor had no means to acquire the bus right after the bus arbitration was completed, that is, until the bus right was negated by the external device.

As described above, according to the bus arbitration method of conventional multiprocessor systems, when an external device requests bus ownership, the main processor unconditionally releases the bus ownership; While taking over, the main processor may remain idle, which may not provide sufficient response time, especially in real-time systems.
Let us consider the case where ssMemoryCont,roller) becomes the bus master and performs DMA transfer of IKF3 in birth mode.

A DMA transfer is a transfer between a memory system and an input/output device (e.g., a disk device) or between a memory system and an input/output device controller (e.g., a hard disk controller), and is performed without going through the main processor. This is data transfer. The DMAC generates an address for the memory system and a DMA transfer command signal for the input/output device or input/output device controller.
Controls DMA transfer.

The data bus is 32 bits, four clock cycles are required for DMA transfer of 32 bit data, and the clock frequency is 10 MHz. In this case, 12.8 μs is required for r)MA transfer of IKB. During this time, the main processor is in a non-processing state and cannot obtain sufficient response time when an interrupt request is received. For this reason, response performance sometimes deteriorates particularly in real-time systems that require high-speed response. That is, in conventional systems, sufficient consideration has not been given to bus arbitration in real-time systems.

[Purpose of the invention]

An object of the present invention is to provide a bus arbitration method that does not degrade response performance even in a real-time microprocessor system.

[Summary of the invention]

The present invention achieves the above object by providing the main processor and another processor with a function that allows the main processor to request acquisition of bus ownership even while another processor holds bus ownership.

[Embodiments of the invention]

FIG. 1 is a block diagram of an embodiment of a microcomputer system using a bus arbitration method according to the present invention.

In FIG. 1, a main processor l (e.g. CPU
: Central Processing Uni
t, ) and another processor 2 (for example, DMAC) are devices that can take bus authority. That is, the main processor 1 uses the address bus 3. Address strobe AS (Ad
dressStrobe) signal 4 R/W (Rea
d/Write) signal 5 to transfer data between the main processor 1 and the memory system 6, between the main processor 1 and the input/output processor 7, and between the main processor 1 and another processor 2 via the data bus 8. , On the other hand, another processor 2 has an address bus 3゜address strobe A.
S (controls No. 6 4 to transfer data between the memory system 6 and the input/output processor 7).

Here, whether the main processor or the DMAC has bus authority, that is, whether the main processor or another processor uses the address bus 3 or the address strobe signal,
! It is necessary to stop IIJ.

As another processor 2, in addition to DMAC, another CPU
Alternatively, a hard disk controller with a DMA function, a network controller, a single-chip microcomputer, etc. can be considered.

(Hold Rsquest) (l! issue and HA
A CK (Hold Acknowledgment) signal is used.

FIG. 2 is a flow chart showing the operation of the bus arbitration method in the microcomputer system of FIG.

In Figure 2, setting a high-active signal to a high level or a low-active signal to a low level is called assert; conversely, setting a high-active signal to a low level or a low-active signal (see No. 73) Setting it to a high level is called negate.

If another processor such as a DMAC accesses the memory while the main processor is executing a program while accessing the memory, the other processor asserts HREQ and requests bus ownership from the main processor.

When the main processor detects that Hr<)':Q is asserted, it asserts HACK and passes the bus right to another processor. At this time, the address, address strobe As, and R/W signal pins are set to high impedance. When the external processor detects the low level of HACK, it knows that the main processor has released the bus right, and
It becomes a bus master and performs memory access such as DMA transfer.

Consider the case where an interrupt request is issued to the main processor while another processor is accessing the memory by taking bus control. In the present invention, as shown in the flowchart of FIG. 2, the main processor sets HACK to negated 1 and requests bus ownership from the external processor. When the external processor detects that HACK has been negated, it negates HREQ and releases the bus. When HREQ is negated, the main processor becomes the bus master again, obtains the right to use the bus, and performs memory access such as program execution.

FIG. 3 is based on the flowchart of FIG. 2. FIG. 3 is a diagram illustrating an example of timing of bus arbitration.

In FIG. 3, the signal lines of the main processor are address (main processor output) and AS (main processor output).

On the other hand, the signal line of another processor.

HREQ (output of another processor), IAcK (input of another processor), address (output of another processor).

AS (separate processor output) and R/W (separate processor output).

The main processor and separate processors operate with the same clock or with asynchronous clocks. In the embodiment shown in FIG. 3, to simplify the explanation, a case where operations are performed using the same clock is shown.

In FIG. 3, the main processor has the right to use the bus at clock 1, outputs an address at clock 1, asserts AS seven times at clock 2, and executes one data transfer up to clock 4. When the MPU requests bus ownership by accessing the MPU, that is, when the bus cycle currently being executed by the MPU ends, it is notified that the bus will be handed over to another processor.

Becomes another process bus master and acquires the right to use the bus. The bus is asserted and the address, AS, and R/W are set to high impedance state (intermediate level in Figure 3) and the right to use the bus is passed to another processor.The other processor outputs the address at clock 6 and outputs the address at clock 7. Assert AS and perform one data transfer up to clock 7, e.g. D M A k
, execute the send.

Another method for passing the bus right from the main processor to another processor is for the main processor to assert HACK at clock 3 or clock 4. In this case, the other processor detects that the AS output of the main processor becomes a high level or high impedance state and becomes the bus master.

Get bus rights. If the main processor has a bus lock signal such as BUSLOCK,
It is necessary to wait until the K signal is negated and the AS output becomes a high level or high impedance state.

The main features of the present invention are as shown in FIG.

By negating HACK, the main processor can request another processor for bus ownership. In FIG. 3, the main processor negates HACK at clock 7.

When another processor detects the high level of F(ACK),
Another processor negates HREQ after the currently executed bus cycle ends, that is, at clock 10, and takes over the bus.
Inform tJ that you will return it. When the main processor detects the high level of HREQ.

Become a bus master. That is, 1 at clocks 11 to 14.
One data transfer is executed, and the next data transfer is executed at clocks 15-18. The bus is clocked and requests the bus, but the bus will not be granted until certain conditions are met. The predetermined condition is, for example, when a bus request permission bit in the status register of the main processor is set.

Another processor finishes the data transfer and takes over the bus right to the MPU.
FIG. 4 shows a flowchart for returning the data to the computer, which is a conventional method.

When the other processor completes a series of memory accesses such as DMA transfer, it negates HREQ and releases the bus mastership.The main processor becomes the bus master again for the other processor and performs memory accesses such as program execution. At the yard, the main processor is HREQ
Waiting while is asserted.

In addition to such conventional functions, the present invention is characterized in that the MPU can request bus rights to peripheral processors, as shown in FIG.

The difference between the flowchart of FIG. 4 and the flowchart of FIG. 2 is that after the main processor releases the bus right, it requests another processor for the bus right and waits.

FIG. 5 is a diagram showing an example of the timing of the bus arbitration method according to the flowchart of FIG. 4. Third, the HACK signal is negated.

In FIGS. 3 and 5, at the falling edge of HACK, the main processor transfers bus ownership to another processor, and
At the rising edge of HREQ, another processor transfers bus ownership to the main processor, thus.

The bus control output of the main processor may be enabled at the rising edge of HREQ, and the bus control output of another processor may be enabled at the falling edge of HACK. At power-on reset, the main processor has bus authority.

FIG. 6 shows an example of an input/output buffer control circuit.

In the flip-flop 20, the Q output becomes high level at the rising edge of the S (set) input, and the Q output becomes low level at the rising edge of the R (reset) input.The Q output is an inverted signal of the Q output. Therefore, when HREQ rises or is reset, the Q output of the flip-flop 20 becomes high level and the Q output becomes low level. This allows main processor 1
side tri-state buffer (21 to 24, 27, 28
゜37, 38) is enabled, and the tri-state buffer (121 to 124, 127゜128) on the other processor 2 side is enabled.
．． 137, 138) are in a high impedance state. That is, the tri-state buffers 21 and 22 are enabled, and the address 61 of the main processor l is transferred to the system bus 19.
Output to. As many tristate buffers as there are address buses 61 are required to enable the address buses 61. In FIG. 6, only two are shown. At the same time, the tri-state buffers 23,24 are enabled and the AS(yi) of the main processor l is activated via the control bus 62,63, respectively.

The R/W signal is output to the system bus 19.

Also, since the direction of the data bus depends on the R/W signal,
When the R/W signal is high level, AND gate 25.3
5 is set to high level and AND gate 26.36 is set to low level to enable tri-state buffers 27 and 37. When the R/W signal is at low level, the AND gate 26.
36 at a high level.

AND gate 25.35 is set to low level to enable tristate buffer 28.38. The R/W signal is inverted through an inverter 29.

The circuit that enables the data bus 64 is (25 to 28.35
~38), up to the number of data buses 64 are required.

Also, at the falling edge of HACK, the output of the flip-flop 20 goes low and the Q output goes high through the inverter 40, enabling the address signal (161), AS signal (162), and R/W signal (163) of another processor 2. , data bus 164 is enabled by the level of the R/W signal. Tri-state buffer 121, 122, 123, 1
24° 127, 128, 137, 138, AND gates 125, 126, 135, 136, and inverter 129 operate as tristate buffers 21, 22,
23, 24, 27, 28, 37° 38, AND gate 2
5, 26, 35, 36, equal to inverter 29.

In FIG. 6, flip-flop 20. Inverter 4
It is also possible to make the main processor 1 on-chip and supply the signal line 41 or 42 to the outside. At this time, the high level of the signal line 41 indicates that the main processor 1 is the bus master, and the low level of the signal fi42 indicates that the other processor 2 is the bus master.

FIG. 7 shows a connection example when there are two or more separate processors that take bus authority for one main processor.
is input to HREQ of

The HACK output of main processor 1 is sent to another processor 2HAC.
HACK the next other processor 2' from the output of Kout
input to in.

In this embodiment, the main processor does not need to know how many separate processors are connected to it.

In the example of FIG. 7, the other processor that first learns that HACKin has been asserted becomes the bus master. That is, if another processor 2'2' asserts HREQ seven times at the same time, the other processor 2 will have priority right of bus ownership.

In addition, in the example of FIG. 7, if another processor is already the bus master, 1, for example, HACK
By disabling HREQ from being asserted when the in input is asserted, it is possible to configure the device so that it cannot become a new bus master.

FIG. 8 is a block diagram showing an example of a bus control circuit within the main processor that implements the timing charts of FIGS. 3 and 5. FIG. The bus control circuit is integrated on the main processor chip. The PLA 50 operates in synchronization with a clock 51 and implements a finite state machine 53 through a feedback bus 52 . The input of the state machine 53 is
These are the internal status signal 54 of the main processor and the 10th bit BIO5HREQ signal of the status register 55. The main processor's internal state signal 54 is a signal requesting memory access or the like. The first O bit of the status register is a bus transfer permission bit. When this bit is high, the processor relinquishes control of the bus. The bus transfer bit can be set low by an on-chip or off-chip interrupt or by the main processor's microprogram.

set or reset.

This signal is a HACK signal, and controls the bus while changing the state inside the state machine 53 according to input conditions and the feedback bus 52.

FIG. 9 is a timing chart showing a second embodiment according to the present invention. The system configuration is the same as that shown in FIG. The bus arbitration algorithm is the same as the flowchart shown in FIG. The only difference between FIG. 3 and FIG. 9 is the main processor output. In Figure 3,
The address signal was valid for 3.5 clocks, but
In the figure, it is valid only for two clocks. The AS signal is the third
In the figure, it is valid for 2.5 clocks, but in FIG. 9 it is valid only for 1 clock. In FIG. 3, the R/W signal was at a low level for 2.5 clocks, but in FIG. 9, it was at a low level only for 2 clocks. However, the bus arbitration methods in FIGS. 3 and 9 are equivalent. In other words, another processor asserts HREQ to request bus ownership, the main processor requests bus ownership, and another processor asserts HREQ.
By negating REQ, the main processor becomes the bus master again.

The flowchart in FIG. 4 is the same in the second embodiment as well.

The bus arbitration method shown in FIG. 5 works equally well for the main processor. Therefore, the addresses, AS, R of the main processor of the second embodiment as shown in FIG.
For the /W signal, there is also a bus arbitration method similar to that shown in FIG.

Control of the human output buffer in the second embodiment can be realized by the method shown in FIG. Further, an example of a system configuration in which a plurality of separate processors exist is the same as that shown in FIG. The hardware for realizing the sequence in FIG. 9 is the same as the circuit in FIG. 8, but the PLA lattice connection method (
The eyeball patterns) are different.

〔Effect of the invention〕

According to the present invention, even when another processor is the bus master,
The main processor can request bus ownership from another processor. Therefore, when a high-priority interrupt or exception handling occurs, for example, even during a DMA transfer in burst mode, it has the advantage of being able to acquire bus ownership and respond quickly, making it especially suitable for real-time systems. It is.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a microcomputer system explaining an embodiment of the bus arbitration method of the present invention, FIGS. 2 and 4 are operation flowcharts explaining an embodiment of the bus arbitration method of the present invention, and FIG. 3 and 5 are timing charts illustrating an embodiment of the bus arbitration method of the present invention, FIG. 6 is a circuit diagram of a human output buffer, and FIG. 7 is a microcomputer system block diagram of another embodiment. FIG. 8 is a circuit block diagram of the bus control circuit, and FIG. 9 is a timing chart illustrating another embodiment of the present invention. l: Main processor 2.2': Other processor 3 Near address bus 4: AS signal line (control bus) 5: R/W signal line (control bus) 6: Memory system 7: Input/output processor agent Patent attorney Ogawa Katsuo Figure 2

Claims (1)

[Scope of Claims] 1. A first processor having an input means for inputting an input signal ■■■■ requesting acquisition of bus rights, and an output means for outputting an output signal ■■■■ approving transfer of bus rights; In a system in which a second processor having an output means for outputting an output signal ■■■■ requesting acquisition of bus ownership and an input means for inputting an input signal ■■■■ approving transfer of bus ownership are connected on the same bus. , the second processor asserts ■■■■, and while the first processor asserts ■■■■ and the second processor holds the bus, the first processor asserts ■■■■. By negating ■, the second processor's ■■■■
1. A bus arbitration method comprising means for transferring bus rights to a first processor. 2. In the first processor which has the input signal ■■■■ requesting acquisition of the bus right and the output signal ■■■■ approving the transfer of the bus right, the second processor sets the ■■■■ to low level. At this time, depending on the value of the register inside the first processor, whether to transfer bus ownership by setting ■■■■ to low level, or to continue execution of the first processor with ■■■■ to high level. 2. A bus arbitration system according to claim 1, further comprising means for separating.