JP2007249942A - Interface device and image forming apparatus with the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide two-way transmission by an LVDS (Low Voltage Differential Signaling) of a parallel signal such as a CPU bus. <P>SOLUTION: This interface device is provided with a function block having: a parallel/serial conversion part 1 for converting a parallel signal into a single end signal; an LVDS driver 3 for converting the single end signal from the parallel/serial conversion part 1 into an LVDS output; an LVDS receiver 4 for converting the LVDS signal into a single end signal; and a serial/parallel conversion part 2 for converting the single end signal from the LVDS receiver 4 into a parallel signal, uses the parallel/serial conversion means 1 and the LVDS driver 3 for data transmission, and uses the LVDS receiver 4 and the serial/parallel conversion part 2 for data reception, wherein the function block is mounted on one package, and a transmission direction control signal 8 for switching a transmission direction function of the function block achieves two-way communication by the LVDS of a parallel signal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to bidirectional transmission of parallel signals such as a data bus, and more particularly to an interface device that realizes bidirectional transmission by LVDS (Low Voltage Differential Signaling) and an image forming apparatus including the interface device.

  In recent data communication systems, data transfer is performed by a bus. Since parallel signals such as this bus are arranged in parallel, the magnetic force generated by the current flowing through the signal destination. Interference with other signals causes unintended currents to flow due to electromagnetic induction, resulting in signal interference that causes malfunctions, signal delays that occur due to slight differences in wiring length, and the like.

  When long-distance transmission is performed using such parallel signals, an increase in signal lines (electric wires) due to measures such as inserting GND between signal lines to prevent signal interference, or signals due to resistance in the wiring path There is a possibility that signal misdetection due to waveform rounding or distortion, or delay between signals due to an increase in wiring length difference may occur. In order to solve such problems and problems, serial communication such as USB and IEEE 1394 is useful for long-distance transmission. However, these signals require a complicated protocol. Although problems such as signal delay do not occur, low-noise communication involving EMI (unwanted electromagnetic waves) is not necessarily good communication.

  Therefore, in order to realize long-distance communication with low noise, currently, two signal lines are used for one signal line, and subtraction is performed between the signal lines. There is a differential signal transmission method that cancels noise. Further, LVDS is a transmission system that inverts the phase of the two signal lines to halve the amplitude of the voltage and has a lower voltage and less noise. However, at present, the communication by LVDS is realized only in one direction, and there is no one that realizes bidirectional communication like a data bus.

  BLVDS (Bus LVDS), which converts a large number of signal lines such as buses into LVDS, has been put to practical use, but a single transmission line can only communicate in one direction, and both can be used as LVDS devices. There are some that realize the direction, but this is prepared for each signal direction, and it is only that that realizes communication with many signal lines such as buses using this. Devices and communication wires are required, resulting in high costs. Of course, it is impossible to transmit an existing bus form signal such as a CPU bus by LVDS, and if it is to be realized, an address bus and other control signals are required in addition to the bidirectional transmission of the data bus. Further cost increases.

  First, the current communication mode in a copier to which the interface apparatus according to the first embodiment is applied will be described. Taking a large copying machine such as a wide-width machine as an example, for example, a signal is sent over a long distance from a PCB (printed circuit board) on which a CPU is mounted to each control load. A copying machine generally includes a reading unit, a writing unit, a main control unit, a transfer paper feeding unit, and the like. For example, a reading unit detects a wide document size. If sensors are required, and if it is intended to detect the document widths of A4, A3, A2, A1, A0, B4, B3, B2, and B1, at least the number of document sizes, for example, nine sensors are required. become.

  Here, if nine sensors are to be controlled from the main control unit, the sensor requires at least three signal lines for the drive power supply and signals, and a total of 27 signal lines (electric wires) over a long distance. Will crawl around. Naturally, since it is necessary to control many loads in each unit, a considerable number of wires run around the entire machine (copier). When such a harness is wound around, a great problem arises from the viewpoint of noise, and assembling the harness to a machine is not easy to work, and leads to an increase in cost due to the number of wires.

  Therefore, as a method of reducing the number of signal lines, if each unit is provided with a PCB that transmits and receives signals by serial communication or the like with the main control board, the control load in the unit is controlled by the PCB. Since the line is only in the unit, the function can be achieved without running over a long distance, and the main control PCB and the PCB of each unit need only a few signal lines used for serial communication. It is possible to improve the workability of scooping while reducing the number of harnesses.

  However, with such a configuration, the signal lines are certainly reduced, but it is necessary to mount a CPU separately from the main control PCB on the PCB mounted on each unit, which increases the software development man-hours. And timing verification by serial communication becomes an issue. Here, if an IC operating on the CPU bus is mounted on the PCB mounted on each unit, and the PCB of each unit is controlled from the main control PCB by parallel communication using the CPU bus, the software required for each unit Although the number of man-hours required for development can be reduced, there are concerns about problems such as malfunction due to signal line distortion due to noise and generation of electromagnetic waves related to EMI.

  By the way, in the conventional bi-directional communication by LVDS as an interface standard for transmitting differential signals, when two signal lines are used, it is necessary to perform termination processing on the receiver side. Are provided, and from the viewpoint of signal reflection due to mismatching of these termination resistors, resistance switching control for invalidating one termination resistor has been performed.

  In addition, conventional LVDS communication uses a bidirectional communication package in which LVDS signal lines are separated as shown in FIG. 9 or a bus signal such as BusLVDS as shown in FIG. 10 is converted into LVDS. Thus, a configuration in which communication is performed point-to-point has been used. With respect to the method of FIG. 9, when there are many signal lines such as bus lines, these configurations use a plurality of packages, which is expensive, and is mounted on a PCB board (printed circuit board). We needed a lot of area. The method of FIG. 10 can connect bus signals with a small number of LVDS signal lines and enables LVDS connection of bus signals. However, there is no bidirectional communication and only one-way communication. If two-way communication is to be realized using the BusLVDS, a plurality of packages are required as in the configuration of FIG.

  Therefore, for example, Patent Document 1 proposes a method that enables communication in the reverse direction with respect to an interface that performs unidirectional communication with LVDS. According to this, bidirectional communication is performed by using a single-ended signal (not a differential signal, a normal signal based on 0V: 5V, 3.3V, etc.) slower than LVDS for communication in the reverse direction. Is realized. In other words, communication in one direction via two signal lines is transmitted using a differential signal, but signal transmission in the reverse direction is performed using a single-ended signal for signal transmission requiring high speed. Uses a differential signal, and performs transmission using a single-ended signal when low speed is acceptable.

Further, as a conventional technology for an interface that enables high-speed data transfer without requiring a special decompression device, for example, Patent Document 2 can be cited. According to this patent document 2, the interface between the printer controller and the printer engine comprises a control line capable of communicating both types of control signals and a data line for transmitting image data from the controller to the engine. Since there is no need to exchange control signals between image data transmissions, high-speed image data transmission is possible.
JP 2005-18312 A JP 2002-254663 A

  However, the above cited reference 1 does not realize the bidirectional communication of the LVDS itself, but uses the single-ended signal to implement the LVDS one-way communication and realize the communication in the opposite direction. In this case, the signal (single-ended signal) at the time of communication opposite to the direction of communication by LVDS is limited in speed and signal type, and noise is also generated. . In particular, bi-directional communication cannot be used for signals such as a data bus, and when performing communication in the opposite direction to LVDS, it is limited to the case of communicating auxiliary signals. Also, in the cited document 2, only one-way communication of image data is performed using a data line.

  The object of the present invention is to convert a signal that requires bi-directional communication using a large number of signals (parallel signals) such as a data bus into a serial signal and realize bi-directional transmission using LVDS for long-distance transmission with low noise. It is an object of the present invention to provide an interface device and an image forming apparatus capable of realizing the above.

In order to solve the above problems, the present invention mainly adopts the following configuration.
A parallel / serial conversion unit that converts an input parallel signal into a single-end signal, an LVDS driver that converts a single-end signal from the parallel / serial conversion unit into an LVDS output, and an input LVDS signal into a single-end signal It comprises a functional block having an LVDS receiver for conversion and a parallel / serial conversion unit for converting a single-ended signal from the LVDS receiver into a parallel signal, and data transmission uses the parallel / serial conversion unit and the LVDS driver, For data reception, the LVDS receiver and the serial / parallel converter are used, the functional block is mounted in one package, and the transmission direction function of the functional block is switched to perform bidirectional communication of the parallel signal by LVDS. Structure To.

  In the interface device, a plurality of functional blocks are mounted on the one package, the transmission direction function can be set for each functional block, and a CPU bus is connected to one functional block among the plurality of functional blocks. In addition, the transmission direction function is set so that the other functional blocks function for data transmission.

  According to the present invention, it is possible to realize bi-directional transmission of parallel signals by LVDS, thereby achieving low-noise long-distance transmission and cost reduction by integrating packages.

  In addition, it is possible to realize an existing bus system such as a CPU bus by making it possible to set functional blocks for realizing bidirectional transmission of LVDS not only in bidirectional but also in one-way transmission. .

  Embodiments of the present invention will be described below with reference to the drawings.

  1 to 8 illustrate an interface device according to a first embodiment of the present invention.

  FIG. 1 is a diagram illustrating an internal circuit of the interface apparatus according to the first embodiment of the present invention. FIG. 2 is a diagram illustrating an example of inversion states of transmission direction control signals on the transmission side and the reception side in LVDS transmission according to the first embodiment. FIG. 3 is a diagram illustrating another example of the inverted state of the transmission direction control signal on the transmission side and the reception side in the LVDS transmission according to the first embodiment. FIG. 4 is a diagram illustrating a related configuration of functional blocks and packages in the interface apparatus according to the first embodiment.

  FIG. 5 is a diagram illustrating a configuration example when the CPU bus is used in the interface apparatus according to the first embodiment. FIG. 6 is a diagram illustrating a method of creating and using a transmission direction control signal as an operation example when the CPU bus is used in the interface apparatus according to the first embodiment. FIG. 7 is a diagram for explaining an operation example when the CPU bus is used in the interface apparatus according to the first embodiment. FIG. 8 is a diagram illustrating a configuration in which the bidirectional LVDS device in the interface apparatus according to the first embodiment is fixed to the function of either the driver or the receiver, and the transmission direction of the functional block is switched as necessary.

  An interface apparatus according to Embodiment 1 of the present invention will be described with reference to FIG. FIG. 1 is a diagram illustrating an internal circuit of the interface apparatus according to the first embodiment of the present invention. In FIG. 1, 1 is a parallel / serial converter, 2 is a serial / parallel converter, 3 is an LVDS driver, 4 is an LVDS receiver, 5 is a PLL, 6 is bidirectional data, 7 is LVDSI / F, and 8 is a transmission direction. A control signal 9 represents a clock.

  FIG. 1 shows an internal circuit for realizing bi-directional communication by LVDS, and transmitted data 6 is first input to the parallel / serial converter 1. The parallel / serial converter 1 shifts data to a register for serial data transfer according to the clock multiplied by the PLL 5. The shifted data is input to the LVDS driver 3 and output as an LVDS signal through the LVDSI / F7. When inputting an LVDS signal, the signal sent by LVDS through the LVDSI / F7 is received by the LVDS receiver 4 and the signal is input to the serial / parallel converter 2 and converted. The processed data is output as parallel data 6.

  As shown in FIG. 2, a transmission direction control signal 8 for switching a signal transmission direction is input to each element (parallel / serial conversion unit 1, serial / parallel conversion unit 2, LVDS driver 3, and LVDS receiver 4). If the control signal 8 is H, the LVDS data transmission unit 11 is active. If the control signal 8 is L, the LVDS data reception unit 12 is active.

  Here, in FIG. 1, the LVDS driver 3 converts an input single-ended signal into LVDS outputs (two signals in opposite directions). The LVDS receiver 4 converts an input LVDS signal (two signals having opposite directions) into a single-ended signal. The parallel / serial converter 1 temporarily shifts input parallel data to a register, and performs parallel / serial conversion by sending data sequentially from the first bit of the register.

  The same applies to converting input serial data into parallel data. Stocked data is stored in a register from the beginning, and if all the data is stored, it is transferred to a port output register. The function of the / parallel converter 2 is fulfilled. These conversion units 1 and 2 can be switched according to their respective applications, and this switching is performed by a transmission direction control signal 8.

  The transmission direction control signal 8 is a signal for controlling the bidirectional transmission direction. Since the data transmission direction has the parallel / serial conversion unit 1 and the LVDS driver 3 as functional blocks, and conversely, the data reception direction has the serial / parallel conversion unit 4 and the LVDS receiver 2. This function needs to be switched depending on the signal transmission direction, and the transmission direction control signal 8 is used as the enable signal.

  The transmission direction control signal 8 may be output from the port as a separate signal at the start of data communication, or a control signal such as read / write used for CPU bus control may be used. Further, when used in one-way transmission, the level of the driver / receiver control signal is fixed by a function that uses it.

  Incidentally, an interface device according to the prior art will be described with reference to FIGS. 14 and 15 in comparison with the two-way communication by LVDS shown in FIG. 1 (Embodiment 1 of the present invention). FIG. 14 shows an example of a LVDS two-way communication package in which the LVDS signal lines are separated, and each has a LVDS driver 3 and a receiver 4 for transmission and reception. With one wire, the signal direction is There is only one direction. FIG. 15 shows the internal configuration of the bus LVDS, which is configured to output the LVDS by the LVDS driver 3 through the parallel / serial converter 1 that converts parallel data into serial data. The signal direction is only one direction. In this case, when receiving a signal in the reverse direction, another receiving package is required.

  The interface device according to the first embodiment of the present invention shown in FIG. 1 is not limited to a copying machine, but can be used as long as it is a device that performs long-distance transmission of LVDS parallel signals. In the first embodiment, A copier is taken as an application example. Next, an outline of a copying machine to which the interface apparatus according to the first embodiment is applied will be described. A copying machine generally includes a reading unit, an image processing unit, a controller, an image data arrangement unit, and a writing unit.

  The reading unit is a portion for reading a document. As a method for reading a document, there are a document reading method using a CCD and a method of reading a document while conveying the document using a contact sensor or the like. The image processing unit performs image processing on the image read by the reading unit. The image processing unit includes a plurality of processors, and each processor performs necessary image processing. Image processing functions include shading correction and background removal.

  The controller also controls the output timing of image data in the image system. The controller has a plurality of processors and storage means such as a memory and these are connected to each other. Image data that has undergone image processing is temporarily stored in a storage means such as a hard disk of the controller. In accordance with the output timing of each image data, necessary data is taken out and transferred to the image data arrangement unit.

  The image data placement unit has a line memory corresponding to the image writing width. Data transferred from the controller to this line memory is arranged according to the image area. The memory is a FIFO, and the arranged data is sent to the write control unit in order from the top. The writing unit is a part that performs an image writing operation, and includes an optical device such as an LD for performing image writing and a driver IC for driving the optical device. The optical device is driven (flashing operation) in accordance with the transferred data, and a writing operation is performed. As will be described later, the CPU is taken up as an example for inputting and outputting the parallel signals illustrated in FIGS. 5 and 7. However, this CPU does not correspond to the controller (for processing image data) described above. The main controller that controls the entire copying machine.

  Next, the outline of the operation of the copying machine as an application example of the first embodiment will be described. An image read by a reading device such as a scanner is converted into digital data, and the data is transferred to an image processing unit. Data for which various types of image processing have been completed is transferred to a controller that controls the system, where it is temporarily stored in storage means such as a hard disk. After that, the data is arranged in the line memory according to the conditions such as the number of copies, the mode, etc., transferred to the writing section as image writing data, and LD is applied to the transfer paper conveyed from the transfer paper stock means such as a cassette in accordance with the writing timing. The writing operation is performed by an optical device such as Such an operation of the copying machine is a general normal operation.

  First, generally speaking, the interface device according to the first embodiment illustrated in FIG. 1 converts a bidirectional parallel signal into a serial signal and transmits the signal by LVDS. With regard to the above, even if a parallel signal having many signal lines such as a data bus is transmitted over a long distance, communication with low noise and high reliability is possible. Further, since bidirectional parallel signal communication is realized by a single package (since it is equipped with components for transmission and reception), the cost can be reduced and the mounting area can be reduced. Further, when the interface apparatus according to the first embodiment is mounted on a copying machine, the functions of bidirectional transmission and unidirectional transmission are selected or fixed (details will be described later, but the transmission direction control signal It is possible to use an existing bus such as a CPU bus, and the space can be saved and the cost can be reduced by accommodating it in one package. Since the parallel signal is serialized, the number of harness lines can be reduced. Software development load is reduced.

  As shown in FIG. 1, the transmission direction control signal 8 switches the transmission direction (transmission direction and reception direction) of LVDS, but the transmission direction is controlled by the signal level. In the transmission side block 11 (see FIG. 2), it is necessary to input signals of different levels. Therefore, as shown in FIG. 2, for example, a signal is input to the other PCB 12 separately from the LVDS signal, and the signal is inverted by the inverting unit 10 shown in FIG. 2 and supplied as a transmission direction control signal. This makes it possible to clarify the data transmission side block 11 and reception side block 12 when transmitting a signal. FIG. 2 is a diagram illustrating inversion states of transmission direction control signals in the transmission side block 11 and the reception side block 12 in LVDS transmission according to the first embodiment.

  Also, as shown in FIG. 3, if a fixed level signal is input to the transmission direction control signal, it can be fixed to either the LVDS transmission / reception function inside the package. It is possible to use only for drivers and receivers. In FIG. 3, the transmission control signal is grounded in the reception side block 12, and a predetermined value is applied as the transmission control signal in the transmission side block 11. As can be seen from the configuration shown in FIG. 2 and FIG. 3, the transmission side block 11 and the reception side block 12 are one common package (the circuit configuration in the solid line frame in the figure), and the settings of the driver and the receiver are appropriately set. Selectable. The transmission side block 11 and the reception side block 12 are switched as appropriate.

  Next, a related configuration of the functional block and the package in the interface apparatus according to the first embodiment will be described with reference to FIG. As shown in FIG. 4, the configuration including the parallel / serial conversion unit 1, the serial / parallel conversion unit 2, the LVDS driver 3, the LVDS receiver 4, the LVDSI / F7, etc. is integrated into the first to third functions. Blocks BA, BB, and BC are used, and a plurality of these first to third functional blocks BA, BB, and BC are collected and stored in one package P.

  The first to third functional blocks BA, BB, and BC can be controlled independently, and the transmission direction of the signal can be set according to the function by the transmission direction control signal 8 or the like. Further, by controlling the enable signal EN as shown in each functional block BA, BB, BC (by applying a normal method), unnecessary functional blocks can be set to be inoperable. .

  Next, a configuration example when the CPU bus is used in the interface apparatus according to the first embodiment will be described with reference to FIG. As shown in FIG. 5, the CPU bus 22 communicates with an address bus 22a, a data bus 22b, and control signals (read signal, write signal, chip select signal, etc.) 22c. Allocation is performed for each third functional block BA, BB, BC. For example, since the data bus 22b is bidirectional communication, the third functional block BC is used for LVDS bidirectional transmission, and the address bus 22a and the control signal 22c are unidirectional communication from the CPU 21 side. The second functional blocks BA and BB may be set as LVDS drivers. Of course, it is necessary to perform the above-described setting also on the PCB on the other side that receives the signal. The first and second functional blocks BA and BB are used as receivers, and the third functional block BC is transmitted bidirectionally. Use as

  Next, an operation example when the CPU bus is used in the interface apparatus according to the first embodiment will be described with reference to FIG. As shown in FIG. 7, the PCB on which the CPU 21 is mounted is referred to as PCB1, and the PCB that is controlled by the CPU is referred to as PCB2.

  The CPU bus 22 performs writing (writing) of data from the CPU 21 of the PCB 1 to the device 23 of the PCB 2 and reading (reading) of receiving data from the other side. Since transmission is performed in the direction, PCB1 simply functions as an LVDS driver and PCB2 functions as an LVDS receiver. Further, at the time of reading, it is necessary to perform an operation in which the CPU 21 sends a command to the counterpart device 23 and the CPU 21 receives data returned in response thereto.

  As a method for realizing the above-described operation, when a read operation is performed, first, the transmission direction control signal 8 of the data bus 22b is input simultaneously when the address and the control signal are transmitted to the PCB 2, and the transmission direction of the data bus 22b is determined. do it. By this transmission direction control signal 8, the third functional block BC is set to the data reception function (LVDS reception function) and can receive data.

  A method for creating and using a transmission direction control signal will be described with reference to FIG. 6 as an operation example when the CPU bus is used in the interface apparatus according to the first embodiment. In FIG. 6, if a signal 8a obtained by ANDing a read signal (a signal when the CPU instructs to read and an L level signal) and, for example, an H signal is input to the transmission direction control signal terminal, communication is performed. Since the read signal is at the H level when writing is not performed or at the time of writing (because it is not when reading is instructed), the output of the AND circuit 8b is at the H level, and the third function block BC is driven by the driver. Set it to. Since the transmission direction control signal becomes L only when a read signal is input, LVDS can be set as a reception function. Thereby, it becomes possible to control only by the signal level of the read signal without separately outputting the transmission direction control signal 8 from the port.

  The CPU bus 22 has a predetermined timing between signals in order to capture data reliably. However, after the read signal (L level signal) is output, the data is captured to some extent. There is no problem in detecting the transmission direction control signal.

  Next, a configuration in which the bidirectional LVDS device in the interface apparatus according to the first embodiment is fixed to a function of either a driver or a receiver and the transmission direction of the functional block is switched as necessary with reference to FIG. explain.

  In the case of the CPU bus, since a control signal is output from the CPU side PCB, the CPU side PCB is set as a so-called master, and the level of the transmission direction control signal is switched according to the transmission direction, so that the transmission of the counterpart PCB (PCB2). The direction can be controlled.

  For example, as shown in FIG. 14, by setting the driver / receiver setting terminal to H (for example, voltage application) on PCB1 and to L (for example, ground) on PCB2, the functions of the bidirectional LVDS device are set to the driver and receiver, respectively. can do. Next, regarding the transmission direction control, as described in FIG. 2, it is necessary to invert the logic of the transmission direction control signal 8 on the driver side and the receiver side.

  Here, the driver side (the PCB 1 on the left side in the example of FIG. 8) transmits with the transmission direction control signal being H (the transmission direction control signal is H for writing, L for reading, for example). Depending on the signal level of the receiver setting terminal 8c (in this case, H), the signal logic selection function unit (selects the input signal from the driver / receiver setting terminal 8c depending on whether the transmission direction control signal 8 is H or L). The second wire W2 is connected as an input to the function block B in 8d) having the function of selecting any output of the functions. Similarly, on the receiver side (PCB2), the wire is selected according to the level of the driver / receiver setting terminal (in this case, L). However, since the level signal is L on the receiver side, the first wire W1 is selected. Thereby, the logic level of the transmission direction control signal 8 is opposite between the driver side and the receiver side.

  Also, setting (fixing) the driver / receiver (interface device) means that the direction of the signal when the transmission direction control signal is sent to the other side must also be determined, and the driver / receiver setting terminal 8c The input / output can be selected in the same manner by the input / output selection function unit 8e according to the level (voltage application H or ground L). In the example described above, the driver side is set to output, and the receiver side is set to input. The point is that the function block of PCB1 is selected as either a transmission function or a reception function according to H or L of the transmission direction control signal 8, and at the same time, the function block of PCB2 is selected as a function opposite to that of PCB1. For example, the structure shown in FIG.

  By controlling a block such as the data bus 22b that requires a bidirectional function with the above-described circuit and a transmission direction control signal, it is possible to switch between the transmission and reception functions for communication. For example, in the case of light, by setting the transmission direction control signal 8 to H, the driver side controls the function block as it is because the second wire W2 is connected. become. On the other hand, on the receiver side, since the input transmission direction control signal is set in the receiver and is input to the functional block through the first wire W1, the signal level is L, and the functional block B is received. Will work. In the case of reading, only the transmission direction control signal described above becomes L, and the rest is the same.

  Here, the features of the interface apparatus according to the first embodiment of the present invention will be summarized and described again. In the prior art, a bus line such as the bus LVDS can be converted into an LVDS serial signal, but bidirectional communication is not realized by only one-way communication. There are ICs that have realized two-way communication, but this has converted the signal lines in each direction to LVDS, making it possible to convert the serial signal as it is to LVDS for communication. However, only one direction of signal flows through one signal line. In addition, serial communication such as USB is used for long-distance transmission, but it is not resistant to noise, and there are still problems with respect to communication speed and processing speed.

  Therefore, in the first embodiment of the present invention, the realization of bi-directional transmission of parallel signals by LVDS is a problem to be solved. With the configuration for achieving this problem, low-noise long-distance transmission and cost of package integration are achieved. In addition to existing buses such as CPU buses, the function blocks for realizing LVDS bi-directional transmission can be set not only in bi-directional but also in one-way transmission. It can be applied to the system. As a configuration for achieving this problem, a combination of a parallel / serial conversion unit and an LVDS driver for data transmission and a serial / parallel conversion unit and an LVDS receiver for data reception is mounted as a functional block in one package. By switching functions according to the application, bi-directional transmission of parallel signals such as a data bus by LVDS is realized. In addition, a communication mode in which one-way transmission and two-way transmission such as a CPU bus are mixed by incorporating a plurality of these functional blocks in one package and enabling setting and fixing of two-way transmission and one-way transmission. The communication can also be made possible.

An example in which the first embodiment is applied to a copying machine will be specifically described as a second embodiment.
FIG. 9 is a diagram showing an outline of the mechanical configuration of the copying machine according to the second embodiment, and FIG. 10 is a block diagram showing the main part of the control configuration. The copier according to the present embodiment includes a main body unit 100, a paper feeding unit 110, a reading unit 120, and an automatic document feeder (ADF) 130. The main body unit 100 is positioned above the paper feeding unit 110, and the reading unit 120 is positioned above the main body unit 100. Further, an ADF 130 is provided above the reading unit 120.

  The copying machine according to the present embodiment forms an image by an electrophotographic method, and a main body unit 100 is provided with a photoconductor 101, a fixing device 102, a duplex device 103, and a paper discharge device 104. A charging unit 105, a developing unit 106, a transfer unit 107, a cleaning unit 108, and a static elimination unit (not shown) are disposed on the outer periphery of the photoconductor 101. The main body 100 is provided with a writing unit 109 for writing. The writing unit 109 includes an optical device such as an LD for writing an image and a driver IC for driving the optical device. The writing unit 109 drives (flashes) the optical device in accordance with the transferred data, and a photoconductor. An optical writing operation is performed on 101.

  The paper feeding unit 110 has five paper feeding stages 111, 112, 113, 114, and 115, which are sent from the designated paper feeding stage through the paper feeding roller to the transfer unit 107 from the vertical conveyance path 116, and are written in. 109 is written on the surface of the photoconductor 101 to form an electrostatic latent image. The reading unit 120 optically reads the document placed on the contact glass in the sub-scanning direction or the document conveyed by the ADF 130 with the traveling body stopped. The former is generally called a flat bed system, and the latter is generally called a sheet through system. Reading by the flat bed method is performed, for example, in the case of a book document, and reading by the sheet-through method is performed, for example, in the case of a plurality of sheet documents. In this embodiment, the ADF 130 is a circulation type automatic document feeder that can also reversely read a document, also referred to as ARDF.

  Furthermore, as shown in FIG. 10, an image data processing unit 200 that handles image data, and an engine control unit 300 that is responsible for overall machine control such as paper conveyance timing are provided.

  The image data processing unit 200 includes an image processing unit 210, a controller 220, an image data arrangement unit 230, an operation unit 240, and a storage device (HDD) 250. The image processing unit 210 includes a plurality of processors. The image data read by the reading unit 120 and converted into digital data is input. Necessary for writing shading correction, background removal, and other images by each processor. Image processing is performed.

  The controller 220 includes a plurality of processors and controls the output timing of image data in the image system. Image data that has undergone image processing is temporarily stored in a storage device (HDD) 250. It should be noted that it may be stored in a memory inside the controller instead of the HDD 250. The controller 220 retrieves necessary data from the HDD 250 according to the output timing of each image data, and transfers it to the data arrangement unit 230. The image data arrangement unit 230 has a line memory corresponding to the image writing width, and data transferred from the controller 220 is arranged in this line memory in accordance with the image area. The memory is a FIFO, and the arranged data is sent to the write control unit in order from the top.

  The operation unit 240 is a user interface, and is provided with a hard key, a soft key, and a display, and an instruction input from the user and a display for the user are performed.

  The engine control unit 300 includes a main control PCB 310 and first and second unit control PCBs 320 and 330 connected to the main control PCB 310 via the first and second LVDS 301 and 302 for each unit. . The main control PCB 310 includes a CPU 311 and first and second bidirectional LVDS devices 312 and 313, and the first and second bidirectional LVDS devices 312 and 313 are connected to the CPU 311 via the CPU bus 314. The first bidirectional LVDS device 312 is connected to the first unit control PCB 320 via the first LVDS 301, and the second bidirectional LVDS device 313 is connected to the second unit control PCB 330 via the second LVDS 302. Are connected to each. The second embodiment is an example in which the LVDS bidirectional communication of the first embodiment is applied to a CPU bus to control a plurality of units at a long distance. In this example, the paper transport timing of the copying machine is used. This is applied to an engine control unit 300 that handles a part related to the overall machine control.

  That is, the main control PCB 310 is connected to various load interface boards and drive boards, and read / write controls. A CPU bus 314 is output from the CPU 311. When the CPU bus 314 outputs to the unit control PCBs 320 and 330, the bidirectional LDVS devices 312 and 313 for realizing the above-described bidirectional transmission of LVDS as described above. And connected to the unit control PCBs 320 and 330. Connection with the bidirectional LDVS devices 312 and 313 is performed by a connector.

  The first unit control PCB 320 includes first and second control ICs 321 and 322, and bidirectionally communicates with the main control PCB 310 via the first LVDS 301 by the bidirectional LVDS device 324 connected to the CPU bus 323. Do. For example, a motor 321a, sensors 321b, 321c, and the like are connected to the first control IC 321, and a clutch 322a, sensors 322b, 322c, and the like are connected to the second control IC 322, for example.

  The third unit control PCB 330 includes a control IC 331 and performs bidirectional communication with the main control PCB 310 via the second LVDS 302 by the bidirectional LDVS device 333 connected to the CPU bus 332. For example, a clutch 331a, sensors 331b, 331c, and the like are connected to the second control IC 331.

  In general, the unit control PCBs 320 and 330 receive the CPU bus 314 by the LVDS devices 324 and 333 in the same manner as the main control PCB 310, convert them into parallel CPU buses 323 and 332, and control ICs 321. , 322, 331. These control ICs 321, 322, and 331 are ICs controlled by the CPU buses 323 and 333, and are ICs that passively operate in response to commands from the CPU 311, such as IO expansion ICs. These ICs are widely used, and the CPU buses 323 and 332 access the allocated address space and control the respective ports accordingly. Therefore, central control from the CPU 311 is possible.

  Further, the CPU buses 314, 323, and 332 can control a plurality of devices by a select signal. For example, if there are three select signals, the two are arranged at optimal positions for connection to the control load. One IOB may be allocated to a read-related IO control PCB.

  In the IO control related to reading, for example, a plurality of sensors necessary for detecting the document size are temporarily input to the port of the IO expansion IC, and the CPU 311 controls the IO expansion IC to obtain sensor information. Thus, only the signal line of the CPU bus obtained by converting the signal line necessary for each sensor into the LVDS serial can be obtained.

  In addition, the first and second unit control PCBs 320 and 330 controlled by the CPU 311 (BCU-Bus Control Unit) of the main control PCB 310 are arranged at optimal positions with respect to the load to which the unit control PCBs 320 and 330 are connected. can do. In other words, the first and second unit control PCBs 320 and 330 controlled by the main control PCB 310 can be arranged at optimal positions that minimize the connection load turning.

  For example, the unit control PCB that performs control related to reading may be arranged in the reading unit 120, and when the sheet feeding unit 110 is to be controlled, the connection with the load controlled by the unit control PCB is minimized. The unit control PCB may be arranged at the position of the paper feeding unit 110. For example, assuming that the control load of the paper feeding unit 110 is concentrated in the lower left as viewed from the rear of the machine, they are currently scooped over a long distance, but in this configuration, unit control is performed around the lower left of the machine. By arranging the PCB, the connection with the control load by the harness can be minimized. Further, since the connection to the main control PCB 310 is only the LVDS cable, it can be easily wound.

  When the control load of the first and second unit control PCBs 320 and 330 is large, there is a possibility that a plurality of control ICs (in particular, IO expansion ICs here) are mounted like the first unit control PCB 320. However, the main control PCB 310 and the control-side PCB (first and second unit control PCBs 320 and 330) need only be connected by an LVDS cable that connects the CPU bus.

  FIG. 11 is an enlarged view of the first unit control PCB 320 which is the control side PCB, for example, there are many connection loads (sensors, clutches, etc.) of the control side PCB, both input and output, and a plurality of IO expansion ICs. If necessary, the CPU bus 323 received by the LVDS bidirectional device 324 and converted into a parallel bus as shown in FIG. 11 may be branched as it is and connected to a plurality of IO expansion ICs. There is no problem if a plurality of select signals are transmitted when they are output from the main control PCB 310.

  For example, as described above, the CPU bus 323 is composed of an address bus 351, a data bus 352, and various control signals. When two IO expansion ICs are to be controlled, this control signal includes a read signal. The first select signal 352-1 and the second select signal 352-2 may be transmitted together with the signal 352r and the write signal 352w, and the select signals 352-1 and 352-1 are transmitted to the control side PCB (first unit control PCB 320). The IO expansion ICs (in this embodiment, the first control IC 321 and the second control IC 322) may be distributed.

  In addition, a signal with severe timing such as an interrupt may be transmitted as it is without being converted into LVDS. FIG. 12 is a diagram showing a configuration for transmitting as it is without converting to LVDS. Regardless of whether it is a copier or another device, the concept of interrupt is often used as the overall system control. There are two types of interrupts: internal interrupts used inside the program and external interrupts that perform interrupt operations in response to external signals. The example of FIG. 12 relates to external interrupts, and the second unit of FIG. This corresponds to the configuration of the control PCB 320.

  In the process from the paper transport process of the copying machine to the execution of the image writing operation, the timing for writing the image is very severe, and if this timing is shifted, the margin width from the leading edge of the paper to the image changes. The effects such as will come out. In order to prevent this, the sensor confirms that the paper has arrived in order to indicate the position when the leading edge of the paper has reached before the writing of the image process. This sensor (hereinafter referred to as a registration sensor) 322r (see FIG. 9). Is input to the CPU 311 by an external interrupt, so that an operation for preferentially confirming the position of the leading edge of the sheet on the program is performed and the operation of the next image writing process is started.

  If the registration sensor 322r is input from the position shown in FIG. 9 to the second unit control PCB 320 as shown in FIG. 12, it is input to the port of the IO expansion IC 322 in the second unit control PCB 320. Will be. The IO expansion IC 322 also has an interrupt port, and the signal input here is further output to the main control PCB 310 as an interrupt signal from the IO expansion signal. If this interrupt signal is not converted to LVDS, it is converted to LVDS. The transmission time can be transmitted to the main control PCB 310 without causing the delay time to be a problem. If there are several signal lines for interrupts or the like, a large current does not flow, so there is no problem with malfunction or noise. Further, as indicated by reference numeral 322r ', the output of the registration sensor may be transmitted as it is to the CPU 311 of the main control PCB 310 (PCB1) without using the interrupt port of the IO expansion IC 322 (reference numeral 325). At that time, if the signal is assigned to the remaining pins of the connector of the LVDS cable of the CPU bus 323, it can be turned around without requiring a separate harness.

  If centralized control that simplifies the power supply startup sequence by the CPU bus is realized as described above, the design of the main power supply startup sequence can be simplified.

  Normally, when the main power is turned on, the CPU initializes the CPU by inputting a reset signal to the CPU to prevent malfunction, and when the power is turned off, the voltage is intentionally set to 0 V when the voltage drops to a certain voltage, and the voltage is Prevents malfunction in the stable region. When there are a plurality of CPUs in the system, the power supply rise / fall sequence must be designed in consideration of the specifications of each CPU. This is to cope with, for example, a communication error in which another CPU must be started before the CPU mounted on the BCU is started, or another CPU has to be started later. It is.

  By setting the timing to the central control from the CPU 311 of the main control PCB 310, even if a reset must be input to the other IO expansion ICs 321, 322, 331, etc., the timing with the CPU 311 of the main control PCB 310 is taken into consideration. It's just a story. FIG. 13 is a timing chart showing the timing relationship with the main power source of the 5V power source S5v, the CPU power source SCPU and the control IC power source SIC. For example, as shown in FIG. 13, if the IO expansion IC 321 must be started before the CPU 311 of the main control PCB 310, for example, if the reset time of the CPU 311 is set to 100 ms, the other ICs 322 and 331 have specifications of each IC. It is sufficient to set a reset time (for example, 50 ms, etc.) that satisfies the above and rises earlier. That is, it is only necessary to reset at any timing of the reset period Tr as shown in FIG.

Thus, according to the present embodiment,
1) Since the configuration in which bidirectional parallel signals are converted into serial signals and transmitted by LVDS is applied to a copying machine, or more broadly, an image forming apparatus, the functions of bidirectional transmission and unidirectional transmission can be selected and fixed. It becomes possible, and connection by existing buses such as a CPU bus becomes possible.
2) Space-saving and cost reduction can be achieved by putting it in one package.
3) Since the parallel signal is converted into a serial signal and transmitted, the number of harness lines can be reduced.
4) Since a plurality of units or devices can be controlled using the CPU bus, central control from the main control PCB is possible.
5) Since central control from the main control PCB is possible, it is possible to reduce the software development man-hours of the control IC (CPU, FPGA, etc.) mounted in each unit and to simplify the overall system configuration. .
6) Since it is possible to reduce the number of software development steps and simplify the configuration of the entire system, timing design and various sequences are facilitated.
7) Since the software development load can be reduced and the number of man-hours required for harnessing can be reduced, the cost of the entire system can be reduced.
There are effects such as.

It is a figure which shows the internal circuit of the interface apparatus which concerns on Example 1 of this invention. 6 is a diagram illustrating an example of inversion states of transmission direction control signals on a transmission side and a reception side in LVDS transmission according to Embodiment 1. FIG. FIG. 10 is a diagram illustrating another example of the inverted state of the transmission direction control signal on the transmission side and the reception side in the LVDS transmission according to the first embodiment. It is a figure which shows the related structure of the functional block and package in the interface apparatus which concerns on Example 1. FIG. It is a figure which shows the structural example at the time of using CPU bus | bath in the interface apparatus which concerns on Example 1. FIG. It is a figure which shows the preparation and usage method of a transmission direction control signal as an operation example at the time of using CPU bus | bath in the interface apparatus which concerns on Example 1. FIG. FIG. 10 is a diagram illustrating an operation example when a CPU bus is used in the interface apparatus according to the first embodiment. It is a figure which shows the structure which fixes the bidirectional | two-way LVDS device in the function of either a driver or a receiver in the interface apparatus which concerns on Example 1, and switches the transmission direction of a functional block as needed. FIG. 4 is a diagram illustrating an outline of a machine configuration of a copying machine according to a second embodiment. FIG. 6 is a block diagram illustrating a main part of a control configuration of a copier according to a second embodiment. FIG. 6 is an enlarged block diagram illustrating a second unit control PCB that is a control-side PCB in Embodiment 2. It is a figure which shows the structure which transmits as it is, without converting into LVDS in Example 2. FIG. It is a timing chart which shows the timing relationship with the main power supply of 5V power supply, CPU power supply U, and control IC power supply. It is the communication by LVDS regarding a prior art, Comprising: It is a block diagram which performs two-way communication by the signal line provided separately. It is a block diagram which converts a bus signal like BusLVDS regarding a prior art into LVDS, and performs one-way communication.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Parallel / serial conversion part 2 Serial / parallel conversion part 3 LVDS driver 4 LVDS receiver 5 PLL
6 Bidirectional data 7 LVDSI / F
8 Transmission direction control signal 9 Clock 10 Inversion unit 11 LVDS data transmission unit (transmission side block)
12 LVDS data receiver (receiver block)
22, 314, 323, 332 CPU bus 22a, 351 Address bus 22b, 352 Data bus 22c Control signal 100 (copier) main unit 200 Image data processing unit 300 Engine control unit 301, 302 LVDS
310 Main control PCB
311 CPU
312, 324, 333 Bidirectional LVDS device 314, 323, 314 CPU bus 320, 330 Unit control PCB (control side PCB)
321,322,331 Control IC
352-1, 352-2 Select signal BA, BB, BC Function block P Package

Claims (11)

A parallel / serial converter that converts an input parallel signal into a single-ended signal;
An LVDS driver that converts a single-ended signal from the parallel / serial converter to an LVDS output;
An LVDS receiver that converts an input LVDS signal into a single-ended signal;
A parallel / serial converter that converts a single-ended signal from the LVDS receiver into a parallel signal;
A functional block having
Data transmission uses the parallel / serial converter and the LVDS driver,
Data reception uses the LVDS receiver and the serial / parallel converter,
An interface device characterized in that bidirectional communication by LVDS of the parallel signal is performed by switching the transmission direction of the signal of the functional block. The interface device according to claim 1, wherein
The functional block mounted on the one package is commonly used as the bidirectional communication driver or receiver. The interface device according to claim 1, wherein
Switching of the transmission direction of the signal of the functional block is performed by applying a transmission direction control signal to each component of the functional block. The interface device according to claim 3, wherein
The functional blocks are arranged as a pair on the transmitting side and the receiving side,
The interface device, wherein one of the functional blocks receives the transmission direction control signal, and the other receives an inverted signal of the transmission direction control signal. The interface device according to claim 1, wherein
An interface device comprising a plurality of functional blocks mounted on the one package, and setting means for setting the transmission direction for each functional block. The interface device according to claim 5, wherein
An interface device, wherein a CPU bus is applied to one of the plurality of functional blocks. The interface device according to claim 5, wherein
The transmission direction function is set, and one functional block of the plurality of functional blocks is connected to a data bus and functions for bidirectional communication, and the other functional block functions for data transmission. Interface device. The interface device according to claim 5, wherein
An interface device, wherein a signal for disabling operation is applied to a functional block that is not used among the plurality of functional blocks. The interface device according to claim 5, wherein
An interface device characterized by switching a signal transmission direction of the functional block based on a read instruction signal for data reception. The interface device according to claim 9, wherein
The functional blocks are arranged as a pair on the transmitting side and the receiving side,
The interface apparatus characterized in that the transmission direction of the signal is automatically switched based on a transmission direction control signal and a signal level of a setting terminal for setting a driver or a receiver.   An image forming apparatus comprising the interface device according to claim 1.

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