JP2009003863A - Interface device and image forming apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To secure a PCB mounting space regardless of an increase in the number of devices. <P>SOLUTION: Function blocks BA, BB and BC each having a parallel/serial converting part for converting an inputted parallel signal into a single end signal, an LVDS (Low Voltage Differential Signaling) driver for converting the single end signal from the parallel/serial converting part into an LVDS output, an LVDS receiver for converting the inputted LVDS signal into a single end signal, and a parallel/serial converting part for converting the single end signal from the LVDS receiver into a parallel signal are packaged as one CPU bus function block, the plurality of packaged function blocks P1, P2 and P3 are mounted to one device package DP, and LVDS communication is achieved by CPU bus control. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to bidirectional transmission of parallel signals such as a data bus, and more particularly to an interface device that realizes bidirectional transmission by LVDS (Low Voltage Differential Signaling) and an image forming apparatus including the interface device.

  In recent data communication systems, data transfer is performed by a bus. Since parallel signals such as this bus are arranged in parallel, the magnetic force generated by the current flowing through the signal destination. Interference with other signals causes unintended currents to flow due to electromagnetic induction, resulting in signal interference that causes malfunctions, signal delays that occur due to slight differences in wiring length, and the like.

  When long-distance transmission is performed using such parallel signals, an increase in signal lines (electric wires) due to measures such as inserting GND between signal lines to prevent signal interference, or signals due to resistance in the wiring path There is a possibility that signal misdetection due to waveform rounding or distortion, or delay between signals due to an increase in wiring length difference may occur. In order to solve such problems and problems, serial communication such as USB and IEEE 1394 is useful for long-distance transmission. However, these signals require a complicated protocol. Although problems such as signal delay do not occur, low-noise communication involving EMI (unwanted electromagnetic waves) is not necessarily good communication.

  Therefore, in order to realize long-distance communication with low noise, currently, two signal lines are used for one signal line, and subtraction is performed between the signal lines. There is a differential signal transmission method that cancels noise. Further, LVDS is a transmission system that inverts the phase of the two signal lines to halve the amplitude of the voltage and has a lower voltage and less noise. However, at present, the communication by LVDS is realized only in one direction, and there is no one that realizes bidirectional communication like a data bus.

  BLVDS (Bus LVDS), which converts a large number of signal lines such as buses into LVDS, has been put to practical use, but a single transmission line can only communicate in one direction, and both can be used as LVDS devices. There are some that realize the direction, but this is prepared for each signal direction, and it is only that that realizes communication with many signal lines such as buses using this. Devices and communication wires are required, resulting in high costs. Of course, it is impossible to transmit an existing bus form signal such as a CPU bus by LVDS, and if it is to be realized, an address bus and other control signals are required in addition to the bidirectional transmission of the data bus. Further cost increase.

  Taking a large-sized copying machine such as a wide-width machine as an example, in the current communication mode in a copying machine, a signal line is extended over a long distance from a PCB (printed circuit board) equipped with a CPU to each control load. Crawls around. A copier generally includes a reading unit, a writing unit, a main control unit, a transfer paper feeding unit, and the like. If the reading unit is a reading unit, a sensor for detecting a wide document size is provided. is necessary. If the document widths A4, A3, A2, A1, A0, B4, B3, B2, and B1 are to be detected, at least nine sensors, for example, for the document size types are required.

  Here, if nine sensors are to be controlled from the main control unit, the sensor requires at least three signal lines for the drive power supply and signals, and a total of 27 signal lines (electric wires) over a long distance. Will crawl around. Naturally, since it is necessary to control many loads in each unit, a considerable number of wires run around the entire machine (copier). Turning such a number of harnesses causes a problem from the viewpoint of noise, and assembling the harness to the machine is poor in workability and leads to an increase in cost due to the number of wires.

  Therefore, as a method of reducing the number of signal lines, if each unit is provided with a PCB that transmits and receives signals by serial communication or the like with the main control board, the control load in the unit is controlled by the PCB. Since the line is only in the unit, the function can be achieved without running over a long distance, and the main control PCB and the PCB of each unit need only a few signal lines used for serial communication. It is possible to improve the workability of scooping while reducing the number of harnesses.

  However, with such a configuration, the signal lines are certainly reduced, but it is necessary to mount a CPU separately from the main control PCB on the PCB mounted on each unit, which increases the software development man-hours. And timing verification by serial communication becomes a problem. Here, if an IC that operates on the CPU bus is mounted on the PCB mounted on each unit and the PCB of each unit is controlled from the main control PCB by parallel communication using the CPU bus, the software development required for each unit is developed. Can reduce the number of man-hours required. However, there are concerns about malfunction due to signal line distortion due to noise, generation of electromagnetic waves related to EMI, and the like.

  By the way, in the conventional bi-directional communication by LVDS as an interface standard for transmitting a differential signal, when two signal lines are used, it is necessary to perform termination processing on the receiver side. Are provided, and from the viewpoint of signal reflection due to mismatching of these termination resistors, resistance switching control for invalidating one termination resistor has been performed.

  In addition, conventional LVDS communication uses a bidirectional communication package in which LVDS signal lines are separated as shown in FIG. 14 or a bus signal such as BusLVDS as shown in FIG. 15 is converted to LVDS. Thus, a method of performing communication from point to point has been adopted. In the method shown in FIG. 14, when there are many signal lines such as bus lines, a plurality of packages are used, which is expensive, and requires a large mounting area on a PCB board (printed circuit board). there were. In the method shown in FIG. 15, bus signals can be connected by a small number of LVDS signal lines, and bus signals can be connected by LVDS. However, bidirectional communication is not performed and communication in only one way is possible. there were. If two-way communication is to be realized using the BusLVDS, a plurality of packages are required as in the configuration of FIG.

  Therefore, for example, Patent Document 1 proposes a method that enables communication in the reverse direction for an interface that performs unidirectional communication with LVDS. According to this, bidirectional communication is performed by using a single-ended signal (not a differential signal, a normal signal based on 0V: 5V, 3.3V, etc.) slower than LVDS for communication in the reverse direction. Is realized. In other words, communication in one direction via two signal lines is transmitted using a differential signal, but signal transmission in the reverse direction is performed using a single-ended signal for signal transmission requiring high speed. Uses differential signals, and when low speeds are acceptable, performs transmission using single-ended signals.

Further, as an example of a conventional interface that enables high-speed data transfer without requiring a special decompression device, for example, the invention described in Patent Document 2 can be cited. In the invention described in Patent Document 2, the interface between the printer controller and the printer engine includes a control line capable of transmitting and receiving various control signals and a data line for transmitting image data from the controller to the engine. In addition, since it is not necessary to transmit and receive a control signal between image data transmissions, high-speed image data transmission is possible.
JP 2005-18312 A JP 2002-254663 A

  However, the above cited reference 1 does not realize the bidirectional communication of the LVDS itself, but uses the single-ended signal to implement the LVDS one-way communication and realize the communication in the opposite direction. In this case, the signal (single-ended signal) at the time of communication opposite to the direction of communication by LVDS is limited in speed and signal type, and noise is also generated. . In particular, bi-directional communication cannot be used for signals such as a data bus, and when performing communication in the opposite direction to LVDS, it is limited to the case of communicating auxiliary signals. Also, in the cited document 2, only one-way communication of image data is performed using a data line.

  As described above, bi-directional communication by LVDS enables communication with a plurality of devices over a long distance using a CPU bus. However, as the number of devices to be controlled increases, a device that realizes bi-directional LVDS on a PCB. In particular, in a main control board on which a CPU is mounted, it is difficult to secure a PCB mounting space for the number of devices.

  Therefore, a problem to be solved by the present invention is to ensure a PCB mounting space regardless of an increase in devices.

  In order to solve the above problems, the first means includes a parallel / serial converter that converts an input parallel signal into a single-end signal, and an LVDS that converts a single-end signal from the parallel / serial converter into an LVDS output. A plurality of functional blocks each having a driver, an LVDS receiver that converts an input LVDS signal into a single-ended signal, and a parallel / serial converter that converts a single-ended signal from the LVDS receiver into a parallel signal It features an interface device that is mounted on a package and performs LVDS communication under CPU bus control.

  A second means is characterized in that, in the first means, a signal line including one address bus, data bus, and control signal line necessary for the CPU bus control is input from the CPU of the CPU bus into the package. To do.

  The third means is characterized in that, in the first means, means for setting whether or not each of the plurality of functional blocks is operable is provided.

  According to a fourth means, in the first means, the one package functions as a driver or a receiver.

  A fifth means is characterized in that, in the fourth means, when the package functions as a receiver, the operation of the functional blocks that are not used is stopped.

  A sixth means is characterized in that, in the fifth means, there is provided means for selecting a functional block of a CPU path to be used when the package functions as a receiver.

  The seventh means is characterized in that the image forming apparatus includes an interface device according to any one of the first to sixth means.

  In the embodiment described later, the parallel / serial converter is denoted by reference numeral 1, the LVDS driver is denoted by numeral 3, the LVDS driver is denoted by numeral 4, the serial / parallel converter is denoted by numeral 2, and the CPU bus is denoted by numerals 314 and 323. , The CPU corresponds to the reference numeral 21, the functional block corresponds to the reference numeral BA, BB, BC, and the package corresponds to the reference numeral P, and the setting of whether each of the plurality of functional blocks is operable is performed by control of the enable signal EN.

  According to the present invention, by mounting a plurality of functional blocks having an LVDS bidirectional communication function in one package, the communication between the CPU and the plurality of devices is realized in one package. Mounting space can be secured.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram showing an internal circuit of an interface device according to an embodiment of the present invention. The interface device according to the embodiment of the present invention basically includes a parallel / serial conversion unit 1, a serial / parallel conversion unit 2, an LVDS driver 3, an LVDS receiver 4, and a PLL unit 5. Reference numeral 6 represents bidirectional data, reference numeral 7 represents LVDSI / F, reference numeral 8 represents a transmission direction control signal, and reference numeral 9 represents a clock.

  In the circuit shown in FIG. 1, data 6 to be transmitted is first input to the parallel / serial converter 1. The parallel / serial converter 1 shifts data to a register for serial data transfer according to the clock multiplied by the PLL 5. The shifted data is input to the LVDS driver 3 and output as an LVDS signal through the LVDSI / F7. When the LVDS signal is input, on the contrary, the signal sent by LVDS through the LVDSI / F7 is received by the LVDS receiver 4, and the signal is input to the serial / parallel converter 2, and the serial / parallel converter is received. The data converted at 2 is output as parallel data 6.

  FIG. 2 is a diagram illustrating an example of inversion states of transmission direction control signals on the transmission side and the reception side. In the figure, a transmission direction control signal 8 for switching a signal transmission direction is input to each element of a parallel / serial conversion unit 1, a serial / parallel conversion unit 2, an LVDS driver 3, and an LVDS receiver 4. If the control signal 8 is H, the LVDS data transmission unit 11 is active, and if it is L, the LVDS data reception unit 12 is active.

  The LVDS driver 3 converts the input single-ended signal into LVDS outputs (two signals having opposite directions). The LVDS receiver 4 converts the input LVDS signals (two signals in opposite directions) into single-ended signals. The parallel / serial conversion unit 1 temporarily shifts the input parallel data to a register, and performs parallel / serial conversion by sequentially sending the data from the first bit of the register. The same applies to converting input serial data into parallel data. Stocked data is stored in a register from the beginning, and if all the data is stored, it is transferred to a port output register. The function of the / parallel converter 2 is fulfilled. These conversion units 1 and 2 can be switched according to their respective applications, and this switching is performed by a transmission direction control signal 8.

  The transmission direction control signal 8 is a signal for controlling the bidirectional transmission direction. Since the data transmission direction has the parallel / serial conversion unit 1 and the LVDS driver 3 as functional blocks, and conversely, the data reception direction has the serial / parallel conversion unit 4 and the LVDS receiver 2. This function needs to be switched depending on the signal transmission direction, and the transmission direction control signal 8 is used as the enable signal.

  The transmission direction control signal 8 may be output from the port as a separate signal at the start of data communication, or a control signal such as read / write used for CPU bus control may be used. Further, when used in one-way transmission, the level of the driver / receiver control signal is fixed by a function that uses it.

  On the other hand, the prior art of FIG. 14 shows the configuration in the LVDS two-way communication package in which the LVDS signal lines are different, but in the package shown in FIG. 2, the LVDS driver 3 and the receiver 4 are respectively used for transmission and reception. In one wire, the signal direction is only one direction. 15 shows the internal configuration of the bus LVDS, the configuration is such that the LVDS driver 3 outputs the data in LVDS through the parallel / serial conversion unit 1 that converts parallel data into serial data. The signal direction is only one direction. In this case, when receiving a signal in the reverse direction, another receiving package is required.

  As shown in FIG. 1, in this embodiment, the transmission direction control signal 8 switches the LVDS transmission direction (transmission direction and reception direction), but the transmission direction is controlled by the signal level, so the data receiving side It is necessary to input signals of different levels between the block 12 and the transmission side block 11 (see FIG. 2). Therefore, as shown in FIG. 2, for example, the signal is input to the other PCB 12 separately from the LVDS signal, and the signal is inverted by the inverting unit 10 and supplied as a transmission direction control signal. This makes it possible to clarify the data transmission side block 11 and reception side block 12 when transmitting a signal.

  Also, as shown in FIG. 3, if a fixed level signal is input to the transmission direction control signal, it can be fixed to either the LVDS transmission / reception function inside the package. It is possible to use only for drivers and receivers. In FIG. 3, the transmission control signal is grounded in the reception side block 12, and a predetermined value is applied as the transmission control signal in the transmission side block 11. As can be seen from FIG. 2 and FIG. 3, the transmission side block 11 and the reception side block 12 are one common package (the circuit configuration in the solid line frame in the figure), and the settings of the driver and the receiver can be appropriately selected. is there. The transmission side block 11 and the reception side block 12 are switched as appropriate.

  FIG. 4 is a diagram showing a related configuration between the functional block and the package in the interface apparatus according to the present embodiment. As shown in FIG. 4, the configuration including the parallel / serial conversion unit 1, the serial / parallel conversion unit 2, the LVDS driver 3, the LVDS receiver 4, the LVDSI / F7, etc. is integrated into the first to third functions. Blocks BA, BB, and BC are used, and a plurality of these first to third functional blocks BA, BB, and BC are collected and stored in one package P. These first to third functional blocks BA, BB, BC can be controlled independently, and the transmission direction of the signal can be set according to the function by the transmission direction control signal 8 or the like. Further, by performing control of a known enable signal EN as shown in each functional block BA, BB, BC, unnecessary functional blocks can be set to be inoperable.

  FIG. 5 is a block diagram showing a configuration of an interface device using a CPU bus. As shown in FIG. 5, the CPU bus 22 includes an address bus 22a, a data bus 22b, and control signals (read signal, write signal, chip select signal, etc.) 22c, and these buses 22a, 22b, and 22c are connected to each other. The CPU 22 and the interface device (package) communicate with each other. In the example of FIG. 5, these signals are assigned to the first to third functional blocks BA, BB, and BC. For example, since the data bus 22b is bidirectional communication, the third functional block BC is used for LVDS bidirectional transmission, and the address bus 22a and the control signal 22c are unidirectional communication from the CPU 21 side. The second functional blocks BA and BB are set as LVDS drivers. Of course, it is necessary to perform the above-described setting also on the PCB on the other side that receives the signal. The first and second functional blocks BA and BB are used as receivers, and the third functional block BC is transmitted bidirectionally. Use as

  FIG. 6 is a diagram showing an operation example of the interface device when the CPU bus is used. In FIG. 6, the PCB on which the CPU 21 is mounted is referred to as PCB1, and the PCB that is controlled by the CPU 21 is referred to as PCB2. The CPU bus 22 performs writing (writing) of data from the CPU 21 of the PCB 1 to the device 23 of the PCB 2 and reading (reading) of receiving data from the other party. Since transmission is performed by direction transmission, PCB1 simply functions as an LVDS driver and PCB2 functions as an LVDS receiver. Further, at the time of reading, it is necessary to perform an operation in which the CPU 21 sends a command to the counterpart device 23 and the CPU 21 receives data returned in response thereto.

  As a method for realizing the above-described operation, when performing a read operation, first, the transmission direction control signal 8 of the data bus 22b is inputted at the same time when the address and the control signal are transmitted to the PCB 2, and the transmission direction of the data bus 22b is changed. Just decide. By this transmission direction control signal 8, the third functional block BC is set to the data reception function (LVDS reception function) and can receive data.

  FIG. 7 is a diagram showing an example of operation when the CPU bus is used, and shows how the transmission direction control signal is created and used. In FIG. 7, if a signal 8a obtained by ANDing a read signal (a signal when the CPU 21 instructs to read, an L level signal) and, for example, an H signal is input to the transmission direction control signal terminal, communication is performed. Since the read signal is at the H level when writing is not performed or at the time of writing (because it is not when reading is instructed), the output of the AND circuit 8b is at the H level, and the third function block BC is driven by the driver. Set it to. With this setting, the transmission direction control signal becomes L only when a read signal is input, so that LVDS can be set as a reception function. Thereby, it becomes possible to control only by the signal level of the read signal without separately outputting the transmission direction control signal 8 from the port.

  At that time, the CPU bus 22 has a predetermined timing between signals in order to capture data reliably. However, after the read signal (L level signal) is output until the data is captured, There is a certain amount of time, and there is no problem in detecting the transmission direction control signal.

  FIG. 8 is a block diagram showing a configuration of an interface device in which a bidirectional LVDS device is fixed to either a driver or a receiver function and the transmission direction of the functional block is switched as necessary. In the case of the CPU bus, since a control signal is output from the CPU side PCB (PCB1), the PCB 1 on the CPU side is set as a so-called master, and the level of the transmission direction control signal 8 is switched according to the transmission direction. The transmission direction of (PCB2) can be controlled. For example, the function of the bidirectional LVDS device can be set to the driver and the receiver by setting the driver / receiver setting terminal 8c to H (for example, voltage application) in the PCB1 and L (for example, ground) in the PCB2.

  In the transmission direction control, as described with reference to FIG. 2, it is necessary to invert the logic of the transmission direction control signal 8 on the driver side and the receiver side. The driver side (PCB1) transmits when the transmission direction control signal 8 is H (transmission direction control signal is H for writing, L for reading, for example), so the signal level of the driver / receiver setting terminal 8c (this Depending on the case H), the second wire W2 is connected as an input to the function block B in the signal logic selection function unit 8d. The signal logic selection function unit 8d selects one of the outputs of the driver function / receiver function for the input signal from the driver / receiver setting terminal 8c depending on whether the transmission direction control signal 8 is H or L. Similarly, on the receiver side (PCB2), the first wire W1 or the second wire W2 is selected according to the level of the driver / receiver setting terminal 8c (in this case, L). Since L is the first wire W1, the logic level of the transmission direction control signal 8 is reversed between the driver side and the receiver side.

  Setting (fixing) the driver / receiver (interface device) also means determining the direction of the signal when sending the transmission direction control signal to the other side. Thus, the input / output selection function unit 8e can select the input / output in the same manner according to the level of the driver / receiver setting terminal 8c (voltage application H or ground L). In the example described above, the driver side is set to output, and the receiver side is set to input. The point is that the function block B of PCB1 is selected as either a transmission function or a reception function according to H or L of the transmission direction control signal 8, and at the same time, the function block B of PCB2 is selected as a function opposite to that of PCB1. Any configuration may be used, and the configuration is not limited to that illustrated in FIG.

  Therefore, by controlling a block such as the data bus 22b (see FIG. 5) that requires a bidirectional function with the circuit and the transmission direction control signal, it is possible to switch between the transmission and reception functions and perform communication. . For example, in the case of light, by setting the transmission direction control signal 8 to H, the driver side is connected to the second wire W2, so that the H signal directly controls the function block B, and the function block B Become a function. On the other hand, on the receiver side, the input transmission direction control signal is set in the receiver and is input to the function block B through the first wire W1, so that the signal level is L and the function block B is received. Will function as. In the case of reading, only the transmission direction control signal described above becomes L, and the rest is the same.

  FIG. 9 is a block diagram showing the features of this embodiment. In the figure, a plurality of functional blocks necessary for the CPU bus (CPU bus functional block = package P) are mounted in one device package DP. The CPU bus functional block (package P) is a set of signal lines (address bus 22a, data bus 22b, control signal 22c) necessary for the CPU bus 22 shown in FIG. In the example shown in FIG. 9, a plurality of CPU bus functional blocks (packages P) are mounted as P1, P2, P3.

  When the signal output from the CPU 21 is input to the device package DP of the LVDS device, it is input to each package P (P1, P2, P3...) That is a CPU bus functional block. From each package P, the CPU bus 22 is converted to LVDS and output. When viewed from the LVDS device (device package DP) itself, the input from the CPU 21 is one block, and the output of the LVDS is a plurality of blocks. It is the composition. Here, the block is a unit in which a signal line necessary for CPU bus control is considered as one block. In FIG. 9, there is one input from the CPU bus 22 as described above, and this is branched internally and input to each CPU bus functional block (package P).

  Each CPU bus function block BW. BB. BC can be operated by an enable signal EN. For example, when the CPU bus function blocks (packages) are P1, P2, and P3 from the top in FIG. 9, when the package P1 is to be operated, the enable signal of the package P1 is used. An L level signal (assuming active L) is input, and an H level signal may be input to the other blocks. This enable signal is equivalent to the enable signal EN in FIG. Alternatively, the above-described CPU bus function blocks P1, P2, P3. Since the CPU bus 22 communicates with a plurality of ICs by designating an IC to be controlled by a chip select signal, the signal always flows in the device or a cable. However, if the timing is satisfied, no trouble due to data collision or the like occurs, so that normal communication and control can be performed.

  Even in the case of the configuration shown in FIG. 9, one driver P can be used for either the driver / receiver. The driver and receiver can be selected by inputting a signal for selecting which function to use for the LVDS device, and the function switching by the selection signal is described in the function block below the CPU bus function block. As shown, the transmission direction control signal 8 is used.

  When used as a receiver, only one function of the plurality of CPU bus function blocks P1, P2, P3... Needs to be operated. Or try to eliminate unintended malfunctions. The LVDS device DP in the present embodiment has a plurality of CPU bus functional blocks P1, P2, P3..., But when used as a receiver, only one of them needs to be operated. Further, when the LVDS device according to this embodiment is mounted on a certain PCB, there is no problem even if a plurality of CPU bus function blocks P1, P2, P3,... .

  However, as the operation of the CPU bus, since the bus is common and an operation of selecting an IC to be controlled by a select signal is performed, even if there are a plurality of control ICs in one PCB, as shown in FIG. If a plurality of select signals can be generated from one CPU bus functional block after being converted into parallel data, control becomes possible. Therefore, as described above, the receiver need only operate one block. FIG. 10 is a block diagram showing the internal configuration of the control unit side PCB (details will be described later).

  Therefore, it is possible to select which block to use from the plurality of blocks P1, P2, and P3 shown in FIG. Which pin of the device outputs the CPU bus converted to parallel greatly affects the pattern distribution to the IC, but usually the pattern is wound around so as to be the shortest. In that case, it is a point to output from which pin of the LVDS device, and it is desirable to use a block assigned to a pin that can be crushed in the shortest time.

  Therefore, if the CPU bus functional blocks P1, P2, and P3 to be used can be selected, the optimum pattern distribution as described above can be considered. As a method of selecting the CPU bus functional block, for example, a method of selecting a block according to the signal level of the block selection signal after allowing a selection signal to be input from the outside to each block can be adopted. . This selection method is as described with reference to FIG.

  The interface device described so far is applied to, for example, a copying machine. FIG. 11 is a diagram showing an outline of the mechanical configuration of the copying machine provided with the above-described interface device, and FIG. 12 is a block diagram showing the main part of the control configuration.

  The copying machine shown in FIG. 11 includes a main body unit 100, a paper feeding unit 110, a reading unit 120, and an automatic document feeding unit (ADF) 130. The main body unit 100 is positioned above the paper feeding unit 110, and the reading unit 120 is positioned above the main body unit 100. Further, an ADF 130 is provided above the reading unit 120.

  The copying machine according to the present embodiment forms an image by an electrophotographic method, and a main body unit 100 is provided with a photoconductor 101, a fixing device 102, a duplex device 103, and a paper discharge device 104. A charging unit 105, a developing unit 106, a transfer unit 107, a cleaning unit 108, and a static elimination unit (not shown) are disposed on the outer periphery of the photoconductor 101. The main body 100 is provided with a writing unit 109 for writing. The writing unit 109 includes an optical device such as an LD for writing an image and a driver IC for driving the optical device. The writing unit 109 drives (flashes) the optical device in accordance with the transferred data, and a photoconductor. An optical writing operation is performed on 101.

  The paper feeding unit 110 has five paper feeding stages 111, 112, 113, 114, and 115, which are sent from the designated paper feeding stage through the paper feeding roller to the transfer unit 107 from the vertical conveyance path 116, and are written in. 109 is written on the surface of the photoconductor 101 to form an electrostatic latent image. The reading unit 120 optically reads the document placed on the contact glass in the sub-scanning direction or the document conveyed by the ADF 130 with the traveling body stopped. The former is generally called a flat bed system, and the latter is generally called a sheet through system. Reading by the flat bed method is performed, for example, in the case of a book document, and reading by the sheet-through method is performed, for example, in the case of a plurality of sheet documents. In this embodiment, the ADF 130 is a circulation type automatic document feeder that can also reversely read a document, also referred to as ARDF.

  Furthermore, as shown in FIG. 12, an image data processing unit 200 that handles image data, and an engine control unit 300 that is responsible for overall machine control such as paper conveyance timing are provided.

  The image data processing unit 200 includes an image processing unit 210, a controller 220, an image data arrangement unit 230, an operation unit 240, and a storage device (HDD) 250. The image processing unit 210 includes a plurality of processors. Image data read by the reading unit 120 and converted into digital data is input, and shading correction, background removal, and other images necessary for writing images by the respective processors. Processing is performed.

  The controller 220 includes a plurality of processors and controls the output timing of image data in the image system. Image data that has undergone image processing is temporarily stored in a storage device (HDD) 250. It should be noted that it may be stored in a memory inside the controller instead of the HDD 250. The controller 220 retrieves necessary data from the HDD 250 according to the output timing of each image data, and transfers it to the data arrangement unit 230. The image data arrangement unit 230 has a line memory corresponding to the image writing width, and data transferred from the controller 220 is arranged in this line memory in accordance with the image area. The memory is a FIFO, and the arranged data is sent to the write control unit in order from the top.

  The operation unit 240 is a user interface, and is provided with hard keys, soft keys, and a display, and an instruction input from the user and display to the user are performed.

  The engine control unit 300 includes a main control PCB 310 and first and second unit control PCBs 320 and 330 connected to each unit via first and second LVDSs 301 and 302 with respect to the main control PCB 310. The main control PCB 310 includes a CPU 311 and first and second bidirectional LVDS devices 312 and 313, and the first and second bidirectional LVDS devices 312 and 313 are connected to the CPU 311 via the CPU bus 314. The first bidirectional LVDS device 312 is connected to the first unit control PCB 320 via the first LVDS 301, and the second bidirectional LVDS device 313 is connected to the second unit control PCB 330 via the second LVDS 302. Are connected to each. This embodiment is an example in which LVDS bi-directional communication is applied to a CPU bus to control a plurality of units at a long distance. In this example, it relates to overall machine control such as paper transport timing of a copying machine. This is applied to the engine control unit 300 that handles the part.

  That is, the main control PCB 310 is connected to interface boards and drive boards of various loads, and read / write control. A CPU bus 314 is connected from the CPU 311, and when the CPU bus 314 outputs to the unit control PCB 320 as described above, the unit control PCB 320 via the bidirectional LDVS device 312 that realizes the above-described bidirectional transmission of LVDS. Connected. The unit control PCB 330 is connected to the second unit control PCB 330 via the second LVDS 302. Connection to the bidirectional LDVS device 312 is performed by a connector.

  The first unit control PCB 320 includes first and second control ICs 321 and 322, and bidirectionally communicates with the main control PCB 310 via the first LVDS 301 by the bidirectional LVDS device 324 connected to the CPU bus 323. Do. For example, a motor 321a, sensors 321b, 321c, and the like are connected to the first control IC 321, and a clutch 322a, sensors 322b, 322c, and the like are connected to the second control IC 322, for example.

  The third unit control PCB 330 includes a control IC 331 and performs bidirectional communication with the main control PCB 310 via the second LVDS 302 by the bidirectional LDVS device 333 connected to the CPU bus 332. For example, a clutch 331a, sensors 331b, 331c, and the like are connected to the second control IC 331.

  In general, the unit control PCBs 320 and 330 receive the CPU bus 314 by the LVDS devices 324 and 333 in the same manner as the main control PCB 310, convert them into parallel CPU buses 323 and 332, and control ICs 321. , 322, 331. These control ICs 321, 322, and 331 are ICs controlled by the CPU buses 323 and 333, and are ICs that passively operate in response to commands from the CPU 311, such as IO expansion ICs. These ICs are widely used, and the CPU buses 323 and 332 access the allocated address space and control the respective ports accordingly. Therefore, central control from the CPU 311 is possible.

  Further, the CPU buses 314, 323, and 332 can control a plurality of devices by a select signal. For example, if there are three select signals, the two are arranged at optimal positions for connection to the control load. One IOB may be allocated to a read-related IO control PCB.

  In the IO control related to reading, for example, a plurality of sensors necessary for detecting the document size are temporarily input to the port of the IO expansion IC, and the CPU 311 controls the IO expansion IC to obtain sensor information. Thus, only the signal line of the CPU bus obtained by converting the signal line necessary for each sensor into the LVDS serial can be obtained.

  In addition, the first and second unit control PCBs 320 and 330 controlled by the CPU 311 (BCU-Bus Control Unit) of the main control PCB 310 are arranged at optimal positions with respect to the load to which the unit control PCBs 320 and 330 are connected. can do. In other words, the first and second unit control PCBs 320 and 330 controlled by the main control PCB 310 can be arranged at optimal positions that minimize the connection load turning.

  For example, the unit control PCB that performs control related to reading may be arranged in the reading unit 120, and when the sheet feeding unit 110 is to be controlled, the connection with the load controlled by the unit control PCB is minimized. The unit control PCB may be arranged at the position of the paper feeding unit 110. For example, if the control load of the paper feeding unit 110 is concentrated in the lower left as viewed from the rear of the machine, they are currently distributed over a long distance, but in this configuration, unit control is performed around the lower left of the machine. By arranging the PCB, the connection with the control load by the harness can be minimized. Further, since the connection to the main control PCB 310 is only the LVDS cable, it can be easily wound.

  When the control load of the first and second unit control PCBs 320 and 330 is large, there is a possibility that a plurality of control ICs (in particular, IO expansion ICs here) are mounted like the first unit control PCB 320. However, the main control PCB 310 and the control-side PCB (first and second unit control PCBs 320 and 330) need only be connected by an LVDS cable that connects the CPU bus.

  As shown in FIG. 10, the first unit control PCB 320 which is the control side PCB has, for example, many connection loads (sensors, clutches, etc.) of the control side PCB, and requires a plurality of IO expansion ICs. In this case, the CPU bus 323 received by the LVDS bidirectional device 324 and converted into a parallel bus may be branched as it is and connected to a plurality of IO expansion ICs. There is no problem if a plurality of select signals are transmitted when they are output from the main control PCB 310.

  For example, as described above, the CPU bus 323 is composed of an address bus 351, a data bus 352, and various control signals. When two IO expansion ICs are to be controlled, this control signal includes a read signal. The first select signal 352-1 and the second select signal 352-2 may be transmitted together with the signal 352r and the write signal 352w, and the select signals 352-1 and 352-1 are transmitted to the control side PCB (first unit control PCB 320). The IO expansion ICs (in this embodiment, the first control IC 321 and the second control IC 322) may be distributed.

  In addition, a signal with severe timing such as an interrupt may be transmitted as it is without being converted into LVDS. FIG. 13 is a diagram showing a configuration for transmitting as it is without converting to the LVDS. Regardless of whether it is a copier or another device, the concept of interrupt is often used as the overall system control. There are two types of interrupts: internal interrupts used inside the program and external interrupts that perform interrupt operations in response to external signals. The example of FIG. 13 relates to external interrupts, and the second unit of FIG. This corresponds to the configuration of the control PCB 320.

  In the process from the paper transport process of the copying machine to the execution of the image writing operation, the timing for writing the image is very severe, and if this timing is shifted, the margin width from the leading edge of the paper to the image changes. The effects such as will come out. In order to prevent this, the sensor confirms that the paper has arrived in order to indicate the position when the leading edge of the paper has reached before the writing of the image process. This sensor (hereinafter referred to as a registration sensor) 322r (see FIG. 11). Is input to the CPU 311 by an external interrupt, so that an operation for preferentially confirming the position of the leading edge of the sheet on the program is performed, and the operation of the next image writing process is started.

  If the registration sensor 322r is input from the position shown in FIG. 11 to the second unit control PCB 320 as shown in FIG. 13, it is input to the port of the IO expansion IC 322 in the second unit control PCB 320. Will be. The IO expansion IC 322 also has an interrupt port, and the signal input here is further output to the main control PCB 310 as an interrupt signal from the IO expansion signal. If this interrupt signal is not converted to LVDS, it is converted to LVDS. The transmission time can be transmitted to the main control PCB 310 without causing the delay time to be a problem. If there are several signal lines for interrupts or the like, a large current does not flow, so there is no problem with malfunction or noise. Further, as indicated by reference numeral 322r ', the output of the registration sensor may be transmitted as it is to the CPU 311 of the main control PCB 310 (PCB1) without using the interrupt port of the IO expansion IC 322 (reference numeral 325). At that time, if the signal is assigned to the remaining pins of the connector of the LVDS cable of the CPU bus 323, it can be turned around without requiring a separate harness.

  If centralized control that simplifies the power supply startup sequence by the CPU bus is realized as described above, the design of the main power supply startup sequence can be simplified.

It is a figure which shows the internal circuit of the interface apparatus which concerns on embodiment of this invention. It is a figure which shows an example of the inversion state of the transmission direction control signal in the transmission side and the receiving side in the transmission of LVDS regarding embodiment. It is a figure which shows the other example of the inversion state of the transmission direction control signal in the transmission side in the transmission of LVDS regarding embodiment, and a receiving side. It is a figure which shows the related structure of the functional block and package in the interface apparatus which concerns on embodiment. It is a figure which shows the structural example at the time of using CPU bus | bath in the interface apparatus which concerns on embodiment. It is a figure explaining the operation example at the time of using CPU bus | bath in the interface apparatus which concerns on embodiment. It is a figure which shows the preparation and usage method of a transmission direction control signal as an operation example at the time of using a CPU bus in the interface apparatus which concerns on embodiment. It is a figure which shows the structure which fixes the bidirectional | two-way LVDS device in the function of either a driver or a receiver in the interface apparatus which concerns on embodiment, and switches the transmission direction of a functional block as needed. It is a block diagram which shows the characteristic of this embodiment which mounted multiple CPU functional blocks in one device package. It is a block diagram which expands and shows 2nd unit control PCB which is control side PCB in embodiment. 1 is a diagram illustrating an outline of a machine configuration of a copying machine. FIG. 12 is a block diagram illustrating a main part of a control configuration of the copier of FIG. 11. It is a figure which shows the structure which transmits as it is, without converting into VDS. It is the communication by LVDS regarding a prior art, Comprising: It is a block diagram which performs two-way communication by the signal line provided separately. It is a block diagram which converts a bus signal like BusLVDS regarding a prior art into LVDS, and performs one-way communication.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Parallel / serial conversion part 2 Serial / parallel conversion part 3 LVDS driver 4 LVDS receiver 5 PLL
6 Bidirectional data 7 LVDSI / F
8 Transmission direction control signal 9 Clock 10 Inversion unit 11 LVDS data transmission unit (transmission side block)
12 LVDS data receiver (receiver block)
21 CPU
22 CPU bus 22a Address bus 22b Data bus 22c Control signal 100 (Copier) main unit BA, BB, BC Function block DP device package P (P1, P2, P3) package

Claims (7)

A parallel / serial converter that converts an input parallel signal into a single-ended signal;
An LVDS driver that converts a single-ended signal from the parallel / serial converter to an LVDS output;
An LVDS receiver that converts an input LVDS signal into a single-ended signal;
Parallel / converts a single-ended signal from the LVDS receiver into a parallel signal
A serial conversion unit;
An interface device, wherein a plurality of functional blocks each having the above are mounted in one package, and LVDS communication is performed by CPU bus control. The interface device according to claim 1.
An interface device, wherein a signal line including one address bus, data bus, and control signal line necessary for the CPU bus control is input from the CPU of the CPU bus into the package. The interface device according to claim 1.
An interface device comprising means for setting whether or not each of the plurality of functional blocks is operable. The interface device according to claim 1.
An interface device that functions as a driver or a receiver in the one package. The interface device according to claim 4, wherein
When the package functions as a receiver, an operation of a function block that is not used is stopped. The interface device according to claim 5, wherein
An interface device comprising means for selecting a functional block of a CPU path to be used when the package functions as a receiver.   An image forming apparatus comprising the interface device according to claim 1.

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