CN109037182A - Chip-packaging structure and memory device - Google Patents
Chip-packaging structure and memory device Download PDFInfo
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- CN109037182A CN109037182A CN201811065137.XA CN201811065137A CN109037182A CN 109037182 A CN109037182 A CN 109037182A CN 201811065137 A CN201811065137 A CN 201811065137A CN 109037182 A CN109037182 A CN 109037182A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 48
- 238000003466 welding Methods 0.000 claims abstract description 136
- 239000002184 metal Substances 0.000 claims abstract description 74
- 229910052751 metal Inorganic materials 0.000 claims abstract description 74
- 239000000084 colloidal system Substances 0.000 claims abstract description 15
- 238000000465 moulding Methods 0.000 claims abstract description 7
- 230000006870 function Effects 0.000 description 12
- 230000015654 memory Effects 0.000 description 10
- 238000005538 encapsulation Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 230000003993 interaction Effects 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 239000002699 waste material Substances 0.000 description 3
- 230000006399 behavior Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000005520 electrodynamics Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004021 metal welding Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/32258—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
- H01L2224/48249—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item the bond pad protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Memories (AREA)
Abstract
The present invention discloses a kind of chip-packaging structure and memory device, wherein the chip-packaging structure includes wafer, metal pad and multiple first conductive welding disks；Wafer is fixed on metal pad by colloid, multiple first conductive welding disks are bonded by metal wire with wafer, first conductive welding disk is provided with 26, eight data pins of multiple first conductive welding disks and wafer, five power pins, four chip select pins, two differential signal pins, read signal pin, write signal pin, data latch pin, code latches pin, data strobe pin, LED signal pin and be ready to/and busy signal pin is correspondingly connected with, metal pad is bonded by metal wire with wafer, the grounding pin connection of metal pad and wafer；Wafer, metal pad and multiple first conductive welding disks pass through molding colloid overall package.The present invention solves the problems, such as that wafer is not easy extension using SSOP-24 packaged type performance and QFN-32 packaged type function is superfluous.
Description
Technical field
The present invention relates to chip encapsulation technology field, in particular to a kind of chip-packaging structure and memory device.
Background technique
Common memory device such as USB flash disk, mobile hard disk etc. generally includes wafer and flash memory, and wafer is encapsulated using QFN
After be mounted on pcb board, usual pin pad be evenly distributed on square surrounding, can take SSOP-24 packaged type and
QFN-32 packaged type, but for SSOP-24 encapsulation, there are pin pad is very few, the problem of being unfavorable for behavior extension,
And for QFN-32 encapsulation, it there are pin pad is excessive, causes extra pin pad function superfluous, cost is caused to waste.
Summary of the invention
The main object of the present invention is to provide a kind of chip-packaging structure, it is intended to solve wafer using the encapsulation side SSOP-24
Formula performance is not easy the problem of extension and QFN-32 packaged type function surplus.
To achieve the above object, a kind of chip-packaging structure proposed by the present invention includes that wafer, metal pad and setting exist
Multiple first conductive welding disks of the metal pad surrounding；
The wafer is fixed on the metal pad by colloid, multiple first conductive welding disks by metal wire with
Wafer bonding, first conductive welding disk are provided with 26, multiple first conductive welding disks and the wafer
Eight data pins, five power pins, four chip select pins, two differential signal pins, read signal pin, write signal draw
Foot, data latch pin, code latch pin, data strobe pin, LED signal pin and get out/busy signal pin correspondence
Connection, the metal pad are bonded by metal wire with the wafer, and the grounding pin of the metal pad and the wafer connects
It connects；
The wafer, the metal pad and multiple first conductive welding disks pass through molding colloid overall package.
Preferably, the chip-packaging structure includes the first lateral margin, the second lateral margin, third lateral margin and the 4th lateral margin, multiple
The first conductive welding disk correspondence is distributed in first lateral margin, second lateral margin, the third lateral margin and the 4th side
On edge, each lateral margin intersection is provided with a vacancy area, at least one second conductive welding disk is provided in the vacancy area,
Second conductive welding disk be bonded by metal wire with the wafer or with metal pad integrated molding setting, described the
Two conductive welding disks are correspondingly connected with the grounding pin of the wafer or remaining corresponding signal pin.
Preferably, the second conductive welding disk quantity is four.
Preferably, the chip-packaging structure further includes third conductive welding disk and the 4th conductive welding disk, and the third is conductive
Pad and the 4th conductive welding disk are bound by metal wire and the wafer, the third conductive welding disk and the 4th conduction
Pad is correspondingly connected with the residual signal pin or grounding pin of the wafer respectively, the third conductive welding disk and described
Four conductive welding disks are correspondingly arranged on two opposite lateral margins.
Preferably, the chip-packaging structure further includes the 5th conductive welding disk and the 6th conductive welding disk, and the described 5th is conductive
Pad and the 6th conductive welding disk are bound by metal wire and the wafer, the 5th conductive welding disk and the 6th conduction
Pad is correspondingly connected with the residual signal pin or grounding pin of the wafer respectively, the 5th conductive welding disk and described
Six conductive welding disks are correspondingly arranged on two opposite lateral margins.
Preferably, the centre distance that two adjacent conductive welding disks of each lateral margin are arranged in is more than or equal to
0.35mm, and it is less than or equal to 0.45mm.
Preferably, the length of each conductive welding disk is more than or equal to 0.25mm and is less than or equal to 0.35mm,
The width of each conductive welding disk is more than or equal to 0.15mm and is less than or equal to 0.25mm.
Preferably, be provided with chamfering on a lateral margin of the conductive welding disk of second conductive welding disk, it is described fall
Angle is more than or equal to 30 degree and is less than or equal to 60 degree.
The present invention also proposes a kind of memory device, which is characterized in that including chip-packaging structure as described above.
Technical solution of the present invention by using include wafer, metal pad, metal pad surrounding is set multiple first
Conductive welding disk compositing chip encapsulating structure, wafer are fixed on metal pad by colloid, and multiple first conductive welding disks pass through gold
Belong to line to be bonded with wafer, the first conductive welding disk is provided with 26, and eight data of multiple first conductive welding disks and wafer are drawn
Foot, five power pins, four chip select pins, two differential signal pins, read signal pin, write signal pin, data latch
Pin, code latch pin, data strobe pin, LED signal pin and be ready to/busy signal pin is correspondingly connected with, metal welding
Disk is bonded by metal wire with wafer, the grounding pin connection of metal pad and wafer, and by forming colloid overall package, when
After chip-packaging structure is mounted on PCB, chip-packaging structure, which can provide, meets memory device progress signal interaction and read-write function
The functional pin of energy, and a variety of chip select functionalities can also be provided, and reduce unnecessary general utility functions pin, to solve
Wafer is not easy the problem of extension and QFN-32 packaged type function surplus using SSOP-24 packaged type performance.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
The structure shown according to these attached drawings obtains other attached drawings.
Fig. 1 is the structural schematic diagram of one embodiment of chip-packaging structure of the present invention；
Fig. 2 is the structural schematic diagram of wafer in one embodiment of chip-packaging structure of the present invention；
Fig. 3 is the structural schematic diagram of chip-packaging structure of the present invention and embodiment；
Fig. 4 is the structural schematic diagram of another embodiment of chip-packaging structure of the present invention.
The embodiments will be further described with reference to the accompanying drawings for the realization, the function and the advantages of the object of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiment is only a part of the embodiments of the present invention, instead of all the embodiments.Base
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts it is all its
His embodiment, shall fall within the protection scope of the present invention.
It is to be appreciated that the description for being related to " first ", " second " etc. in the present invention is used for description purposes only, and cannot understand
For its relative importance of indication or suggestion or implicitly indicate the quantity of indicated technical characteristic.Define as a result, " first ",
The feature of " second " can explicitly or implicitly include at least one of the features.In addition, the "and/or" occurred in full text contains
Justice are as follows: including three schemes arranged side by side, by taking " A/B " as an example, including the scheme that A scheme or B scheme or A and B meet simultaneously, separately
Outside, the technical solution between each embodiment can be combined with each other, can be real with those of ordinary skill in the art but must be
Based on existing, the combination of this technical solution will be understood that not when conflicting or cannot achieve when occurs in the combination of technical solution
In the presence of, also not the present invention claims protection scope within.
The present invention proposes a kind of chip-packaging structure.
It is a kind of in the present embodiment as shown in FIG. 1, FIG. 1 is the structural schematic diagram of one embodiment of chip-packaging structure of the present invention
Chip-packaging structure includes wafer 10, metal pad 20 and multiple first conductive welding disks that 20 surrounding of metal pad is arranged in
30；
The wafer 10 is fixed on the metal pad 20 by colloid, and multiple first conductive welding disks 30 pass through gold
Belong to line 40 to be bonded with the wafer 10, first conductive welding disk 30 is provided with 26, multiple first conductive welding disks
30 with eight data pin DATAL0~DATAL7 of the wafer 10, five power pins VCCQ, VCCO, V50, V12 and
V33P, four chip select pin CE0~CE3, two differential signal pin DP and DM, read signal pin RD, write signal pin WR, number
According to latch pin ALE, code latches pin CLE, data strobe pin DQS, LED signal pin LED and be ready to/busy signal draws
Foot RB0 is correspondingly connected with, and the metal pad 20 is bonded by metal wire 40 with the wafer 10, the metal pad 20 with it is described
The grounding pin GND connection of wafer 10；
The wafer 10, the metal pad 20 and multiple first conductive welding disks 30 are (not shown by molding colloid
Overall package out).
In the present embodiment, wafer 10 is mainly the main control chip in memory device, and memory device mainly includes master control core
Piece, at least one flash memory, Chip-R and LED etc., wafer 10 be used to connect flash memory in memory device and external device with into
Row signal interaction, including signal read-write operation and storage.
As shown in Fig. 2, Fig. 2 is the structural schematic diagram of wafer 10 in chip-packaging structure first embodiment of the present invention, wafer
10 include 48 signal pins, including multiple chip select pin CE, multiple data pin DATAL, multiple grounding pin GND,
Multiple vacant pin NC, multiple common pin DATAH etc., wafer 10 is drawn multiple signal pins by multiple conductive welding disks,
And with the progress of QFN packaged type.
QFN is a kind of leadless packages, and square or rectangle, the central location of package bottom has a large area naked
Reveal pad, the encapsulation periphery around big pad is pad pin, since QFN encapsulation has sea unlike traditional QFP
Gull wing lead, the conductive path between internal pin and pad is short, and electrodynamic capacity and the intracorporal skirt resistance of encapsulation are very low, institute
To be capable of providing brilliant electrical property.
Wafer 10 is fixed on metal pad 20 by colloid, and metal pad 20 passes through gold for holding up wafer 10
Belong to line 40 to connect with a grounding pin GND of wafer 10, while playing heat sinking function, colloid can be used elargol or other
Material, the first conductive welding disk 30 that 20 periphery of metal pad is arranged in are acted on for welding, and copper sheet is passed through pressing mold, exposure, is shown
The first metal pad 20 and multiple first conductive welding disks 30 are generated after shadow, etching, stripping, plating, rubberizing processing.
In the present embodiment, the first conductive welding disk 30 is provided with 26, and correspondence is distributed in the four of metal pad 20
Week, and connect one by one by metal wire 40 with the corresponding pin of wafer 10, the two of the wafer 10 being connect with the first conductive welding disk 30
16 signal pins include eight data pin DATAL0~DATAL7, five power pins VCCQ, VCCO, V50, V12 and
V33P, four chip select pin CE0~CE3, two differential signal pin DP and DM, read signal pin RD, write signal pin WR, number
According to latch pin ALE, code latches pin CLE, data strobe pin DQS, LED signal pin LED and be ready to/busy signal draws
Foot RB0 is correspondingly connected with, and increases multiple chip select pin CE compared to SSOP-24, guarantee memory device can with multiple flash memories into
Row message reference is read, and compared to the connection that QFN-32 reduces common pin DATAH, is avoided adding unnecessary functional pin and be led
Design cost is caused to increase.
Eight data pin DATAL0~DATAL7 are used to carry out signal interaction with flash memory, five power pins VCCQ,
VCCO, V50, V12 and V33P include having multiple and different voltage class, can be adapted to more external equipments and provide electricity for flash memory
Source signal, four chip select pin CE0~CE3 can be connect with four flash memories and carry out selection access communication, and SSOP-24 encapsulation by
In a chip select pin CE0 can only be configured, is communicated so that selection access can only be carried out with single flash memory, lead to not realize wafer
10 global function piece choosing, two differential signals pin DP and DM are used to connect with external devices the transmission for realizing differential signal, read
The connection of the signal end of signal pins RD and write signal pin WR and flash memory carries out signal read-write, and data latch pin ALE and code
The signal end for latching pin CLE and flash memory is connected to carry out the latch of signal and the latch of code, and data strobe pin DQS is used for
Data transmission is controlled, LED signal pin LED is connect with the LED light of setting on the storage device, to control lighting, putting out for LED
It goes out or color change is to indicate the working condition of memory device, be ready to/busy signal pin RB0 is when being high level, expression can
To carry out data transmission, when be ready to/busy signal pin be low level when, expression state is busy not to accept the interview.
In the present embodiment, it is bonded respectively with wafer 10 by metal wire 40 in the first conductive welding disk 30 and metal pad 20
Afterwards, by forming colloid overall package, plastics, ceramics or other materials can be used.
Technical solution of the present invention by using include wafer 10, metal pad 20,20 surrounding of metal pad are set more
A first conductive welding disk, 30 compositing chip encapsulating structure, wafer 10 are fixed on metal pad 20 by colloid, and multiple first lead
Electrical bonding pads 30 are bonded by metal wire 40 with wafer 10, and the first conductive welding disk 30 is provided with 26, the multiple first conductive welderings
Eight data pin DATAL0~DATAL7 of disk 30 and wafer 10, five power pins VCCQ, VCCO, V50, V12 and
V33P, four chip select pin CE0~CE3, two differential signal pin DP and DM, read signal pin RD, write signal pin WR, number
According to latch pin ALE, code latches pin CLE, data strobe pin DQS, LED signal pin LED and be ready to/busy signal draws
Foot RB0 is correspondingly connected with, and metal pad 20 is bonded by metal wire 40 with wafer 10, the grounding pin of metal pad 20 and wafer 10
GND connection, and by molding colloid overall package, after chip-packaging structure is mounted on PCB, chip-packaging structure be can provide
Meet memory device and carry out the functional pin of signal interaction and read-write capability, and a variety of chip select functionalities can also be provided, and subtract
Few unnecessary general utility functions pin, to solve that SSOP-24 performance is not easy extension and QFN-32 encapsulation function is superfluous asks
Topic.
Further, the chip-packaging structure includes the first lateral margin, the second lateral margin, third lateral margin and the 4th lateral margin, more
A first conductive welding disk 30 is corresponding to be distributed in first lateral margin, second lateral margin, the third lateral margin and described the
On four lateral margins, each lateral margin intersection is provided with a vacancy area, at least one second conduction is provided in the vacancy area
Pad 50, second conductive welding disk 50 are bonded by metal wire 40 with the wafer 10 or integrated with the metal pad 20
Molding setting, second conductive welding disk 50 are connected with the grounding pin GND of the wafer 10 or corresponding signal pins.
In the present embodiment, the chip-packaging structure is in rectangular design, is respectively provided with multiple first on four lateral margins and leads
Electrical bonding pads 30, while the area that has vacant position is set in the lateral margin intersection of rectangle, at least one second conductive welding disk is set in the area of vacancy
50, the second conductive welding disk 50 can be connect by metal wire 40 with the other pins of wafer 10, such as the common pin of wafer 10
DATAH or vacant pin NC with metal pad 20 is designed to one to carry out extension or the second conductive welding disk 50 of performance
Body, and being connect simultaneously with the grounding pin GND of wafer 10, thus chip-packaging structure patch on PCB metal pad 20 with
Pcb board occur patch it is bad when, reliable grounding function is provided, the imperfect earth of wafer 10 is avoided the occurrence of.
Further, 50 quantity of the second conductive welding disk is four.
It, can also be each in order to further increase 10 extended capability of wafer or increase the Earthing Reliability of metal pad 20
Second conductive welding disk 50 is arranged in vacancy area, i.e., there are four the second conductive welding disks 50 for setting, and four the second conductive welding disks 50 were both
The signal pins of chip-packaging structure be can be used as but also as grounding pin GND, so that the function of improving chip-packaging structure is more
Sample or ground connection stability.
It, can also be by any two in 26 pins in one embodiment of chip-packaging structure in an alternative embodiment
Signal pins are arranged in the corresponding vacancy Liang Ge area, the settable grounding pin GND in other two vacancy area, or in chip package
On the basis of 26 pins in one embodiment of structure increase by four four functional pins, may be selected ground connection or with wafer 10
On other signal pins connection.
As shown in figure 3, Fig. 3 is the structural schematic diagram of the another embodiment of chip-packaging structure of the present invention, the chip package
Structure further includes third conductive welding disk (not shown go out) and the 4th conductive welding disk (not shown out), the third conductive welding disk and institute
It states the 4th conductive welding disk to bind by metal wire 40 and the wafer 10, the third conductive welding disk and the 4th conductive welding disk
It is correspondingly connected with respectively with the corresponding signal pins of the wafer 10 or grounding pin GND, the third conductive welding disk and described
4th conductive welding disk is correspondingly arranged on two opposite lateral margins.
In the present embodiment, in order to which the ground connection for further increasing 10 behavior extension ability of wafer or metal pad 20 is reliable
Property, it can also add a conductive welding disk again respectively on two opposite lateral margins, third conductive welding disk and the 4th conductive welding disk are equal
Identical as 30 structure of the first conductive welding disk, that is, the conductive welding disk quantity being arranged on lateral margin is 28, third conductive welding disk
It is connected with the 4th conductive welding disk by the remaining functional pin corresponding with wafer 10 of metal wire 40 to carry out the extension of performance, or
It is wholely set with metal pad 20, is further ensured that the ground connection stability of chip-packaging structure.
As shown in figure 4, Fig. 4 is the structure of another embodiment of chip-packaging structure of the present invention, the chip-packaging structure is also
Including the 5th conductive welding disk and the 6th conductive welding disk, the 5th conductive welding disk (not shown go out) and the 6th conductive welding disk
(not shown go out) is bound by metal wire 40 and the wafer 10, the 5th conductive welding disk and the 6th conductive welding disk difference
It is correspondingly connected with the corresponding signal pins of the wafer 10 or grounding pin GND, the 5th conductive welding disk and the described 6th
Conductive welding disk is correspondingly arranged on two opposite lateral margins.
In the present embodiment, one can be also added again respectively on two opposite lateral margins on the basis of above-mentioned fourth embodiment
A conductive welding disk, the 5th conductive welding disk and the 6th conductive welding disk are identical as 30 structure of the first conductive welding disk, that is, are arranged in lateral margin
On conductive welding disk quantity be 30, the 5th conductive welding disk and the 6th conductive welding disk are corresponding with wafer 10 by metal wire 40
Remaining functional pin is connected to carry out the extension of performance, or is wholely set with metal pad 20 to guarantee chip-packaging structure
Ground connection stability.
Optionally, the centre distance that two adjacent conductive welding disks of each lateral margin are arranged in is more than or equal to
0.35mm, and it is less than or equal to 0.45mm.
It is understood that the conductive welding disk being arranged on lateral margin should maintain a certain distance, distance is easily caused greatly very much
Apart from too small easily cause short-circuit danger occurs for the waste of cost, therefore, in this implementation, often between two neighboring conductive welding disk
Centre distance between one conductive welding disk between 0.35mm to 0.45, thus avoid occur short circuit and cost waste ask
Topic.
Optionally, the length of each conductive welding disk is more than or equal to 0.25mm and is less than or equal to 0.35mm,
The width of each conductive welding disk is more than or equal to 0.15mm and is less than or equal to 0.25mm.
Similarly, the size of each conductive welding disk should not be too large or too small, and conductive welding disk design size will cause greatly very much core
Chip package overall dimensions are bigger than normal, to cause the oversized of memory device, gold is then caused when conductive welding disk is undersized
Belong to line 40 be bonded difficulty, therefore, the Design of length of each conductive welding disk between 0.25mm and 0.35mm, each conductive welding disk
Width design is between 0.15 and 0.25mm.
Optionally, it is provided with down on a lateral margin of first conductive welding disk 30 of second conductive welding disk 50
Angle, the chamfering are more than or equal to 30 degree and are less than or equal to 60 degree.
It should be noted that being arranged in the second conductive welding disk 50 at adjacent side lip intersection, and the second conductive welding disk
50 with metal pad 20 when being integrally designed, in order to avoid the second conductive welding disk 50 and 20 junction of metal pad and adjacent conductive weld
When disk is because apart from too small generation short circuit, the conductive welding disk of 50 two sides of the second conductive welding disk is provided with chamfering, and guarantee is led with second
Electrical bonding pads 50 and metal pad 20 keep corresponding distance, avoid that short circuit risk occurs, and chamfering may be provided at 30 degree to 60
Between, best angle is 45 degree.
The present invention also proposes a kind of memory device, which includes chip-packaging structure, the chip-packaging structure
Specific structure is referring to above-described embodiment, since this memory device uses whole technical solutions of above-mentioned all embodiments,
At least all beneficial effects brought by the technical solution with above-described embodiment, this is no longer going to repeat them.
The above description is only a preferred embodiment of the present invention, is not intended to limit the scope of the invention, all at this
Under the inventive concept of invention, using equivalent structure transformation made by description of the invention and accompanying drawing content, or directly/use indirectly
It is included in other related technical areas in scope of patent protection of the invention.
Claims (9)
1. a kind of chip-packaging structure, which is characterized in that including wafer, metal pad and the metal pad surrounding is arranged in
Multiple first conductive welding disks；
The wafer is fixed on the metal pad by colloid, multiple first conductive welding disks by metal wire with it is described
Wafer bonding, first conductive welding disk are provided with 26, eight of multiple first conductive welding disks and the wafer
Data pin, five power pins, four chip select pins, two differential signal pins, read signal pin, write signal pin, number
According to latch pin, code latches pin, data strobe pin, LED signal pin and be ready to/busy signal pin is correspondingly connected with,
The metal pad is bonded by metal wire with the wafer, and the metal pad is connect with the grounding pin of the wafer；
The wafer, the metal pad and multiple first conductive welding disks pass through molding colloid overall package.
2. chip-packaging structure as described in claim 1, which is characterized in that the chip-packaging structure include the first lateral margin,
Second lateral margin, third lateral margin and the 4th lateral margin, multiple first conductive welding disks are corresponding to be distributed in first lateral margin, described the
On two lateral margins, the third lateral margin and the 4th lateral margin, each lateral margin intersection is provided with a vacancy area, the vacancy
Be provided at least one second conductive welding disk in area, second conductive welding disk be bonded by metal wire with the wafer or with
The metal pad is integrally formed setting, the grounding pin or residual signal pin of second conductive welding disk and the wafer
It is correspondingly connected with.
3. chip-packaging structure as claimed in claim 2, which is characterized in that the second conductive welding disk quantity is four.
4. chip-packaging structure as claimed in claim 3, which is characterized in that the chip-packaging structure further includes third conduction
Pad and the 4th conductive welding disk, the third conductive welding disk and the 4th conductive welding disk are tied up by metal wire and the wafer
It is fixed, the third conductive welding disk and the 4th conductive welding disk respectively with the residual signal pin or grounding pin of the wafer
It is correspondingly connected with, the third conductive welding disk and the 4th conductive welding disk are correspondingly arranged on two opposite lateral margins.
5. chip-packaging structure as claimed in claim 4, which is characterized in that the chip-packaging structure further includes the 5th conduction
Pad and the 6th conductive welding disk, the 5th conductive welding disk and the 6th conductive welding disk are tied up by metal wire and the wafer
It is fixed, the 5th conductive welding disk and the 6th conductive welding disk respectively with the residual signal pin or grounding pin of the wafer
It is correspondingly connected with, the 5th conductive welding disk and the 6th conductive welding disk are correspondingly arranged on two opposite lateral margins.
6. the chip-packaging structure as described in claim 1-5 any one, which is characterized in that be arranged in two of each lateral margin
The centre distance of the adjacent conductive welding disk is more than or equal to 0.35mm, and is less than or equal to 0.45mm.
7. the chip-packaging structure as described in claim 1-5 any one, which is characterized in that the length of each conductive welding disk
Degree is more than or equal to 0.25mm and is less than or equal to 0.35mm, and the width of each conductive welding disk is more than or equal to
0.15mm and be less than or equal to 0.25mm.
8. chip-packaging structure as claimed in claim 2, which is characterized in that close to the conduction of second conductive welding disk
Chamfering is provided on one lateral margin of pad, the chamfering is more than or equal to 30 degree and is less than or equal to 60 degree.
9. a kind of memory device, which is characterized in that including the chip-packaging structure as described in claim 1 to 8 any one.
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| CN110729252A (en) * | 2019-10-31 | 2020-01-24 | 中国电子科技集团公司第十三研究所 | 0.4 mm-pitch ceramic four-side lead flat shell and preparation method thereof |
| CN111367465A (en) * | 2018-12-26 | 2020-07-03 | 深圳市江波龙电子股份有限公司 | Control method of storage device, storage device and electronic device |
| CN112582286A (en) * | 2020-12-10 | 2021-03-30 | 青岛信芯微电子科技股份有限公司 | Packaging method, device, equipment and medium |
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| CN109037182B (en) | 2024-05-03 |
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