CN203644762U - Stereo packaging NAND FLASH memory with capacity of 4GX8bit - Google Patents
Stereo packaging NAND FLASH memory with capacity of 4GX8bit Download PDFInfo
- Publication number
- CN203644762U CN203644762U CN201320679014.1U CN201320679014U CN203644762U CN 203644762 U CN203644762 U CN 203644762U CN 201320679014 U CN201320679014 U CN 201320679014U CN 203644762 U CN203644762 U CN 203644762U
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- China
- Prior art keywords
- nand flash
- layer
- chip
- capacity
- flash memory
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- 238000004806 packaging method and process Methods 0.000 title abstract 4
- 238000005538 encapsulation Methods 0.000 claims description 20
- 150000001875 compounds Chemical class 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 5
- 239000010931 gold Substances 0.000 abstract description 5
- 229910052737 gold Inorganic materials 0.000 abstract description 5
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 abstract 5
- 241000446313 Lamella Species 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Semiconductor Memories (AREA)
Abstract
The utility model relates to a stereo packaging NAND FLASH memory with capacity of 4GX8bit; the stereo packaging NAND FLASH memory comprises eight 512M X 8bit NAND FLASH chips, a lead wire framework layer piled from top to bottom, and eight chip layers; the lead wire framework layer is provided with pins used for connecting outside; the eight NAND FLASH chips are respectively placed on the eight chip layers; the piled lead wire framework layer and eight chip layers are embedded and cut so as to expose electric connecting pins on a periphery, and a gold plated connecting line is arranged on an outer surface; the gold plated connecting line can correspondingly connect the electric connecting pins exposed from the lead wire framework and eight chip layers; the pins of the lead wire framework layer can be used as physical connecting objects for external access signals and external output signals. The stereo packaging NAND FLASH memory with capacity of 4GX8bit can relatively reduce occupied plane space of a printed circuit board.
Description
[technical field]
The utility model relates to memory device, and relating in particular to a kind of capacity is the three-dimensional encapsulation NAND FLASH memory of 4G × 8bit.
[background technology]
At present, on a lot of printed circuit board (PCB)s (PCB), all need to be equipped with NAND FLASH storage chip, due to the finite capacity of each NAND FLASH storage chip, if be to use very large NAND FLASH memory space in a certain application, will expand so the area of printed circuit board (PCB), then post multiple NAND FLASH storage chips in the above.
Due at some particular places, use the shared plane space of equipment of printed circuit board (PCB) to have certain restriction to some, may just need to reduce the area of plane of printed circuit board (PCB); Like this, relative difficult ground expands the memory space on NAND FLASH printed circuit board (PCB) (PCB).
[utility model content]
The technical problems to be solved in the utility model is to provide the three-dimensional encapsulation NAND FLASH memory that a kind of capacity is 4G × 8bit, and it can reduce the plane space that takies printed circuit board (PCB) relatively.
Above-mentioned technical problem is achieved through the following technical solutions:
The three-dimensional encapsulation NAND FLASH memory that a kind of capacity is 4G × 8bit, it is characterized in that, comprise the NAND FLASH chip of eight 512M × 8bit, carry out from bottom to up stacking a lead frame rack-layer and eight chip layer, lead frame rack-layer is provided with the pin connecting for externally, and eight NAND FLASH chips are located at correspondingly respectively and are put in eight chip layer; Described stacking a lead frame rack-layer and eight chip layer are exposed electrical connection pin after embedding, cutting on periphery, and are provided with gold-plated connecting line at outer surface; Gold-plated connecting line carries out correspondence by a described lead frame rack-layer with the electrical connection pin exposing in eight chip layer and is connected, and the pin of lead frame rack-layer is the physical connection thing with external output signal as external access signal.
It is that 512Mb, data-bus width are the encapsulation NAND FLASH chip of 8,48 pins that described NAND FLASH chip all adopts memory capacity.
The data wire of described eight NAND FLASH chips is compound, the reading signal lines of eight NAND FLASH chips, write signal line, write-protect line, address latch signal line juxtaposition.
Between NAND FLASH chip by eight 512M × 8bit, connect into capacity and be the technology that the technology of the NAND FLASH memory of 4G × 8bit can adopt the art personnel conventionally to grasp, primary creation point of the present utility model is to utilize eight chip layer to put NAND FLASH chip, then by gold-plated connecting line being set putting eight chip layer of chip and the pin wiring of a lead frame rack-layer connects into a NAND FLASH memory at outer surface after stacking, embedding, cutting.Visible, the logical three-dimensional encapsulation mode of the utility model avoids carrying out all NAND FLASH of juxtaposition chip in a chip layer, reduce the plane space that takies printed circuit board (PCB), thereby reduced the plane space of printed circuit board (PCB), be especially applicable to being applied to Aeronautics and Astronautics field.Annexation between the NAND FLASH chip of eight 512M × 8bit of the application self design that the utility model is further concrete.
[accompanying drawing explanation]
Fig. 1 is the sectional view of the present utility model of embodiment mono-;
Fig. 2 is eight NAND FLASH chip connection diagrams of the present utility model of embodiment mono-.
[embodiment]
Embodiment mono-
As depicted in figs. 1 and 2, the three-dimensional encapsulation NAND FLASH memory that a kind of capacity that the present embodiment provides is 4G × 8bit, comprise and carry out from bottom to up a stacking lead frame rack-layer and eight chip layer: one is provided with the lead frame rack-layer 1 of the pin 11 for being externally connected, one is pasted with the first chip layer 2 of NAND FLASH chip 21, one is pasted with the second chip layer 3 of NAND FLASH chip 31, one is pasted with the 3rd chip layer 4 of NAND FLASH chip 41, one is pasted with the four-core lamella 5 of NAND FLASH chip 51, one is pasted with the 5th chip layer 6 of NAND FLASH chip 61, one is pasted with the 6th chip layer 7 of NAND FLASH chip 71, one is pasted with the 7th chip layer 8 of NAND FLASH chip 81, one is pasted with the 8th chip layer 9 of NAND FLASH chip 91, it is that 512Mb, data-bus width are the encapsulation NAND FLASH chip of the TSOP-48 (48 pins) of 8 that NAND FLASH chip 21,31,41,51,61,71,81,91 all adopts memory capacity, stacking a lead frame rack-layer and eight chip layer are exposed electrical connection pin after embedding, cutting on periphery, and are provided with gold-plated connecting line at outer surface, gold-plated connecting line carries out lead frame rack-layer and the electrical connection pin exposing in chip layer corresponding be connected to form a memory capacity and reach 32Gb, data-bus width to reach 08, pin package be TSOP-50(50 pin) the three-dimensional encapsulation NAND FLASH memory of encapsulation, the pin 11 of lead frame rack-layer 1 is as the external access signal of three-dimensional encapsulation NAND FLASH memory and the physical connection thing of external output signal.
Wherein, the data wire of eight NAND FLASH chips is compound, the #RE reading signal lines of eight NAND FLASH chips, #WE write signal line, #WP write-protect line, ALE address latch signal line juxtaposition.
Lead frame rack-layer and eight chip layer can adopt printed circuit board (PCB).
The preparation process of above-mentioned three-dimensional encapsulation NAND FLASH memory is as follows:
(1) pin 11 is welded in lead frame rack-layer 1; NAND FLASH chip 21,31,41,51,61,71,81,91 is arranged on respectively in chip layer 2,3,4,5,6,7,8,9 accordingly;
(2) lead frame rack-layer 1, the first chip layer 2, the second chip layer 3, the 3rd chip layer 4, four-core lamella 5, the 5th chip layer 6, the 6th chip layer 7, the 7th chip layer 8, the 8th chip layer 9 are carried out stacking from bottom to up;
(3) use epoxy resin to carry out embedding to a lead frame rack-layer and eight chip layer, a lead frame rack-layer and eight chip layer after embedding are cut, to allow a lead frame rack-layer and eight chip layer expose electrical connection pin on periphery separately;
(4) a lead frame rack-layer and eight chip layer are carried out to surface gold-plating to form Gold plated Layer, now, the electrical connection pin that Gold plated Layer is exposed on periphery separately with eight chip layer is connected, and all interconnects and also connect pin simultaneously between the electrical connection pin exposing;
(5) for the signal node this separation separates, Gold plated Layer is carried out to surperficial line engraving to form gold-plated connecting line, gold-plated connecting line carries out lead frame rack-layer and the electrical connection pin exposing in chip layer corresponding be connected to form a memory capacity and reach 32Gb, data-bus width to reach 8, pin package be TSOP-50(50 pin) the three-dimensional encapsulation NAND FLASH memory of encapsulation, the pin 11 of lead frame rack-layer 1 is as the external access signal of three-dimensional encapsulation NAND FLASH memory and the physical connection thing of external output signal.
The concrete purposes of each pin of this three-dimensional encapsulation NAND FLASH memory is as table 1.
The concrete purposes of table 1 pin
The utility model is not limited to above-described embodiment, based on simple replacement above-described embodiment, that do not make creative work, should belong to the scope that the utility model discloses.
Claims (3)
1. the three-dimensional encapsulation NAND FLASH memory that capacity is 4G × 8bit, it is characterized in that, comprise the NAND FLASH chip of eight 512M × 8bit, carry out from bottom to up stacking a lead frame rack-layer and eight chip layer, lead frame rack-layer is provided with the pin connecting for externally, and eight NAND FLASH chips are located at respectively in eight chip layer correspondingly; Described stacking a lead frame rack-layer and eight chip layer are exposed electrical connection pin after embedding, cutting on periphery, and are provided with gold-plated connecting line at outer surface; Gold-plated connecting line carries out correspondence by a described lead frame rack-layer with the electrical connection pin exposing in eight chip layer and is connected, and the pin of lead frame rack-layer is the physical connection thing with external output signal as external access signal.
2. the three-dimensional encapsulation NAND FLASH memory that a kind of capacity according to claim 1 is 4G × 8bit, it is characterized in that, it is that 512Mb, data-bus width are the encapsulation NAND FLASH chip of 8,48 pins that described NAND FLASH chip all adopts memory capacity.
3. the three-dimensional encapsulation NAND FLASH memory that is 4G × 8bit according to a kind of capacity described in claim 1 to 2 any one is characterized in that; the data wire of described eight NAND FLASH chips is compound, the reading signal lines of eight NAND FLASH chips, write signal line, write-protect line, address latch signal line juxtaposition.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320679014.1U CN203644762U (en) | 2013-10-30 | 2013-10-30 | Stereo packaging NAND FLASH memory with capacity of 4GX8bit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320679014.1U CN203644762U (en) | 2013-10-30 | 2013-10-30 | Stereo packaging NAND FLASH memory with capacity of 4GX8bit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203644762U true CN203644762U (en) | 2014-06-11 |
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ID=50875987
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320679014.1U Expired - Lifetime CN203644762U (en) | 2013-10-30 | 2013-10-30 | Stereo packaging NAND FLASH memory with capacity of 4GX8bit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203644762U (en) |
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2013
- 2013-10-30 CN CN201320679014.1U patent/CN203644762U/en not_active Expired - Lifetime
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140611 |
|
| CX01 | Expiry of patent term |