CN203423171U

CN203423171U - Three-dimensional packaged SDRAM having 2M*8bit capacity

Info

Publication number: CN203423171U
Application number: CN201320385621.7U
Authority: CN
Inventors: 王烈洋; 叶振荣; 黄小虎; 蒋晓华; 颜军
Original assignee: ZHUHAI ORBITA CONTROL ENGINEERING Co Ltd
Current assignee: ZHUHAI ORBITA CONTROL ENGINEERING Co Ltd
Priority date: 2013-06-30
Filing date: 2013-06-30
Publication date: 2014-02-05
Anticipated expiration: 2023-06-30

Abstract

The utility model relates to a three-dimensional packaged SDRAM (Synchronous Dynamic Random Access memory) having a 2M*8bit capacity. The three-dimensional packaged SDRAM includes four SDRAM chips having a capacity of 512K*8bit each, and also includes a lead frame layer and four chip layers piled from bottom up. The lead frame layer is provided with pins used for external connection and the four SRAM chips are arranged on the four chip layers in a one-to-one corresponding manner. Electric connection pins are exposed on the periphery of the lead frame layer and the four chip layers being encapsulated and cut and outer surfaces of the lead frame layer and the four chip layers are provided with gold-plating connection lines. The gold-plating connection lines perform corresponding connection of the electric connection pins exposed on the lead frame layer and the four chip layers. The pins serve as physic connectors for external access signals and external output signals of the three-dimensional packaged SDRAM. By adopting the three-dimensional packaged SDRAM, occupancy of plane space of a printed circuit board can be reduced comparatively.

Description

A kind of capacity is the three-dimensional encapsulation mram memory of 2M * 8bit

[technical field]

The utility model relates to memory device, and relating in particular to a kind of capacity is the three-dimensional encapsulation mram memory of 2M * 8bit.

[background technology]

At present, on a lot of printed circuit board (PCB)s (PCB), all need to be equipped with MRAM chip (MRAM: magnetic resistance type random data memory), finite capacity due to each MRAM storage chip, if be to use very large MRAM memory space in a certain application, will expand the area of printed circuit board (PCB) so, then post a plurality of MRAM chips in the above.

Due at some particular places, to some, use the shared plane space of equipment of printed circuit board (PCB) to have certain restriction, may just need to reduce the area of plane of printed circuit board (PCB); Like this, relative difficult ground expands the memory space on MRAM printed circuit board (PCB) (PCB).

[utility model content]

The technical problems to be solved in the utility model is to provide the three-dimensional encapsulation mram memory that a kind of capacity is 2M * 8bit, and it can reduce the plane space that takies printed circuit board (PCB) relatively.

Above-mentioned technical problem is achieved through the following technical solutions:

A kind of capacity is the three-dimensional encapsulation mram memory of 2M * 8bit, comprise the MRAM chip that four capacity are 512K * 8bit, it is characterized in that, also comprise and carry out from bottom to up stacking a lead frame rack-layer and four chip layer, lead frame rack-layer is provided with the pin connecting for externally, and four MRAM chips are arranged on respectively in four chip layer correspondingly; Described stacking a lead frame rack-layer and four chip layer are exposed electrical connection pin after embedding, cutting on periphery, and are provided with gold-plated connecting line at outer surface; Gold-plated connecting line carries out corresponding connection by the electrical connection pin exposing in a described lead frame rack-layer and four chip layer, and the pin of lead frame rack-layer is the physical connection thing with external output signal as external access signal.

The data/address bus of described four MRAM chips, address wire, reading signal lines, write signal line are distinguished compound, the chip selection signal juxtaposition of described four MRAM chips.

The technology that connects into capacity between the MRAM chip that is 512K * 8bit by four capacity and be the mram memory of 2M * 8bit belongs to the technology that the art personnel grasp conventionally, creation point of the present utility model is that the utility model utilizes four storing chip layer to put MRAM chip, then by stacking, embedding, after cutting, at outer surface, gold-plated connecting line is set putting four chip layer of chip and the pin wiring of a lead frame rack-layer connects into a three-dimensional encapsulation mram memory, logical three-dimensional encapsulation mode avoids carrying out all MRAM chips of juxtaposition in a chip layer, reduced the plane space that takies printed circuit board (PCB), thereby reduced the plane space of printed circuit board (PCB), especially be applicable to being applied to aviation, space industry.

[accompanying drawing explanation]

Fig. 1 is sectional view of the present utility model;

Fig. 2 is four MRAM chip connection diagrams of the present utility model.

[embodiment]

As depicted in figs. 1 and 2, a kind of three-dimensional encapsulation mram memory that the present embodiment provides, comprise the lead frame rack-layer 1 of carrying out from bottom to up a stacking lead frame rack-layer and four chip layer 2,3,4, being provided with the pin 11 for being externally connected at 5:, one is pasted with the chip layer 2 of MRAM chip 21, one is pasted with the chip layer 3 of MRAM chip 31, one chip layer 4, that is pasted with MRAM chip 41 is pasted with the chip layer 5 of MRAM chip 51; The encapsulation MRAM chip of

MRAM chip

21,31,41,51 TSOP-44 that all employing capacity is 512K * 8bit (44 pins); Stacking a lead frame rack-layer and four chip layer are exposed electrical connection pin after embedding, cutting on periphery, and are provided with gold-plated connecting line at outer surface; Gold-plated connecting line carries out corresponding connection by the electrical connection pin exposing in chip layer take and form a capacity and reach the three-dimensional encapsulation mram memory that 16M * 8bit, pin package are SOP-54 (54 pins) encapsulation, and the pin 11 of lead frame rack-layer 1 is as the external access signal of three-dimensional encapsulation mram memory and the external physical connection thing of output signal.

Wherein, the data/address bus of four MRAM chips, address wire, reading signal lines, write signal line are distinguished compound, the chip selection signal line juxtaposition of four MRAM chips.

Lead frame rack-layer and four chip layer can adopt printed circuit board (PCB).

The preparation process of above-mentioned three-dimensional encapsulation mram memory is as follows:

(1) pin 11 is welded in lead frame rack-layer 1;

MRAM chip

21,31,41,51 is arranged on accordingly respectively and is put in chip layer 2,3,4,5;

(2) lead frame rack-layer 1, the first chip layer 2, the second chip layer 3, the 3rd chip layer 4, four-core lamella 5 are carried out stacking from bottom to up;

(3) use epoxy resin to carry out embedding to a lead frame rack-layer and four chip layer, a lead frame rack-layer and four chip layer after embedding are cut, to allow a lead frame rack-layer and four chip layer expose electrical connection pin on periphery separately;

(4) a lead frame rack-layer and four chip layer are carried out to surface gold-plating to form Gold plated Layer, now, the electrical connection pin that Gold plated Layer is exposed on periphery separately with four chip layer is connected, and all interconnects and also connect pin simultaneously between the electrical connection pin exposing;

(5) for this separated signal node is separated, Gold plated Layer is carried out to surperficial line engraving to form gold-plated connecting line, gold-plated connecting line carries out corresponding connection by the electrical connection pin exposing in lead frame rack-layer and chip layer take and form a capacity and reach the three-dimensional encapsulation mram memory that 16M * 8bit, pin package are SOP-54 (54 pins) encapsulation, and the pin 11 of lead frame rack-layer 1 is as the external access signal of three-dimensional encapsulation mram memory and the external physical connection thing of output signal.

The concrete purposes of 54 pins of this three-dimensional encapsulation mram memory is as table 1.

The concrete purposes of table 1 pin

The utility model is not limited to above-described embodiment, based on simple replacement above-described embodiment, that do not make creative work, should belong to the scope that the utility model discloses.

Claims

1. the three-dimensional encapsulation mram memory that capacity is 2M * 8bit, comprise the MRAM chip that four capacity are 512K * 8bit, it is characterized in that, also comprise and carry out from bottom to up stacking a lead frame rack-layer and four chip layer, lead frame rack-layer is provided with the pin connecting for externally, and four MRAM chips are arranged on respectively in four chip layer correspondingly; Described stacking a lead frame rack-layer and four chip layer are exposed electrical connection pin after embedding, cutting on periphery, and are provided with gold-plated connecting line at outer surface; Gold-plated connecting line carries out corresponding connection by the electrical connection pin exposing in a described lead frame rack-layer and four chip layer, and the pin of lead frame rack-layer is the physical connection thing with external output signal as external access signal.

2. the three-dimensional encapsulation mram memory that a kind of capacity according to claim 1 is 2M * 8bit, it is characterized in that, the data/address bus of described four MRAM chips, address wire, reading signal lines, write signal line are distinguished compound, the chip selection signal juxtaposition of described four MRAM chips.