CN203423174U - Three-dimensional packaged SDRAM having 512M*32bit capacity - Google Patents

Abstract

The utility model relates to a three-dimensional packaged SDRAM (Synchronous Dynamic Random Access memory) having a 512M*32bit capacity. The three-dimensional packaged SDRAM includes four SDRAM chips having a capacity of 256K*16bit each, and also includes a lead frame layer and four chip layers piled from bottom up. The four SDRAM chips include the first SRAM chip, the second SRAM chip, the third SRAM chip and the fourth SRAM chip. The lead frame layer is provided with pins used for external connection and each of the chip layers receives one of the SRAM chips. Electric connection pins are exposed on the periphery of the lead frame layer and the four chip layers being encapsulated and cut and outer surfaces of the lead frame layer and the four chip layers are provided with gold-plating connection lines. The gold-plating connection lines perform corresponding connection of the electric connection pins exposed on the lead frame layer and the four chip layers. The pins serve as physic connectors for external access signals and external output signals of the three-dimensional packaged SDRAM. By adopting the three-dimensional packaged SDRAM, occupancy of plane space of a printed circuit board can be reduced comparatively.

Description

A kind of capacity is the three-dimensional encapsulation SRAM memory of 512K * 32bit

[technical field]

The utility model relates to memory device, and relating in particular to a kind of capacity is the three-dimensional encapsulation SRAM memory of 512K * 32bit.

[background technology]

At present, on a lot of printed circuit board (PCB)s (PCB), all need to be equipped with sram chip (SRAM: static random data storage), finite capacity due to each SRAM storage chip, if be to use very large SRAM memory space in a certain application, will expand the area of printed circuit board (PCB) so, then post a plurality of sram chips in the above.

Due at some particular places, to some, use the shared plane space of equipment of printed circuit board (PCB) to have certain restriction, may just need to reduce the area of plane of printed circuit board (PCB); Like this, relative difficult ground expands the memory space on SRAM printed circuit board (PCB) (PCB).

[utility model content]

The technical problems to be solved in the utility model is to provide the three-dimensional encapsulation SRAM memory that a kind of capacity is 512K * 32bit, and it can reduce the plane space that takies printed circuit board (PCB) relatively.

Above-mentioned technical problem is achieved through the following technical solutions:

Be a three-dimensional encapsulation SRAM memory of 512K * 32bit, comprise the sram chip that four capacity are 256K * 16bit: the first sram chip, the second sram chip, Three S's RAM chip, the 4th sram chip; Also comprise and carry out from bottom to up stacking a lead frame rack-layer and four chip layer, lead frame rack-layer is provided with the pin connecting for externally, puts a described sram chip in each chip layer; Described stacking a lead frame rack-layer and four chip layer are exposed electrical connection pin after embedding, cutting on periphery, and are provided with gold-plated connecting line at outer surface; Gold-plated connecting line carries out corresponding connection by the electrical connection pin exposing in a described lead frame rack-layer and four chip layer, and the pin of lead frame rack-layer is as the external access signal of three-dimensional encapsulation SRAM memory and the physical connection thing of external output signal.

The address wire of four sram chips, reading signal lines, write signal line are corresponding compound respectively; The data/address bus of the first sram chip, the second sram chip is compound, and the data/address bus of Three S's RAM chip, the 4th sram chip is compound; The chip selection signal line of the first sram chip, Three S's RAM chip is compound, and the chip selection signal line of the second sram chip, the 4th sram chip is compound.

The capacity that connects between the sram chip that is 256K * 16bit by four capacity is that the technology of the SRAM memory of 512K * 32bit belongs to the technology that the art personnel grasp conventionally, creation point of the present utility model is to utilize four chip layer to put sram chip, then by stacking, embedding, after cutting, at outer surface, gold-plated connecting line is set putting four chip layer of chip and the pin wiring of a lead frame rack-layer connects into a three-dimensional encapsulation SRAM memory, by three-dimensional encapsulation mode, avoid carrying out all sram chips of juxtaposition in a chip layer, reduced the plane space that takies printed circuit board (PCB), thereby reduced the plane space of printed circuit board (PCB), especially be applicable to being applied to aviation, space industry.

[accompanying drawing explanation]

Fig. 1 is sectional view of the present utility model;

Fig. 2 is four sram chip connection diagrams of the present utility model.

[embodiment]

As depicted in figs. 1 and 2, the three-dimensional encapsulation SRAM memory that a kind of capacity that the present embodiment provides is 512K * 32bit, comprise and carry out from bottom to up a stacking lead frame rack-layer and four chip layer: one is provided with the lead frame rack-layer 1 of the pin 11 for being externally connected, one is pasted with the chip layer 2 of the first sram chip 21, one is pasted with the chip layer 3 of the second sram chip 31, one chip layer 4, that is pasted with Three S's RAM chip 41 is pasted with the chip layer 5 of the 4th sram chip 51; It is the encapsulation sram chip of 256K * 16bit, TSOP-44 (44 pins) that four sram chips 21,31,41,51 all adopt memory capacity; Stacking a lead frame rack-layer and four chip layer are exposed electrical connection pin after embedding, cutting on periphery, and are provided with gold-plated connecting line at outer surface; Gold-plated connecting line by the electrical connection pin exposing in lead frame rack-layer and chip layer carry out corresponding connection take form a capacity as 512K * 32bit, pin package be the three-dimensional encapsulation SRAM memory of SOP-64 (64 pins) encapsulation, the pin 11 of lead frame rack-layer 1 is as the external access signal of three-dimensional encapsulation SRAM memory and the external physical connection thing of output signal.

Wherein, the address wire of four sram chips, reading signal lines, write signal line are corresponding compound respectively; The data/address bus of the first sram chip 21, the second sram chip 31 is compound, and the data/address bus of Three S's RAM chip 41, the 4th sram chip 51 is compound; The chip selection signal line of the first sram chip 21, Three S's RAM chip 41 is compound, and the chip selection signal line of the second sram chip 31, the 4th sram chip 51 is compound.

Lead frame rack-layer and four chip layer can adopt printed circuit board (PCB).

The preparation process of above-mentioned three-dimensional encapsulation SRAM memory is as follows:

(1) pin 11 is welded in lead frame rack-layer 1; The first sram chip 21, the second sram chip 31, Three S's RAM chip 41, the 4th sram chip 51 are arranged on respectively in chip layer 2,3,4,5 accordingly;

(2) lead frame rack-layer 1, chip layer 2, chip layer 3, chip layer 4, chip layer 5 are carried out stacking from bottom to up;

(3) use epoxy resin to carry out embedding to a lead frame rack-layer and four chip layer, a lead frame rack-layer and four chip layer after embedding are cut, to allow a lead frame rack-layer and four chip layer expose electrical connection pin on periphery separately;

(4) a lead frame rack-layer and four chip layer are carried out to surface gold-plating to form Gold plated Layer, now, the electrical connection pin that Gold plated Layer is exposed on periphery separately with four chip layer is connected, and all interconnects and also connect pin simultaneously between the electrical connection pin exposing;

(5) for this separated signal node is separated, Gold plated Layer is carried out to surperficial line engraving to form gold-plated connecting line, gold-plated connecting line by the electrical connection pin exposing in lead frame rack-layer and chip layer carry out corresponding connection take form a capacity as 512K * 32bit, pin package be the three-dimensional encapsulation SRAM memory of SOP-64 (64 pins) encapsulation, the pin 11 of lead frame rack-layer 1 is as the external access signal of three-dimensional encapsulation SRAM memory and the external physical connection thing of output signal.

The concrete purposes of 64 pins of this three-dimensional encapsulation SRAM memory is as table 1.

The concrete purposes of table 1 pin

The utility model is not limited to above-described embodiment, based on simple replacement above-described embodiment, that do not make creative work, should belong to the scope that the utility model discloses.

Claims (2)

1. the three-dimensional encapsulation SRAM memory that capacity is 512K * 32bit, comprises the sram chip that four capacity are 256K * 16bit: the first sram chip, the second sram chip, Three S's RAM chip, the 4th sram chip; It is characterized in that, also comprise and carry out from bottom to up stacking a lead frame rack-layer and four chip layer, lead frame rack-layer is provided with the pin connecting for externally, puts a described sram chip in each chip layer; Described stacking a lead frame rack-layer and four chip layer are exposed electrical connection pin after embedding, cutting on periphery, and are provided with gold-plated connecting line at outer surface; Gold-plated connecting line carries out corresponding connection by the electrical connection pin exposing in a described lead frame rack-layer and four chip layer, and the pin of lead frame rack-layer is as the external access signal of three-dimensional encapsulation SRAM memory and the physical connection thing of external output signal.

2. the three-dimensional encapsulation SRAM memory that a kind of capacity according to claim 1 is 512K * 32bit, is characterized in that, the address wire of four sram chips, reading signal lines, write signal line are corresponding compound respectively; The data/address bus of the first sram chip, the second sram chip is compound, and the data/address bus of Three S's RAM chip, the 4th sram chip is compound; The chip selection signal line of the first sram chip, Three S's RAM chip is compound, and the chip selection signal line of the second sram chip, the 4th sram chip is compound.

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