CN203644765U - Three-dimensional packaging EEPROM memory with capacity of 256Kx32bit - Google Patents
Three-dimensional packaging EEPROM memory with capacity of 256Kx32bit Download PDFInfo
- Publication number
- CN203644765U CN203644765U CN201320682871.7U CN201320682871U CN203644765U CN 203644765 U CN203644765 U CN 203644765U CN 201320682871 U CN201320682871 U CN 201320682871U CN 203644765 U CN203644765 U CN 203644765U
- Authority
- CN
- China
- Prior art keywords
- chip
- eeprom
- layer
- lead frame
- eeprom chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004806 packaging method and process Methods 0.000 title abstract 2
- 150000001875 compounds Chemical class 0.000 claims description 21
- 238000005538 encapsulation Methods 0.000 claims description 20
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 5
- 239000010931 gold Substances 0.000 abstract description 5
- 229910052737 gold Inorganic materials 0.000 abstract description 5
- 238000007747 plating Methods 0.000 abstract description 3
- 238000007789 sealing Methods 0.000 abstract 1
- 241000446313 Lamella Species 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The utility model relates to a three-dimensional packaging EEPROM memory with capacity of 256Kx32bit. The memory is characterized by comprising eight 128Kx8bit EEPROM chips, and a lead frame layer and eight chip layers which are stacked from bottom up. The lead frame layer is provided with pins used for external connection. The eight EEPROM chips are respectively disposed on the eight chip layers in a one-to-one manner. Electrical connection pins are exposed from the periphery of the stacked lead frame layer and the eight chip layers after the lead frame layer and the eight chip layers are processed by filling and sealing and cutting, and an outer surface is provided with gold plating connecting lines. The gold plating connecting lines correspondingly connect the electrical connection pins which are exposed from the lead frame layer and the eight chip layers. The pins of the lead frame layer are used as physical connection objects for external access signals and external output signals. The EEPROM memory can relatively reduce plane space of a printed circuit board.
Description
[technical field]
The utility model relates to memory device, and relating in particular to a kind of capacity is 256K × 32bit three-dimensional encapsulation eeprom memory.
[background technology]
At present, on a lot of printed circuit board (PCB)s (PCB), all need to be equipped with EEPROM storage chip, due to the finite capacity of each EEPROM storage chip, if be to use very large EEPROM memory space in a certain application, will expand so the area of printed circuit board (PCB), then post multiple EEPROM storage chips in the above.
Due at some particular places, use the shared plane space of equipment of printed circuit board (PCB) to have certain restriction to some, may just need to reduce the area of plane of printed circuit board (PCB); Like this, relative difficult ground expands the memory space on EEPROM printed circuit board (PCB) (PCB).
[utility model content]
It is 256K × 32bit three-dimensional encapsulation eeprom memory that the technical problems to be solved in the utility model is to provide a kind of capacity, and it can reduce the plane space that takies printed circuit board (PCB) relatively.
Above-mentioned technical problem is achieved through the following technical solutions:
The three-dimensional encapsulation eeprom memory that a kind of capacity is 256K × 32bit, it is characterized in that, comprise the eeprom chip of eight 128K × 8bit, also comprise and carry out from bottom to up stacking a lead frame rack-layer and eight chip layer, lead frame rack-layer is provided with the pin connecting for externally, and eight eeprom chips are arranged on respectively in eight chip layer correspondingly; Described stacking a lead frame rack-layer and eight chip layer are exposed electrical connection pin after embedding, cutting on periphery, and are provided with gold-plated connecting line at outer surface; The electrical connection pin exposing in a described lead frame rack-layer and eight chip layer is carried out corresponding connection by gold-plated connecting line, and the pin of lead frame rack-layer is the physical connection thing with external output signal as external access signal.
OE reading signal lines, the WE write signal line of eight eeprom chips are corresponding compound respectively; The chip selection signal line of the first eeprom chip, the second eeprom chip, the 3rd eeprom chip, the 4th eeprom chip is compound, and the chip selection signal line of the 5th eeprom chip, the 6th eeprom chip, the 7th eeprom chip, the 8th eeprom chip is compound; The data wire of the data wire of the first eeprom chip and the 5th eeprom chip is compound; The data wire of the data wire of the second eeprom chip and the 6th eeprom chip is compound; The data wire of the data wire of the 3rd eeprom chip and the 7th eeprom chip is compound; The data wire of the data wire of the 4th eeprom chip and the 8th eeprom chip is compound.
It is that 128Kb, data-bus width are the encapsulation eeprom chip of the TSOP-32 of 8 that described eeprom chip adopts memory capacity.
The capacity that connects between eeprom chip by eight 128K × 8bit is the technology that the technology of the eeprom memory of 256K × 32bit can adopt the art personnel conventionally to grasp, primary creation point of the present utility model is to utilize eight chip layer to put eeprom chip, then by gold-plated connecting line being set putting eight chip layer of chip and the pin wiring of a lead frame rack-layer connects into an eeprom memory at outer surface after stacking, embedding, cutting.Visible, the logical three-dimensional encapsulation mode of the utility model avoids carrying out all eeprom chips of juxtaposition in a chip layer, reduce the plane space that takies printed circuit board (PCB), thereby reduced the plane space of printed circuit board (PCB), be especially applicable to being applied to Aeronautics and Astronautics field.Annexation between the eeprom chip of eight 128K × 8bit of the application self design that the utility model is further concrete.
[accompanying drawing explanation]
Fig. 1 is the sectional view of the present utility model of embodiment mono-;
Fig. 2 is the internal structure schematic diagram of the present utility model of embodiment mono-.
[embodiment]
Embodiment mono-
As depicted in figs. 1 and 2, a kind of capacity that the present embodiment provides is 256K × 32bit three-dimensional encapsulation eeprom memory, comprise and carry out from bottom to up a stacking lead frame rack-layer and eight chip layer: one is provided with the lead frame rack-layer 1 of the pin 11 for being externally connected, one is pasted with the first chip layer 2 of the first eeprom chip 21, one is pasted with the second chip layer 3 of the second eeprom chip 31, one is pasted with the 3rd chip layer 4 of the 3rd eeprom chip 41, one is pasted with the four-core lamella 5 of the 4th eeprom chip 51, one is pasted with the 5th chip layer 6 of the 5th eeprom chip 61, one is pasted with the 6th chip layer 7 of the 6th eeprom chip 71, one is pasted with the 7th chip layer 8 of the 7th eeprom chip 81, one is pasted with the 8th chip layer 9 of the 8th eeprom chip 91, it is that 128Kb, data-bus width are the encapsulation eeprom chip of the TSOP-32 (32 pins) of 8 that eeprom chip 21,31,41,51,61,71,81,91 all adopts memory capacity, stacking a lead frame rack-layer and eight chip layer are exposed electrical connection pin after embedding, cutting on periphery, and are provided with gold-plated connecting line at outer surface, gold-plated connecting line carries out associated connection by lead frame rack-layer and the electrical connection pin exposing in chip layer and reaches 8Mb, data-bus width and reach 32, pin package as SOP-64(64 pin to form a memory capacity) the three-dimensional encapsulation eeprom memory of encapsulation: eight eeprom chips become to be connected in parallel, and the pin 11 of lead frame rack-layer 1 is as the external access signal of three-dimensional encapsulation eeprom memory and the physical connection thing of external output signal.
Wherein, the OE reading signal lines of eight eeprom chips, WE write signal line are corresponding compound respectively; The chip selection signal line of the first eeprom chip, the second eeprom chip, the 3rd eeprom chip, the 4th eeprom chip is compound, and the chip selection signal line of the 5th eeprom chip, the 6th eeprom chip, the 7th eeprom chip, the 8th eeprom chip is compound; The data wire of the data wire of the first eeprom chip and the 5th eeprom chip is compound; The data wire of the data wire of the second eeprom chip and the 6th eeprom chip is compound; The data wire of the data wire of the 3rd eeprom chip and the 7th eeprom chip is compound; The data wire of the data wire of the 4th eeprom chip and the 8th eeprom chip is compound.
Lead frame rack-layer and eight chip layer can adopt printed circuit board (PCB).
The preparation process of above-mentioned three-dimensional encapsulation eeprom memory is as follows:
(1) pin 11 is welded in lead frame rack-layer 1; Eeprom chip 21,31,41,51,61,71,81,91 is arranged on respectively in chip layer 2,3,4,5,6,7,8,9 accordingly;
(2) lead frame rack-layer 1, the first chip layer 2, the second chip layer 3, the 3rd chip layer 4, four-core lamella 5, the 5th chip layer 6, the 6th chip layer 7, the 7th chip layer 8, the 8th chip layer 9 are carried out stacking from bottom to up;
(3) use epoxy resin to carry out embedding to a lead frame rack-layer and eight chip layer, a lead frame rack-layer and eight chip layer after embedding are cut, to allow a lead frame rack-layer and eight chip layer expose electrical connection pin on periphery separately;
(4) a lead frame rack-layer and eight chip layer are carried out to surface gold-plating to form Gold plated Layer, now, the electrical connection pin that Gold plated Layer is exposed on periphery separately with eight chip layer is connected, and all interconnects and also connect pin simultaneously between the electrical connection pin exposing;
(5) for the signal node this separation separates, Gold plated Layer is carried out to surperficial line engraving to form gold-plated connecting line, gold-plated connecting line carries out corresponding connection by the electrical connection pin exposing in lead frame rack-layer and chip layer and reaches 8Mb, data-bus width and reach 32, pin package as SOP-64(64 pin to form a memory capacity) the three-dimensional encapsulation eeprom memory of encapsulation, the pin 11 of lead frame rack-layer 1 is as the external access signal of three-dimensional encapsulation eeprom memory and the external physical connection thing of output signal.
The concrete purposes of each pin of this three-dimensional encapsulation eeprom memory is as table 1.
The concrete purposes of table 1 pin
The utility model is not limited to above-described embodiment, based on simple replacement above-described embodiment, that do not make creative work, should belong to the scope that the utility model discloses.
Claims (3)
1. the three-dimensional encapsulation eeprom memory that capacity is 256K × 32bit, it is characterized in that, comprise the eeprom chip of eight 128K × 8bit, also comprise and carry out from bottom to up stacking a lead frame rack-layer and eight chip layer, lead frame rack-layer is provided with the pin connecting for externally, and eight eeprom chips are arranged on respectively in eight chip layer correspondingly; Described stacking a lead frame rack-layer and eight chip layer are exposed electrical connection pin after embedding, cutting on periphery, and are provided with gold-plated connecting line at outer surface; The electrical connection pin exposing in a described lead frame rack-layer and eight chip layer is carried out corresponding connection by gold-plated connecting line, and the pin of lead frame rack-layer is the physical connection thing with external output signal as external access signal.
2. the three-dimensional encapsulation eeprom memory that a kind of capacity according to claim 1 is 256K × 32bit, is characterized in that, OE reading signal lines, the WE write signal line of eight eeprom chips are corresponding compound respectively; The chip selection signal line of the first eeprom chip, the second eeprom chip, the 3rd eeprom chip, the 4th eeprom chip is compound, and the chip selection signal line of the 5th eeprom chip, the 6th eeprom chip, the 7th eeprom chip, the 8th eeprom chip is compound; The data wire of the data wire of the first eeprom chip and the 5th eeprom chip is compound; The data wire of the data wire of the second eeprom chip and the 6th eeprom chip is compound; The data wire of the data wire of the 3rd eeprom chip and the 7th eeprom chip is compound; The data wire of the data wire of the 4th eeprom chip and the 8th eeprom chip is compound.
3. the three-dimensional encapsulation eeprom memory that a kind of capacity according to claim 1 and 2 is 256K × 32bit, is characterized in that, it is that 128Kb, data-bus width are the encapsulation eeprom chip of the TSOP-32 of 8 that described eeprom chip adopts memory capacity.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201320682871.7U CN203644765U (en) | 2013-10-30 | 2013-10-30 | Three-dimensional packaging EEPROM memory with capacity of 256Kx32bit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201320682871.7U CN203644765U (en) | 2013-10-30 | 2013-10-30 | Three-dimensional packaging EEPROM memory with capacity of 256Kx32bit |
Publications (1)
Publication Number | Publication Date |
---|---|
CN203644765U true CN203644765U (en) | 2014-06-11 |
Family
ID=50875990
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201320682871.7U Expired - Lifetime CN203644765U (en) | 2013-10-30 | 2013-10-30 | Three-dimensional packaging EEPROM memory with capacity of 256Kx32bit |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN203644765U (en) |
-
2013
- 2013-10-30 CN CN201320682871.7U patent/CN203644765U/en not_active Expired - Lifetime
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN109037182A (en) | Chip-packaging structure and memory device | |
CN203644763U (en) | Three-dimensional packaging NAND FLASH memory with capacity of 512Mx8bit | |
CN203644765U (en) | Three-dimensional packaging EEPROM memory with capacity of 256Kx32bit | |
CN203644769U (en) | Three-dimensional packaging EEPROM memory with capacity of 1Mx8bit | |
CN205751528U (en) | Mobile solid state hard disc | |
CN203644770U (en) | Three-dimensional packaging NAND FLASH memory with capacity of 8Gx8bit | |
CN203644762U (en) | Stereo packaging NAND FLASH memory with capacity of 4GX8bit | |
CN203644767U (en) | Three-dimensional packaging NAND FLASH memory with capacity of 16Gx8bit | |
CN203760449U (en) | Stereoscopically packaged NOR FLASH storage device having capacity of 16 M*16 bit | |
CN203746837U (en) | Three-dimensional packaged NAND FLASH memory with capacity of 4G*16bit | |
CN203423173U (en) | Three-dimensional packaged SDRAM having 256K*32bit capacity | |
CN203423171U (en) | Three-dimensional packaged SDRAM having 2M*8bit capacity | |
CN203103290U (en) | Stereoscopically encapsulated SRAM | |
CN203423172U (en) | Three-dimensional packaged SDRAM having 1M*16bit capacity | |
CN203423174U (en) | Three-dimensional packaged SDRAM having 512M*32bit capacity | |
CN104766826B (en) | Memory assembly for flight parameter recorder and processing method thereof | |
CN203644764U (en) | Three-dimensional packaging EEPROM memory with capacity of 512Kx8bit | |
CN203423177U (en) | Three-dimensional packaged SDRAM having 64M*48bit capacity | |
CN203423175U (en) | Three-dimensional packaged SDRAM having 128M*16bit capacity | |
CN206022355U (en) | Multi-project wafer fast packing plate | |
CN209282202U (en) | The non-hermetically sealed three-dimension packaging SRAM memory that a kind of capacity is 512k × 32bit | |
CN203406280U (en) | Three-dimensionally packaged SDRAM memory with capacity of 512M x 8bit | |
CN203423176U (en) | Three-dimensional packaged DDR1 memory having 64M*32bit capacity | |
CN209312764U (en) | The non-hermetically sealed three-dimension packaging eeprom memory that a kind of capacity is 1M × 8bit | |
CN208706636U (en) | Chip-packaging structure and memory device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CX01 | Expiry of patent term |
Granted publication date: 20140611 |
|
CX01 | Expiry of patent term |