CN203423176U - Three-dimensional packaged DDR1 memory having 64M*32bit capacity - Google Patents
Three-dimensional packaged DDR1 memory having 64M*32bit capacity Download PDFInfo
- Publication number
- CN203423176U CN203423176U CN201320387583.9U CN201320387583U CN203423176U CN 203423176 U CN203423176 U CN 203423176U CN 201320387583 U CN201320387583 U CN 201320387583U CN 203423176 U CN203423176 U CN 203423176U
- Authority
- CN
- China
- Prior art keywords
- ddr1
- layer
- lead frame
- chip
- frame rack
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Landscapes
- Semiconductor Memories (AREA)
- Dram (AREA)
Abstract
The utility model relates to a three-dimensional packaged DDR1 memory having a 64M*32bit capacity. The three-dimensional packaged DDR1 memory includes two DDR1 chips having 64M*16bit capacities. The three-dimensional packaged DDR1 memory is characterized in that the three-dimensional packaged DDR1 memory also includes a lead frame layer and two chip layers piled from bottom up; the lead frame layer is provided with pins used for external connection; the two DDR1 chips are arranged on the two chip layers in a one-to-one corresponding manner; electric connection pins are exposed on the periphery of the lead frame layer and the four chip layers being encapsulated and cut and outer surfaces of the lead frame layer and the four chip layers are provided with gold-plating connection lines; the gold-plating connection lines perform corresponding connection of the electric connection pins exposed on the lead frame layer and the two chip layers; and the pins serve as physic connectors for external access signals and external output signals of the three-dimensional packaged SDRAM. By adopting the three-dimensional packaged SDRAM, occupancy of plane space of a printed circuit board can be reduced comparatively.
Description
[technical field]
The utility model relates to memory device, and relating in particular to a kind of capacity is the three-dimensional encapsulation DDR1 memory of 64M * 32bit.
[background technology]
At present, on a lot of printed circuit board (PCB)s (PCB), all need to be equipped with DDR1 chip (DDR1: dual rate dynamic random data storage), finite capacity due to each DDR1 storage chip, if be to use very large DDR1 memory space in a certain application, will expand the area of printed circuit board (PCB) so, then post a plurality of DDR1 chips in the above.
Due at some particular places, to some, use the shared plane space of equipment of printed circuit board (PCB) to have certain restriction, may just need to reduce the area of plane of printed circuit board (PCB); Like this, relative difficult ground expands the memory space on DDR1 printed circuit board (PCB) (PCB).
[utility model content]
The technical problems to be solved in the utility model is to provide the three-dimensional encapsulation DDR1 memory that a kind of capacity is 64M * 32bit, and it can reduce the plane space that takies printed circuit board (PCB) relatively.
Above-mentioned technical problem is achieved through the following technical solutions:
A kind of capacity is the three-dimensional encapsulation DDR1 memory of 64M * 32bit, comprise the DDR1 chip that two capacity are 64M * 16bit, it is characterized in that, also comprise and carry out from bottom to up stacking a lead frame rack-layer and two chip layer, lead frame rack-layer is provided with the pin connecting for externally, and two DDR1 chips are arranged on respectively in two chip layer correspondingly; Described stacking a lead frame rack-layer and two chip layer are exposed electrical connection pin after embedding, cutting on periphery, and are provided with gold-plated connecting line at outer surface; Gold-plated connecting line carries out corresponding connection by the electrical connection pin exposing in a described lead frame rack-layer and two chip layer, and the pin of lead frame rack-layer is the physical connection thing with external output signal as external access signal.
The write signal line of two DDR1 chips, CK clock, CKE clock enable signal, BA block selection signal, RAS row address latch, CAS column address latch corresponding compound respectively, the data/address bus juxtaposition of two DDR1 chips.
The technology that connects into capacity between the DDR1 chip that is 64M * 16bit by two capacity and be the DDR1 memory of 64M * 32bit belongs to the technology that the art personnel grasp conventionally, creation point of the present utility model is to utilize two storing chip layer to put DDR1 chip, then by stacking, embedding, after cutting, at outer surface, gold-plated connecting line is set the electrical connection pin of two chip layer and a lead frame rack-layer is carried out to the corresponding three-dimensional encapsulation DDR1 memory that connects into, avoid carrying out all DDR1 chips of juxtaposition in a chip layer, reduced the plane space that takies printed circuit board (PCB), thereby reduced the plane space of printed circuit board (PCB), especially be applicable to being applied to aviation, space industry.
[accompanying drawing explanation]
Fig. 1 is sectional view of the present utility model;
Fig. 2 is two DDR1 chip connection diagrams of the present utility model.
[embodiment]
As depicted in figs. 1 and 2, the three-dimensional encapsulation DDR1 memory that a kind of capacity that the present embodiment provides is 64M * 32bit, comprise the lead frame rack-layer 1 of carrying out from bottom to up a stacking lead frame rack-layer and two chip layer 2, being provided with the pin 11 for being externally connected at 3:, one be pasted with DDR1 chip 21 put that chip layer 2, is pasted with DDR1 chip 31 put chip layer 3; The encapsulation DDR1 chip of DDR1 chip 21,31 TSOP-66 that all employing capacity is 64M * 16bit (66 pins); Stacking a lead frame rack-layer and two chip layer are exposed electrical connection pin after embedding, cutting on periphery, and are provided with gold-plated connecting line at outer surface; Gold-plated connecting line by the electrical connection pin exposing in lead frame rack-layer and chip layer carry out corresponding connection take form a capacity as 64M * 32bit, pin package be the three-dimensional encapsulation DDR1 memory of SOP-86 (86 pins) encapsulation, the pin 11 of lead frame rack-layer 1 is as the external access signal of three-dimensional encapsulation DDR1 memory and the external physical connection thing of output signal.
Wherein, the write signal line of two DDR1 chips, CK clock, CKE clock enable signal, BA block selection signal, RAS row address latch, CAS column address latch corresponding compound respectively, the data/address bus juxtaposition of two DDR1 chips.
The preparation process of above-mentioned three-dimensional encapsulation DDR1 memory is as follows:
(1) pin 11 is welded in lead frame rack-layer 1; DDR1 chip 21,31 is arranged on respectively in chip layer 2,3 accordingly;
(2) lead frame rack-layer 1, chip layer 2, chip layer 3 are carried out stacking from bottom to up;
(3) use epoxy resin to carry out embedding to a lead frame rack-layer and two chip layer, a lead frame rack-layer and two chip layer after embedding are cut, to allow a lead frame rack-layer and two chip layer expose electrical connection pin on periphery separately;
(4) a lead frame rack-layer and two chip layer are carried out to surface gold-plating to form Gold plated Layer, now, the electrical connection pin that Gold plated Layer is exposed on periphery separately with two chip layer is connected, and all interconnects and also connect pin simultaneously between the electrical connection pin exposing;
(5) for this separated signal node is separated, Gold plated Layer is carried out to surperficial line engraving to form gold-plated connecting line, gold-plated connecting line by the electrical connection pin exposing in lead frame rack-layer and chip layer carry out corresponding connection take form a capacity as 64M * 32bit, pin package be the three-dimensional encapsulation DDR1 memory of SOP-86 (86 pins) encapsulation, the pin 11 of lead frame rack-layer 1 is as the external access signal of three-dimensional encapsulation DDR1 memory and the external physical connection thing of output signal.
The concrete purposes of 86 pins of this three-dimensional encapsulation DDR1 memory is as table 1.
The concrete purposes of table 1 pin
The utility model is not limited to above-described embodiment, based on simple replacement above-described embodiment, that do not make creative work, should belong to the scope that the utility model discloses.
Claims (2)
1. the three-dimensional encapsulation DDR1 memory that capacity is 64M * 32bit, comprise the DDR1 chip that two capacity are 64M * 16bit, it is characterized in that, also comprise and carry out from bottom to up stacking a lead frame rack-layer and two chip layer, lead frame rack-layer is provided with the pin connecting for externally, and two DDR1 chips are arranged on respectively in two chip layer correspondingly; Described stacking a lead frame rack-layer and two chip layer are exposed electrical connection pin after embedding, cutting on periphery, and are provided with gold-plated connecting line at outer surface; Gold-plated connecting line carries out correspondence by a described lead frame rack-layer with the electrical connection pin exposing in two chip layer and is connected, and the pin of lead frame rack-layer is the physical connection thing with external output signal as external access signal.
2. the three-dimensional encapsulation DDR1 memory that a kind of capacity according to claim 1 is 64M * 32bit, it is characterized in that, the write signal line of two DDR1 chips, CK clock, CKE clock enable signal, BA block selection signal, RAS row address latch, CAS column address latch corresponding compound respectively, the data/address bus juxtaposition of two DDR1 chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320387583.9U CN203423176U (en) | 2013-06-30 | 2013-06-30 | Three-dimensional packaged DDR1 memory having 64M*32bit capacity |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320387583.9U CN203423176U (en) | 2013-06-30 | 2013-06-30 | Three-dimensional packaged DDR1 memory having 64M*32bit capacity |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203423176U true CN203423176U (en) | 2014-02-05 |
Family
ID=50022267
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320387583.9U Expired - Lifetime CN203423176U (en) | 2013-06-30 | 2013-06-30 | Three-dimensional packaged DDR1 memory having 64M*32bit capacity |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203423176U (en) |
-
2013
- 2013-06-30 CN CN201320387583.9U patent/CN203423176U/en not_active Expired - Lifetime
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9805785B2 (en) | Electronic device | |
| CN103985648B (en) | The wafer-level packaging method of quasiconductor and semiconductor package part | |
| CN103843136A (en) | Packaging dram and soc in an IC package | |
| CN203423176U (en) | Three-dimensional packaged DDR1 memory having 64M*32bit capacity | |
| CN203423177U (en) | Three-dimensional packaged SDRAM having 64M*48bit capacity | |
| CN203423175U (en) | Three-dimensional packaged SDRAM having 128M*16bit capacity | |
| CN203644763U (en) | Three-dimensional packaging NAND FLASH memory with capacity of 512Mx8bit | |
| CN203406280U (en) | Three-dimensionally packaged SDRAM memory with capacity of 512M x 8bit | |
| CN203423171U (en) | Three-dimensional packaged SDRAM having 2M*8bit capacity | |
| CN203103290U (en) | Stereoscopically encapsulated SRAM | |
| CN203423172U (en) | Three-dimensional packaged SDRAM having 1M*16bit capacity | |
| CN203423173U (en) | Three-dimensional packaged SDRAM having 256K*32bit capacity | |
| CN203423174U (en) | Three-dimensional packaged SDRAM having 512M*32bit capacity | |
| CN203300642U (en) | Three-dimensionally packaged DDR1 SDRAM memory | |
| CN102087983A (en) | Packaging and laminating method, packaging and laminating structure and circuit board system thereof | |
| CN209282202U (en) | The non-hermetically sealed three-dimension packaging SRAM memory that a kind of capacity is 512k × 32bit | |
| CN203644765U (en) | Three-dimensional packaging EEPROM memory with capacity of 256Kx32bit | |
| CN203760449U (en) | Stereoscopically packaged NOR FLASH storage device having capacity of 16 M*16 bit | |
| CN203423178U (en) | Three-dimensional packaged SDRAM memory with capacity of 256M*8bit | |
| CN203103288U (en) | Stereoscopically encapsulated NAND-FLASH memory | |
| CN203644762U (en) | Stereo packaging NAND FLASH memory with capacity of 4GX8bit | |
| CN203746837U (en) | Three-dimensional packaged NAND FLASH memory with capacity of 4G*16bit | |
| CN203800042U (en) | Embedded packaging body structure | |
| CN203644769U (en) | Three-dimensional packaging EEPROM memory with capacity of 1Mx8bit | |
| CN203644764U (en) | Three-dimensional packaging EEPROM memory with capacity of 512Kx8bit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140205 |