CN203423175U - Three-dimensional packaged SDRAM having 128M*16bit capacity - Google Patents

Abstract

The utility model relates to a three-dimensional packaged SDRAM (Synchronous Dynamic Random Access memory) having a 128M*16bit capacity. The three-dimensional packaged SDRAM includes four SDRAM chips, and also includes a lead frame layer and four chip layers piled from bottom up. The lead frame layer is provided with pins used for external connection and each chip layer receives a chip. Electric connection pins are exposed on the periphery of the lead frame layer and the four chip layers being encapsulated and cut and outer surfaces of the lead frame layer and the four chip layers are provided with gold-plating connection lines. The gold-plating connection lines perform corresponding connection of the electric connection pins exposed on the lead frame layer and the four chip layers. The pins serve as physic connectors for external access signals and external output signals of the three-dimensional packaged SDRAM. By adopting the three-dimensional packaged SDRAM, occupancy of plane space of a printed circuit board can be reduced comparatively.

Description

A kind of capacity is the three-dimensional encapsulation SDRAM memory of 128M * 16bit

[technical field]

The utility model relates to memory device, and relating in particular to a kind of capacity is the three-dimensional encapsulation SDRAM memory of 128M * 16bit.

[background technology]

At present, on a lot of printed circuit board (PCB)s (PCB), all need to be equipped with SDRAM chip (SDRAM: dynamic random data storage), finite capacity due to each SDRAM storage chip, if be to use very large SDRAM memory space in a certain application, will expand the area of printed circuit board (PCB) so, then post a plurality of SDRAM chips in the above.

Due at some particular places, to some, use the shared plane space of equipment of printed circuit board (PCB) to have certain restriction, may just need to reduce the area of plane of printed circuit board (PCB); Like this, relative difficult ground expands the memory space on SDRAM printed circuit board (PCB) (PCB).

[utility model content]

The technical problems to be solved in the utility model is to provide the three-dimensional encapsulation SDRAM memory that a kind of capacity is 128M * 16bit, and it can reduce the plane space that takies printed circuit board (PCB) relatively.

For solving the problems of the technologies described above, the utility model provides following technical scheme:

A kind of capacity is the three-dimensional encapsulation SDRAM memory of 128M * 16bit, comprise the SDRAM chip that four capacity are 128M * 4bit, it is characterized in that, also comprise and carry out from bottom to up stacking a lead frame rack-layer and four chip layer, lead frame rack-layer is provided with the pin connecting for externally, and four SDRAM chips arrange respectively in four chip layer correspondingly; Described stacking a lead frame rack-layer and four chip layer are exposed electrical connection pin after embedding, cutting on periphery, and are provided with gold-plated connecting line at outer surface; Gold-plated connecting line carries out corresponding connection by the electrical connection pin exposing in a described lead frame rack-layer and four chip layer, and the pin of lead frame rack-layer is the physical connection thing with external output signal as external access signal.

The address wire of described four SDRAM chips, write signal line, CLK clock, CKE clock enable signal, BA block selection signal, RAS row address latch, CAS column address latch corresponding compound respectively, the data/address bus juxtaposition of described four SDRAM chips.

The technology that connects into capacity between the SDRAM chip that is 128M * 4bit by four capacity and be the SDRAM memory of 128M * 16bit belongs to the technology that the art personnel grasp conventionally, creation point of the present utility model is to utilize four storing chip layer to put SDRAM chip, then by stacking, embedding, after cutting, at outer surface, gold-plated connecting line is set putting four chip layer of chip and the pin wiring of a lead frame rack-layer connects into a three-dimensional encapsulation SDRAM memory, by three-dimensional encapsulation mode, avoid carrying out all SDRAM chips of juxtaposition in a chip layer, reduced the plane space that takies printed circuit board (PCB), thereby reduced the plane space of printed circuit board (PCB), especially be applicable to being applied to aviation, space industry.

[accompanying drawing explanation]

Fig. 1 is sectional view of the present utility model;

Fig. 2 is four SDRAM chip connection diagrams of the present utility model.

[embodiment]

As depicted in figs. 1 and 2, the three-dimensional encapsulation SDRAM memory that a kind of capacity that the present embodiment provides is 128M * 16bit, comprise and carry out from bottom to up a stacking lead frame rack-layer and four chip layer: one is provided with the pin chip layer 1 of the pin 11 for being externally connected, one is pasted with the chip layer 2 of SDRAM chip 21, one is pasted with the chip layer 3 of SDRAM chip 31, one is pasted with the chip layer 5 that SDRAM chip 41 chip layer 4, are pasted with SDRAM chip 51; It is the encapsulation SDRAM chip of 128M * 4bit, TSOP-54 (54 pins) that SDRAM chip 21,31,41,51 all adopts memory capacity; Stacking a lead frame rack-layer and four chip layer are exposed electrical connection pin after embedding, cutting on periphery, and are provided with gold-plated connecting line at outer surface; Gold-plated connecting line by the electrical connection pin exposing in chip layer carry out corresponding connection take form a capacity as 128M * 16bit, pin package be the three-dimensional encapsulation SDRAM memory of SOP-54 (54 pins) encapsulation, the pin 11 of lead frame rack-layer 1 is as the external access signal of three-dimensional encapsulation SDRAM memory and the external physical connection thing of output signal.

Wherein, the address wire of four SDRAM chips, write signal line, CLK clock, CKE clock enable signal, BA block selection signal, RAS row address latch, CAS column address latch corresponding compound respectively, the data/address bus juxtaposition of four SDRAM chips.

The preparation process of above-mentioned three-dimensional encapsulation SDRAM memory is as follows:

(1) pin 11 is welded in lead frame rack-layer 1; SDRAM chip 21,31,41,51 is arranged on respectively in chip layer 2,3,4,5 correspondingly;

(2) lead frame rack-layer 1, chip layer 2, chip layer 3, chip layer 4, chip layer 5 are carried out stacking from bottom to up;

(3) use epoxy resin to carry out embedding to a lead frame rack-layer and four chip layer, a lead frame rack-layer and four chip layer after embedding are cut, to allow a lead frame rack-layer and four chip layer expose electrical connection pin on periphery separately;

(4) a lead frame rack-layer and four chip layer are carried out to surface gold-plating to form Gold plated Layer, now, the electrical connection pin that Gold plated Layer is exposed on periphery separately with four chips is connected, and all interconnects and also connect pin simultaneously between the electrical connection pin exposing;

(5) for this separated signal node is separated, Gold plated Layer is carried out to surperficial line engraving to form gold-plated connecting line, gold-plated connecting line by the electrical connection pin exposing in lead frame rack-layer and chip layer carry out associated connection take form a capacity as 128M * 16bit, pin package be the three-dimensional encapsulation SDRAM memory of SOP-54 (54 pins) encapsulation, the pin 11 of lead frame rack-layer 1 is as the external access signal of three-dimensional encapsulation SDRAM memory and the external physical connection thing of output signal.

The concrete purposes of 54 pins of this three-dimensional encapsulation SDRAM memory is as table 1.

The concrete purposes of table 1 pin

The utility model is not limited to above-described embodiment, based on simple replacement above-described embodiment, that do not make creative work, should belong to the scope that the utility model discloses.

Claims (2)

1. the three-dimensional encapsulation SDRAM memory that capacity is 128M * 16bit, comprise the SDRAM chip that four capacity are 128M * 4bit, it is characterized in that, also comprise and carry out from bottom to up stacking a lead frame rack-layer and four chip layer, lead frame rack-layer is provided with the pin connecting for externally, and four SDRAM chips arrange respectively in four chip layer correspondingly; Described stacking a lead frame rack-layer and four chip layer are exposed electrical connection pin after embedding, cutting on periphery, and are provided with gold-plated connecting line at outer surface; Gold-plated connecting line carries out corresponding connection by the electrical connection pin exposing in a described lead frame rack-layer and four chip layer, and the pin of lead frame rack-layer is the physical connection thing with external output signal as external access signal.

2. the three-dimensional encapsulation SDRAM memory that a kind of capacity according to claim 1 is 128M * 16bit, it is characterized in that, the address wire of described four SDRAM chips, write signal line, CLK clock, CKE clock enable signal, BA block selection signal, RAS row address latch, CAS column address latch corresponding compound respectively, the data/address bus juxtaposition of described four SDRAM chips.

Images