CN201450006U - Semi-conductor device of integrated memory chip and control chip - Google Patents
Semi-conductor device of integrated memory chip and control chip Download PDFInfo
- Publication number
- CN201450006U CN201450006U CN2009200464975U CN200920046497U CN201450006U CN 201450006 U CN201450006 U CN 201450006U CN 2009200464975 U CN2009200464975 U CN 2009200464975U CN 200920046497 U CN200920046497 U CN 200920046497U CN 201450006 U CN201450006 U CN 201450006U
- Authority
- CN
- China
- Prior art keywords
- chip
- control chip
- semiconductor device
- semi
- integrated memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Abstract
The utility model relates to a semi-conductor device of an integrated memory chip and a control chip, and belongs to the technical field of electronic packing. The semi-conductor device comprises a basal plate, a memory chip, a control chip and a passive element, wherein bonding pads of the memory chip and the control chip are electrically connected with the bonding pads on the basal plate through a lead wire (mostly golden wires) bonding mode, then, the passive element is connected through a basal plate internal circuit, thereby realizing electrical connection between the memory chip and the control chip in the semi-conductor device. The semi-conductor device can pack the storage chip and the control chip together and is provided with U-disk function, SD card function, NANDflash memorizers and other functions, and a semiconductor device can be packed, such as LGA, BGA and so on.
Description
(1) technical field
The utility model relates to a kind of semiconductor device.Belong to technical field of electronic encapsulation.
(2) background technology
There are the semiconductor device of storage chip and the semiconductor device of controller chip in the market.Develop a system if desired, as USB flash disk, SD card etc., we must use the semiconductor device of storage chip and the semiconductor device of controller chip respectively so, have so not only increased development difficulty, bring compatibility issue, also can increase the total cost of system.
(3) utility model content
The purpose of this utility model is to overcome the inconvenience that semiconductor device that above-mentioned needs use storage chip and controller chip respectively brings, and the semiconductor device of a kind of integrated storage chip and controller chip is provided.
The purpose of this utility model is achieved in that the semiconductor device of a kind of integrated memory chip and control chip, described semiconductor device comprises substrate, storage chip, control chip and passive device, and by the lead-in wire (being gold thread mostly) bonding mode the pad of described storage chip and control chip and the pad on the substrate are electrically connected, connect passive device by the substrate internal wiring again, thereby realize being electrically connected of this semiconductor device inside storage chip and control chip.
The semiconductor device of the utility model integrated memory chip and control chip, described storage chip has one or more, and for saving substrate space, described storage chip and control chip are carrying out piling up on the three dimensions on the substrate.
The semiconductor device of the utility model integrated memory chip and control chip, described storage chip is or/and control chip carries out the transfer of pad by the support plate chip.
The semiconductor device of integrated memory chip of the present utility model and control chip, described passive device are that resistance is or/and electric capacity.
The semiconductor device of integrated memory chip of the present utility model and control chip, described semiconductor packages become packing forms commonly used such as LGA or BGA.
The beneficial effects of the utility model are:
This semiconductor device can be packaged together storage chip and control chip, has functions such as USB flash disk function, SD card function, NANDflash memory, and is packaged into a semiconductor device, as LGA, BGA etc.
(4) description of drawings
To those skilled in the art, from the following conjunction with figs. that is described in detail, the utility model can more clearly be understood, and its above-mentioned and other purpose and advantage will become more obvious, wherein:
Fig. 1 is USB flash disk structural representation in the past.
Fig. 2 is SD card structure schematic diagram in the past.
Fig. 3 is a functional block diagram of the present utility model.
Fig. 4 is a conspectus of the present utility model.
Fig. 5 is a support plate chip conspectus of the present utility model.
Among the figure: support plate chip U1, Nandflash chip U2, SD card control chip U3, USB control chip U4.
(5) embodiment
Fig. 3 is an embodiment functional block diagram of the present utility model, Fig. 4 is the conspectus of the utility model embodiment, it combines the function of Fig. 1, Fig. 2, be divided into into three parts: Nandflash chip U2 (2 layers of chip, trapezoidal piling up), SD card control chip U3, USB control chip U4, the semiconductor packages in the present embodiment becomes a LGA module.Can see lead-in wire (the being gold thread mostly) bonding scheme of described each chip among Fig. 4.Present embodiment has used support plate chip U1.The pad of USB control chip U4 links to each other by the pad of bonding line with support plate chip U1 centre, pad in the middle of the support plate chip U1 links to each other with the top pad of support plate chip U1 (seeing Fig. 5 support plate chip conspectus) by support plate chip U1 internal connection circuit, and the top pad of support plate chip U1 is electrically connected by bonding line and substrate again.By support plate chip U1, realize the transfer of chip U4 pad.
The pad of SD card control chip U3 is electrically connected by bonding line and substrate.The pad of Nandflash chip U2 also is to be electrically connected by bonding line and substrate, connects passive device resistance or/and electric capacity etc. by the substrate internal wiring again.Finally realized the encapsulation scheme of the semiconductor device of integrated memory chip and control chip.
In the present embodiment, memory function and SD card function, USB flash disk function are separate.For further reducing product cost, to enhance competitiveness, the semiconductor device of present embodiment can remove SD card control chip U3, only keeps the USB function; Perhaps remove USB control chip U4 and support plate chip U1, only keep SD card function; Perhaps the both removes, and only keeps Nandflash chip U2, uses as storage chip.
After the utility model semiconductor packages becomes packing forms commonly used such as LGA, BGA, but, make things convenient for PCB client to use, improve the stability of a system and compatibility, reduce PCB client's design difficulty and design cost with regard to the secondary upper plate.
More than the purpose of narration done for preferred embodiment of the present utility model in order to illustrate, accurately be disclosed form and be not intended to limit the utility model, based on above instruction or to make an amendment or change from embodiment of the present utility model study be possible, embodiment is for explain principle of the present utility model and allow those skilled in the art and various embodiment utilize the utility model to select and narrate that technological thought attempt of the present utility model is decided by appended claim and equalization thereof in practical application.
Claims (4)
1. the semiconductor device of integrated memory chip and control chip, it is characterized in that described semiconductor device comprises substrate, storage chip, control chip and passive device, and by the mode of lead-in wire bonding the pad of described storage chip and control chip and the pad on the substrate are electrically connected, again by substrate internal wiring connection passive device.
2. the semiconductor device of a kind of integrated memory chip according to claim 1 and control chip is characterized in that described storage chip has one or more, and described storage chip and control chip are carrying out piling up on the three dimensions on the substrate.
3. the semiconductor device of a kind of integrated memory chip according to claim 1 and control chip is characterized in that storage chip or/and control chip carries out the transfer of pad by support plate chip U1.
4. the semiconductor device of a kind of integrated memory chip according to claim 1 and control chip is characterized in that described semiconductor packages becomes LGA or BGA packing forms.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009200464975U CN201450006U (en) | 2009-06-11 | 2009-06-11 | Semi-conductor device of integrated memory chip and control chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009200464975U CN201450006U (en) | 2009-06-11 | 2009-06-11 | Semi-conductor device of integrated memory chip and control chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201450006U true CN201450006U (en) | 2010-05-05 |
Family
ID=42554729
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009200464975U Expired - Lifetime CN201450006U (en) | 2009-06-11 | 2009-06-11 | Semi-conductor device of integrated memory chip and control chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201450006U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103680640A (en) * | 2013-12-11 | 2014-03-26 | 北京时代民芯科技有限公司 | Laser simulation single particle effect back irradiation test method for memory circuit |
| CN104425013A (en) * | 2013-08-30 | 2015-03-18 | 北京兆易创新科技股份有限公司 | Flash memory unit |
| CN104425012A (en) * | 2013-08-30 | 2015-03-18 | 北京兆易创新科技股份有限公司 | NAND flash memory unit |
| CN110018801A (en) * | 2019-05-22 | 2019-07-16 | 深圳三地一芯电子有限责任公司 | A kind of integral type storage equipment |
-
2009
- 2009-06-11 CN CN2009200464975U patent/CN201450006U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104425013A (en) * | 2013-08-30 | 2015-03-18 | 北京兆易创新科技股份有限公司 | Flash memory unit |
| CN104425012A (en) * | 2013-08-30 | 2015-03-18 | 北京兆易创新科技股份有限公司 | NAND flash memory unit |
| CN103680640A (en) * | 2013-12-11 | 2014-03-26 | 北京时代民芯科技有限公司 | Laser simulation single particle effect back irradiation test method for memory circuit |
| CN110018801A (en) * | 2019-05-22 | 2019-07-16 | 深圳三地一芯电子有限责任公司 | A kind of integral type storage equipment |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20100505 |
|
| CX01 | Expiry of patent term |