CN101127332A - Pin ball grid array encapsulation structure of wafer - Google Patents
Pin ball grid array encapsulation structure of wafer Download PDFInfo
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- CN101127332A CN101127332A CN 200610109599 CN200610109599A CN101127332A CN 101127332 A CN101127332 A CN 101127332A CN 200610109599 CN200610109599 CN 200610109599 CN 200610109599 A CN200610109599 A CN 200610109599A CN 101127332 A CN101127332 A CN 101127332A
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- 238000005538 encapsulation Methods 0.000 title claims description 72
- 238000004806 packaging method and process Methods 0.000 claims abstract description 10
- 239000013078 crystal Substances 0.000 claims description 44
- 239000000853 adhesive Substances 0.000 claims description 42
- 230000001070 adhesive effect Effects 0.000 claims description 42
- 238000005530 etching Methods 0.000 claims description 6
- 239000003292 glue Substances 0.000 claims description 6
- 230000002093 peripheral effect Effects 0.000 claims description 6
- 229920001971 elastomer Polymers 0.000 claims description 4
- 239000000806 elastomer Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 238000003466 welding Methods 0.000 abstract description 10
- 239000011324 bead Substances 0.000 abstract 4
- 239000012945 sealing adhesive Substances 0.000 abstract 4
- 235000012431 wafers Nutrition 0.000 abstract 4
- 239000004020 conductor Substances 0.000 abstract 2
- 238000003491 array Methods 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 abstract 1
- 238000010276 construction Methods 0.000 description 26
- 239000000758 substrate Substances 0.000 description 14
- 230000000694 effects Effects 0.000 description 8
- 230000008901 benefit Effects 0.000 description 4
- 230000002950 deficient Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 239000000872 buffer Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 238000007639 printing Methods 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 239000002390 adhesive tape Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
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- 238000011161 development Methods 0.000 description 1
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- 229910052742 iron Inorganic materials 0.000 description 1
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- 239000007769 metal material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
The utility model relates to a packaging structure for the pin ball-lattice arrays on wafers, mainly comprising a non-external pin conductor frame, a wafer, an adhesive-wafer layer, a plurality of welding wires, a sealing adhesive body and a plurality of welding beads. The adhesive-wafer layer is formed between the active surface of the wafer and the upper surface of the pin of the non-external pin conductor frame; the welding wires are in electric connection with the wafer and the pins; the welding beads are arranged in the catching region of the lower surface of the pins; the sealing adhesive body is used to seal the upper surface of the pins, the adhesive-wafer layer and the welding wires, the lower surface except the region for arranging the welding beads, and the side faces between the lower surface and the upper surface of the pins; the sealing adhesive body is provided with a plurality of counterbores to make the exposed catching region relatively concave in a bottom surface of the sealing adhesive body. With the structure, the utility model solves the problem that the welding beads fall off easily, and improves the stability and reliability of solder sphere placement and wire bond.
Description
Technical field
The present invention relates to a kind of semiconductor wafer and exempt to use the sphere grid array encapsulation technology of circuit board, particularly relate to and a kind ofly solve the soldered ball problem that comes off easily, and can promote the ball grid array encapsulation construction (Ball Grid Array package withleads on chip) of pin kenel on the wafer of routing and stability of planting ball and reliability.
Background technology
Sphere grid array in the past (BGA) packaging structure is to use circuit substrate as chip carrier, and circuit substrate is provided with slotted eye, passes through for the bonding wire of routing.Common this ball grid array encapsulation construction can be referred to as chip type sphere grid array (Chip-On-Board BGA) or the sphere grid array (Chip-On-Substrate BGA) of wafer on substrate on window type ball grid array (Window BGA), the plate.
Seeing also shown in Figure 1ly, is the schematic cross-section of existing known a kind of ball grid array encapsulation construction.Existing known ball grid array encapsulation construction 100 mainly comprises a circuit substrate 110, a wafer 120, one sticking crystal layer 130, a plurality of bonding wire 140, an adhesive body 150 and a plurality of soldered ball 160.This circuit substrate 110 is to be a kind of bismaleimide-3 pyridine (BismaleimideTriazine, BT) printed circuit board (PCB) of material, slotted eye 113 with a upper surface 111, a lower surface 112 and a perforation upper and lower surface, other has a plurality of routings and connects finger and the pad of receiving (figure does not draw).The active surface 121 of this wafer 120 is formed with a plurality of weld pads 140, by this sticking crystal layer 130 active surface 121 of this wafer 120 is cemented in the upper surface 111 of this circuit substrate 110, and those weld pads 122 are aligned in this slotted eye 113.Those bonding wires 140 electrically connect the weld pad 122 of this wafer 120 to this circuit substrate 110 via this slotted eye 113.The upper surface 111 of this adhesive body 150 except being formed on this circuit substrate 110 more is formed in this slotted eye 113, to seal those bonding wires 140.160 of those soldered balls are the lower surfaces 112 that is arranged at this circuit substrate 110, engage for outer surface.Because the active surface 121 of this wafer 120 is near circuit substrate 110, can shorten the length of bonding wire 140, so can be applicable to the encapsulation of the memory chip of high frequency, as second generation Double Data Rate (Double Data Rate 2, DDR2) memory body, or other special purpose integrated circuit (Application Specific IntegratedCircuit, encapsulation ASIC).
Yet the cost of circuit substrate is quite to be higher than lead frame (leadframe), if can significantly reduce packaging cost with lead frame as chip carrier and be packaged into ball grid array encapsulation construction.Therefore; someone proposes and can use lead frame under the sphere grid array encapsulation architecture; yet is the whole outside that exposes to wafer as No. the 495941st, TaiWan, China patent announcement with its soldered ball of ball grid array encapsulation construction that is disclosed for No. 584316; lack protection; in removing the process of storage, be easy to ball. in addition; lead frame is directly fixing by hard adhesive body at the joint of soldered ball, and nonelastic support effect needs further to promote so plant the stability and the product reliability of ball.
This shows that above-mentioned existing ball grid array encapsulation construction obviously still has inconvenience and defective, and demands urgently further being improved in structure and use.In order to solve the problem of above-mentioned existence, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and common product does not have appropriate structure to address the above problem, this obviously is the problem that the anxious desire of relevant dealer solves.Therefore how to found a kind of novel pin ball grid array encapsulation structure of wafer, real one of the current important research and development problem that belongs to, also becoming the current industry utmost point needs improved target.
Because the defective that above-mentioned existing ball grid array encapsulation construction exists, the inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, and the utilization of cooperation scientific principle, actively studied innovation, in the hope of founding a kind of new pin ball grid array encapsulation structure of wafer, can improve general existing ball grid array encapsulation construction, make it have more practicality.Through constantly research, design, and, create the present invention who has practical value finally through after studying sample and improvement repeatedly.
Summary of the invention
Main purpose of the present invention is, overcome the defective that existing ball grid array encapsulation construction exists, and provide a kind of novel pin ball grid array encapsulation structure of wafer, technical problem to be solved is to make it can solve the problem that the BGA encapsulating products uses not to be had outer pin formula lead frame and cause soldered ball to come off easily, and can promote routing and plant the stability and the reliability of ball, thereby be suitable for practicality more.
Another object of the present invention is to, a kind of novel pin ball grid array encapsulation structure of wafer is provided, technical problem to be solved is to make it not have wafer peripheral and central welding pad with encapsulation there to be outer pin formula lead frame carrying, becomes the BGA encapsulating products, thereby is suitable for practicality more.
A further object of the present invention is, a kind of novel pin ball grid array encapsulation structure of wafer is provided, and technical problem to be solved is to make its soldered ball stress buffer effect that can promote the BGA encapsulation, thereby is suitable for practicality more.
An also purpose of the present invention is, a kind of novel pin ball grid array encapsulation structure of wafer is provided, technical problem to be solved is to make it not make BGA encapsulation microminiaturization become wafer size encapsulation kenel there to be outer pin formula lead frame, thereby is suitable for practicality more.
The object of the invention to solve the technical problems realizes by the following technical solutions.According to a kind of pin ball grid array encapsulation structure of wafer that the present invention proposes, it comprises: a no external leading pin type lead frame, and it has a plurality of pins, and the lower surface definition of each pin has a routing district and a catching region; One wafer, it has an active surface, is formed with a plurality of first weld pads on this active surface; One sticking crystal layer, it is formed between the upper surface of this active surface of this wafer and those pins; A plurality of bonding wires, it connects the routing district of those first weld pads of this wafer to those pins; One adhesive body, it is in conjunction with this wafer and seal the upper surface of those bonding wires, this sticking crystal layer, those pins, lower surface and the side of those pins between upper surface and lower surface except those catching region, and this adhesive body has a plurality of counterbores, so that those catching region that appear are recessed into the bottom surface in this adhesive body relatively; And a plurality of soldered balls, it is arranged at those catching region.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid pin ball grid array encapsulation structure of wafer, wherein said those counterbores are that the mode of etching partially with lead frame forms.
Aforesaid pin ball grid array encapsulation structure of wafer, wherein said sticking crystal layer are to be patterning, comprise those routing districts of those pins and the corresponding position of those catching region so that should glue the bonding region of crystal layer.
Aforesaid pin ball grid array encapsulation structure of wafer, be formed with at least one second weld pad on this active surface of wherein said wafer in addition, those first weld pads are arranged in a middle position of this active surface, this second weld pad is arranged in a peripheral position of this active surface, and this second weld pad is not covered by this sticking crystal layer and those pins.
Aforesaid pin ball grid array encapsulation structure of wafer, wherein said sticking crystal layer are the elastomers for low modulus.
Aforesaid pin ball grid array encapsulation structure of wafer, this active surface area of wherein said wafer be not less than this adhesive body the surface engagement area 70 percent so that this packaging structure is wafer size encapsulation (CSP) kenel.
Aforesaid pin ball grid array encapsulation structure of wafer, wherein said adhesive body have more at least one inner fovea part that is lower than this bottom surface, and those counterbores are to be positioned at this inner fovea part.
The present invention compared with prior art has tangible advantage and beneficial effect.As known from the above, in order to achieve the above object, the invention provides a kind of ball grid array encapsulation construction, mainly comprise a no external leading pin type lead frame, a wafer, a sticking crystal layer, a plurality of bonding wire, an adhesive body and a plurality of soldered ball.This no external leading pin type lead frame has a plurality of pins, and the lower surface definition of each pin has a routing district and a catching region.This wafer has an active surface, is formed with a plurality of first weld pads on this active surface.Should sticking crystal layer be formed between the upper surface of this active surface of this wafer and those pins.Those bonding wires are to connect the routing district of those first weld pads of this wafer to those pins.This adhesive body is in conjunction with this wafer and seals the upper surface of those bonding wires, this sticking crystal layer, those pins, lower surface and the side of those pins between upper surface and lower surface except those catching region, and this adhesive body has a plurality of counterbores, so that those catching region that appear are recessed into the bottom surface in this adhesive body relatively.Those soldered balls are arranged at those catching region.
Aforesaid ball grid array encapsulation construction, wherein those counterbores are that the mode of etching partially with lead frame forms.Aforesaid ball grid array encapsulation construction should sticking crystal layer be to be patterning wherein, was to comprise those routing districts of those pins and the corresponding position of those catching region so that should glue the bonding region of crystal layer.Aforesaid ball grid array encapsulation construction, wherein be formed with at least one second weld pad in addition on this active surface of this wafer, those first weld pads are middle positions that are arranged in this active surface, this second weld pad is a peripheral position that is arranged in this active surface, and this second weld pad is not covered by this sticking crystal layer and those pins.Aforesaid ball grid array encapsulation construction should sticking crystal layer be for hanging down the elastomer of modulus wherein.Aforesaid ball grid array encapsulation construction, wherein this active surface area of this wafer be not less than this adhesive body the surface engagement area 70 percent so that this packaging structure is wafer size encapsulation (CSP) kenel.
By technique scheme, pin ball grid array encapsulation structure of wafer of the present invention has following advantage at least:
1, the present invention has overcome the defective that existing ball grid array encapsulation construction exists, can solve the problem that the BGA encapsulating products uses not to be had outer pin formula lead frame and cause soldered ball to come off easily, and can promote routing and the stability and the reliability of planting ball, be very suitable for practicality.
2, the present invention can not have wafer peripheral and central welding pad with encapsulation there to be outer pin formula lead frame carrying, becomes the BGA encapsulating products, thereby is suitable for practicality more.
3, the present invention can promote the soldered ball stress buffer effect of BGA encapsulation.
4, the present invention can not make BGA encapsulation microminiaturization become wafer size encapsulation kenel there to be outer pin formula lead frame, thereby is suitable for practicality more.
In sum, the invention relates to a kind of pin ball grid array encapsulation structure of wafer, mainly comprise a no external leading pin type lead frame, a wafer, a sticking crystal layer, a plurality of bonding wire, an adhesive body and a plurality of soldered ball.Should sticking crystal layer be to be formed between the upper surface of pin of the active surface of this wafer and this no external leading pin type lead frame.Those bonding wires are to electrically connect this wafer and those pins.Those soldered balls are the catching region that are arranged at the lower surface of those pins.This adhesive body is upper surface, the lower surface and the side of those pins between upper surface and lower surface except the zone that is provided with for those soldered balls of those bonding wires of sealing, this sticking crystal layer, those pins, and this adhesive body is to have a plurality of counterbores, so that those catching region that appear are recessed into the bottom surface in this adhesive body relatively.By said structure, can solve the problem that soldered ball comes off easily, and can promote routing and the stability and the reliability of planting ball.The present invention has above-mentioned plurality of advantages and practical value, no matter it all has bigger improvement on product structure or function, obvious improvement is arranged technically, and produced handy and practical effect, and more existing ball grid array encapsulation construction has the outstanding effect of enhancement, thereby being suitable for practicality more, and having the extensive value of industry, really is a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 is the schematic cross-section that has known a kind of ball grid array encapsulation construction now.
Fig. 2 is according to first specific embodiment of the present invention, a kind of schematic cross-section of pin ball grid array encapsulation structure of wafer.
Fig. 3 is according to first specific embodiment of the present invention, the schematic diagram of the sticking crystal layer of this packaging structure on wafer.
Fig. 4 is according to second specific embodiment of the present invention, the schematic cross-section of another kind of pin ball grid array encapsulation structure of wafer.
100: ball grid array encapsulation construction 110: circuit substrate
111: upper surface 112: lower surface
113: slotted eye 120: wafer
121: active surface 122: weld pad
130: sticking crystal layer 140: bonding wire
150: adhesive body 160: soldered ball
200: ball grid array encapsulation construction 210: pin
211: upper surface 212: lower surface
213: routing district 214: catching region
220: wafer 221: active surface
222: 223: the first weld pads in the back side
240: bonding wire 250: adhesive body
251: bottom surface 252: counterbore
253: inner fovea part 260: soldered ball
300: ball grid array encapsulation construction 310: pin
311: upper surface 3.12: lower surface
313: routing district 314: catching region
320: wafer 321: active surface
322: 323: the first weld pads in the back side
Weld pad 330 in 324: the second: sticking crystal layer
340: bonding wire 350: adhesive body
351: bottom surface 352: counterbore
360: soldered ball
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, to its embodiment of pin ball grid array encapsulation structure of wafer, structure, feature and the effect thereof that foundation the present invention proposes, describe in detail as after.
Seeing also shown in Figure 2ly, is the schematic cross-section according to first specific embodiment of the present invention a kind of pin ball grid array encapsulation structure of wafer.A kind of ball grid array encapsulation construction 200 of the present invention's first specific embodiment mainly comprises a no external leading pin type lead frame, a wafer 220, one sticking crystal layer 230, a plurality of bonding wire 240, an adhesive body 250 and a plurality of soldered ball 260.This no external leading pin type lead frame is to have a plurality of pins 210, and the outer end of those pins 210 is the edges that roughly are aligned in this adhesive body 250, a little projection or recessed.Usually those pins 210 are to be metal material, as copper, iron or its alloy, and can be by punching press or etching forming.Each pin 210 is to have a upper surface 211 and a lower surface 212.Wherein the lower surface 212 of each pin 210 is that definition has a routing district 213 and a catching region 214, respectively can be for the connection of those bonding wires 240 and the setting of those soldered balls 260.
Above-mentioned wafer 220 has an active surface 221 and an opposing backside surface 222, is formed with a plurality of first weld pads 223 on this active surface 221, its be these wafer 220 internal integrated circuit elements to external electrode.In the present embodiment, be formed with at least one second weld pad 224 on this active surface 221 of this wafer 220 in addition, those first weld pads 223 are middle positions that are arranged in this active surface 221, and this second weld pad 224 is peripheral positions that are arranged in this active surface 221.Owing to promptly leave the gap between those pins 210, can not cover this second weld pad 224, also needn't need extra boring so as circuit substrate.
Above-mentioned sticking crystal layer 230 is to be formed between the upper surface 211 of this active surface 221 of this wafer 220 and those pins 210, and the upper surface 211 that this sticking crystal layer 230 is bonding those pins 210 is corresponding to the position of those routing districts 213 with those catching region 214.Should can be the B rank colloid (B-stage adhesive by printing) of printing formation or glue brilliant adhesive tape (adhesivetape) by sticking crystal layer 230, can be pre-formed in this active surface 221 of this wafer 220 or the upper surface 211 of those pins 210.In the present embodiment, this sticking crystal layer 230 can be printed on this active surface 221 of wafer 220 earlier.
See also shown in Figure 3, be according to first specific embodiment of the present invention, the schematic diagram of the sticking crystal layer of this packaging structure on wafer. preferably, should sticking crystal layer 230 be to be patterning, so that should glue the bonding region of crystal layer 230 is to comprise those routing districts 213 of those pins 210 and the corresponding position of those catching region 214, so that those first weld pads 223 are not covered by this sticking crystal layer 230 with this second weld pad 224.Therefore, the shape of this sticking crystal layer 230 can help the connection of those bonding wires 240 and the setting of those soldered balls 260, more helps the upper-lower seal of this adhesive body 250 to those pins 210.Preferably, this sticking crystal layer 230 is the elastomers for low modulus, with resiliency supported those bonding wires 240 and those soldered balls 260, the effect that can promote soldered ball 260 stress buffers of BGA encapsulation.
Those above-mentioned bonding wires 240 are for routing formation and connect the routing district 213 of those first weld pads 223 of this wafer 220 to those pins 210, make the telecommunications signal of this wafer 220, power supply can be electrically connected to corresponding pin 210 smoothly with earth terminal.
Above-mentioned adhesive body 250; it is in conjunction with this wafer 220 and seals the upper surface 211 of those bonding wires 240, this sticking crystal layer 230, those pins 210, lower surface 212 and the side of those pins 210 between upper surface 211 and lower surface 212 except those catching region 214; and this adhesive body 250 has a plurality of counterbores 252; so that those catching region 214 that appear are recessed into relatively in a bottom surface 251 of this adhesive body 250 (promptly this packaging structure carries out the surface of surface engagement); to protect the bottom of those soldered balls, reduce and fall the ball probability.In the present embodiment, those counterbores 252 are that the mode of etching partially with lead frame forms, that is to say, those catching region 214 are originally thicker, occupy the predetermined position that forms those counterbores 252, after this adhesive body 250, those catching region 214 are etched partially (half-etching), so that this adhesive body 250 is formed with a plurality of counterbores 252 that can appear those catching region 214.In the present embodiment, this adhesive body 250 has more at least one inner fovea part 253 that is lower than this bottom surface 251, and those counterbores 252 are to be positioned at this inner fovea part 253, to strengthen the protectiveness to those soldered balls 260.
Moreover this adhesive body 250 is to comprise at least to seal this wafer 220 makes this wafer 220 with partially sealed this wafer 220 two kinds of exposed kenels of the back side 222 fully in conjunction with the kenel kind of this wafer 220.In the present embodiment, these active surface 221 areas of this wafer 220 be not less than this adhesive body 250 the surface engagement area 70 percent, so that this packaging structure is wafer 220 sizes encapsulation (CSP) kenel, can make the whole of those soldered balls 260 all be positioned at the below of this wafer 220 and should glue crystal layer 230 supports.
In addition, using existing printing reflow, ball contraposition reflow etc. to plant the playing skill art can be to be arranged at those catching region 214 with those soldered balls 260.Those soldered balls 260 can be same as the pin position that has known window type ball grid array encapsulation construction 200 now.
Therefore, above-mentioned ball grid array encapsulation construction 200 is to use does not have outer pin formula lead frame as chip carrier, can solve the problem that soldered ball 260 comes off easily, and can promote routing and the stability and the reliability of planting ball.In addition, can use and not have outer pin formula lead frame carrying and encapsulate the wafer 220 that has periphery and central welding pad simultaneously, become the BGA encapsulating products.
Seeing also shown in Figure 4ly, is the schematic cross-section according to the another kind of pin ball grid array encapsulation structure of wafer of second specific embodiment of the present invention.At the another kind of ball grid array encapsulation construction 300 of the present invention's second specific embodiment, mainly comprise a no external leading pin type lead frame, a wafer 320, one sticking crystal layer 330, a plurality of bonding wire 340, an adhesive body 350 and a plurality of soldered ball 360.Its main element is roughly the same with first specific embodiment.
This no external leading pin type lead frame has a plurality of pins 310.
This each pin 310 has a upper surface 311 and a lower surface 312, and each lower surface 312 definition has a routing district 313 and a catching region 314.
This wafer 320 has an active surface 321 and a back side 322, is formed with a plurality of first weld pads 323 and at least one second weld pad 324 on this active surface 321.
Should sticking crystal layer 330, be to be formed between the upper surface 311 of this active surface 321 of this wafer 320 and those pins 310.
Those bonding wires 340 are those first weld pads 323 and the corresponding routing district 313 of second weld pad 324 to those pins 310 that connect this wafer 320.
This adhesive body 350, be in conjunction with wafer 320 and seal the upper surface 311 of those bonding wires 340, this sticking crystal layer 330, those pins 310, lower surface 312 and the side of those pins 310 between upper surface 311 and lower surface 312 except those catching region 314, and this adhesive body 350 is to have a plurality of counterbores 352, so that those catching region 314 that appear are recessed into the bottom surface 351 in this adhesive body 350 relatively.In the present embodiment, the bottom surface 351 of this adhesive body 350 is to can be flat condition.
In addition, those soldered balls 360 are to be arranged at those catching region 314.By this, use and do not have outer pin formula lead frame, can solve the problem that soldered ball 360 comes off easily, and can promote routing and the stability and the reliability of planting ball as chip carrier.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (7)
1. pin ball grid array encapsulation structure of wafer is characterized in that it comprises:
One no external leading pin type lead frame, it has a plurality of pins, and the lower surface definition of each pin has a routing district and a catching region;
One wafer, it has an active surface, is formed with a plurality of first weld pads on this active surface;
One sticking crystal layer, it is formed between the upper surface of this active surface of this wafer and those pins;
A plurality of bonding wires, it connects the routing district of those first weld pads of this wafer to those pins;
One adhesive body, it is in conjunction with this wafer and seal the upper surface of those bonding wires, this sticking crystal layer, those pins, lower surface and the side of those pins between upper surface and lower surface except those catching region, and this adhesive body has a plurality of counterbores, so that those catching region that appear are recessed into the bottom surface in this adhesive body relatively; And
A plurality of soldered balls, it is arranged at those catching region.
2. pin ball grid array encapsulation structure of wafer according to claim 1 is characterized in that wherein said those counterbores are that the mode of etching partially with lead frame forms.
3. pin ball grid array encapsulation structure of wafer according to claim 1 is characterized in that wherein said sticking crystal layer is to be patterning, comprises those routing districts of those pins and the corresponding position of those catching region so that should glue the bonding region of crystal layer.
4. pin ball grid array encapsulation structure of wafer according to claim 1, it is characterized in that being formed with at least one second weld pad in addition on this active surface of wherein said wafer, those first weld pads are arranged in a middle position of this active surface, this second weld pad is arranged in a peripheral position of this active surface, and this second weld pad is not covered by this sticking crystal layer and those pins.
5. pin ball grid array encapsulation structure of wafer according to claim 1 is characterized in that wherein said sticking crystal layer is the elastomer for low modulus.
6. according to claim 1,2 or 3 described pin ball grid array encapsulation structure of wafer, this active surface area that it is characterized in that wherein said wafer be not less than this adhesive body the surface engagement area 70 percent so that this packaging structure is wafer size encapsulation (CSP) kenel.
7. pin ball grid array encapsulation structure of wafer according to claim 1 it is characterized in that wherein said adhesive body has more at least one inner fovea part that is lower than this bottom surface, and those counterbores is to be positioned at this inner fovea part.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610109599 CN100481407C (en) | 2006-08-14 | 2006-08-14 | Pin ball grid array encapsulation structure of wafer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610109599 CN100481407C (en) | 2006-08-14 | 2006-08-14 | Pin ball grid array encapsulation structure of wafer |
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| Publication Number | Publication Date |
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| CN101127332A true CN101127332A (en) | 2008-02-20 |
| CN100481407C CN100481407C (en) | 2009-04-22 |
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| CN 200610109599 Active CN100481407C (en) | 2006-08-14 | 2006-08-14 | Pin ball grid array encapsulation structure of wafer |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102184908A (en) * | 2011-04-26 | 2011-09-14 | 日月光半导体制造股份有限公司 | Advanced square flat pin-free encapsulating structure and manufacturing method thereof |
| CN107845618A (en) * | 2013-08-18 | 2018-03-27 | 乾坤科技股份有限公司 | Electronic system with composite base material |
| CN110660679A (en) * | 2018-06-29 | 2020-01-07 | 欣兴电子股份有限公司 | Method for joining electronic components |
-
2006
- 2006-08-14 CN CN 200610109599 patent/CN100481407C/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102184908A (en) * | 2011-04-26 | 2011-09-14 | 日月光半导体制造股份有限公司 | Advanced square flat pin-free encapsulating structure and manufacturing method thereof |
| CN107845618A (en) * | 2013-08-18 | 2018-03-27 | 乾坤科技股份有限公司 | Electronic system with composite base material |
| CN110660679A (en) * | 2018-06-29 | 2020-01-07 | 欣兴电子股份有限公司 | Method for joining electronic components |
| CN110660679B (en) * | 2018-06-29 | 2021-10-08 | 欣兴电子股份有限公司 | Method for joining electronic components |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100481407C (en) | 2009-04-22 |
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